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* flash_ec: stm32/npcx_uut: Set ec_boot_mode to off on exitstabilize-nocturne.10736.Bstabilize-atlas.10736.BWai-Hong Tam2018-05-301-5/+4
| | | | | | | | | | | | | | | | | | | | | The ec_boot_mode is used for flashing EC on STM32 and NPCX chips. The ec_boot_mode pin is an open-drain GPIO. Doing save/restore is destructive. For example, if DUT is unpowered (ec_boot_mode is "on"), doing save/restore will force it outputting to "on". We should not put it to the save/restore list. Instead, set it back to "off" on exit. BRANCH=none BUG=b:80305869 TEST=Ran flash_ec when DUT is unpowered -> failed as expected. Reran again when powered. Checked EC UART showed-up afterward. Change-Id: Iecf4b663fe9ae75a673a29a66505a4121d29888c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1073646 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: add support for enabling factory mode on bootMary Ruthven2018-05-304-22/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have determined the checks to run for board_is_first_factory_boot. This change updates cr50 to check for those conditions and enable ccd when the system determines that it is first boot in the factory. This will check that the board id is erased and the inactive image is a GUC image. The factory updates Cr50 from the GUC image, because those GUC images don't have support for everything they need to do in the factory. To determine that cr50 just recovered from that factory update, it will check that the GUC image is still in the inactive region and no board id is set. There are 2 images installed in GUC 0.0.13 and 0.0.22, so cr50 will check these versions. Future GUC images will have a field in the header declaring that they are a GUC image. I still need to create the GUC field in the header and check that in inactive_image_is_guc_image. Factory mode can't be enabled on deep sleep resume. It is only enabled after power-on reset or hard reset. This change also moves factory stuff into a factory_mode file instead of keeping it in board.c This adds 200 bytes. BUG=b:77543904 BRANCH=cr50 TEST=Verify factory mode is only enabled when cr50 recovered from reboot not deep sleep resume, 0.0.13 or 0.0.22 are in the inactive region, and the board id is erased. Change-Id: Ibece878049658493e8ad159121ada63d7a6f6b79 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1059864 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charge_state_v2: Add a hysteresis for under-voltage throttlingPhilip Chen2018-05-301-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | There is a potential loop: (1) We throttle AP when we see under-voltage. (2) VBAT bumps because throttling starts. From our experiment, AP throttling saves ~1A, and thus VBAT increases by ~80mV. (3) VBAT hasn't hit BAT_LOW_VOLTAGE_THRESH for BAT_UVP_TIMEOUT_US, so we stop throttling. (4) VBAT again drops below BAT_LOW_VOLTAGE_THRESH. (5) Go back to (1). So let's introduce a hysteresis to under-voltage throttling. We stop throttling only when we are confident that even if we stop throttling, the battery voltage will stay above BAT_LOW_VOLTAGE_THRESH. BUG=b:73050145, chromium:838754 BRANCH=scarlet TEST=manually test on scarlet Change-Id: Ic0c17a7d37d5d6ee38c7b19f9b65d17421e55cbc Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1070568 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* atlas: improve discharged battery handlingCaveh Jalali2018-05-301-82/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | we normally try to find out a few things about a battery (like charge level) before actaully applying charging power to it. when the battery is completely discharged, the controller on the battery can't respond as it is not self-powered. so, we have to avoid all operations that depend on the battery responding in the battery discovery/initialization path. as long as we report that a battery is present and it is not responsive, the charger task will enter ST_PRECHARGE which means it'll provide a "precharge" current to the battery to try to talk to it. this allows the battery's controller to report battery parameters allowing our charger task can do the right thing. BUG=b:79354967 BRANCH=none TEST=atlas now discovers the discharged battery reliably Change-Id: I5e5a3abda07508eb791b712fb2f9b9f5fe383e07 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1065492 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* sensors: Make sync driver more robustAlexandru M Stan2018-05-302-23/+41
| | | | | | | | | | | | | | | | | | | | | | Use a queue now for sync events, this will allow multiple interrupts to be called before the motion sense task executes. The events (including timestamps) get stored in a small queue. 8 events for the queue size should be plenty, most applications will have latency concerns anyway once we get a couple of queued up events. Also changed the init function to be a little bit more robust to race conditions. Added count argument to the "sync" simulation command to test the queue behavior. BRANCH=master BUG=b:73551961, b:67743747 TEST="sync 4" yields 4 events on the AP, whereas before it would only give the AP the last event. Change-Id: I9fcb1fb8b35eb5f8ffcc21afbfcb0f0d9bc33804 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1065149 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Fizz: Increase VR3 voltage to avoid boot failureDaisuke Nojiri2018-05-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | When V3P3A_EC is higher than V3P3A_DSW + 0.07V, system 3.3V rail is powered by V3P3A_EC. V3P3A_EC LDO will shut down when PU27 triggers OTP. This patch increases VR3 voltage by 3%, which gives us 3.399. This is more than the maximum voltage PU27 can provide, thus, V3P3A_DSW will win the voltage race (against V3P3A_EC). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:80114849 BRANCH=Fizz TEST=Boot Fizz Change-Id: Ieb6fbc4ad056a79dc1eef5eae7a91385575bac0b Reviewed-on: https://chromium-review.googlesource.com/1069594 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit d674a0e3cb15ee7f542c16f5930f0ef4a5f000ea) Reviewed-on: https://chromium-review.googlesource.com/1076707 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* system: Enable/Disable low power idle in run timePhilip Chen2018-05-304-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | We have enable_sleep()/disable_sleep() to enable/disable EC deep sleep mode in runtime. Here we introduce similar interfaces to enable/disable EC idle (sleep) mode. BUG=b:78792296 BRANCH=scarlet TEST=Confirm idle mode is enabled/disabled when enable_idle() and disable_idle() are called. Change-Id: I2484f08a066523441064968da99c47de9342ecf0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1072370 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> (cherry picked from commit c6b6626cdccef04b0ff203aaed0d84dbdcecf8b7) Reviewed-on: https://chromium-review.googlesource.com/1076708 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* yorp: enable interrupt for base accel sensorJagadish Krishnamoorthy2018-05-303-4/+19
| | | | | | | | | | | | | | | | | Configure the accel sensor gpio to interrupt. Enable CONFIG_ACCEL_INTERRUPTS and CONFIG_ACCEL_FIFO to activate FIFO mode. BUG=b:74932344 BRANCH=NONE TEST=On Yorp board, "accelinfo on 1000" should output BASE ACCEL values. Change-Id: Icecbbe604b32b6bd691558d2898896f6d1443f19 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1073645 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* fizz: Enable optimized SHA256/RSA in RO onlyNicolas Boichat2018-05-291-0/+6
| | | | | | | | | | | | | | | | Decreases verification time from 923ms to 785ms. Optimized version do not really help in RW, as they just increase the image size (which also increases verification time). BRANCH=fizz BUG=b:77608104 TEST=make BOARD=fizz -j, flash fizz, check timing. Change-Id: Ia8c36c35c0321c1995dc1cede7b27f7636037795 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1075908 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nocturne: Add pull ups on PD INTs.Aseda Aboagye2018-05-291-2/+2
| | | | | | | | | | | | | | | | | BUG=b:79619258 BRANCH=master TEST=Source on C0, verify can Sink on C1. Change-Id: Ic03a99d10cb207db0f8e892289575450809fce05 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1056867 Reviewed-by: Benson Leung <bleung@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 6aef8f22b4dfc2a7427bc3d8a2c5375323ca03ed) Reviewed-on: https://chromium-review.googlesource.com/1058889 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Fix PWM0 alternate pin definition.Aseda Aboagye2018-05-291-1/+1
| | | | | | | | | | | | | | | | | | | The pin was not configured correctly. BUG=None BRANCH=None TEST=Flash nocturne, verify PWM0 is functional. Change-Id: I7cd6c9b541af6df42d5c6a07bff3557ca4fd53c4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1055909 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 39751b29e4e0f30416ea70c58f21d0bd9d1c4e3b) Reviewed-on: https://chromium-review.googlesource.com/1058888 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* acpi: Add map for controlling USB port powerEmil Lundmark2018-05-292-0/+64
| | | | | | | | | | | | | | | | | | | Some devices have GPIO pins that control USB port power connected to the EC, so they cannot be toggled by ACPI. This patch adds a memory map between the EC and ACPI that can be used on such devices. It can hold the power state of up to 8 USB ports. Currently, only dumb power ports are supported. BUG=chromium:833436 BRANCH=fizz TEST=On a fizz that runs BIOS with EC_ACPI_MEM_USB_PORT_POWER mapped, check that both reads and writes are propagated. Change-Id: I413defcb9e4d234fea7f54d46b6b8a1a10efa31e Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1069273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* yorp: drive PPC EN_SNK from TCPC gpioJett Rink2018-05-293-9/+39
| | | | | | | | | | | | | Since the PS8751 is now driving the EN_SNK GPIO on the PPC, we cannot reset without a battery otherwise we will brown out the board. BRANCH=none BUG=b:78896495,b:78021059 TEST=verified with reworked board. Change-Id: Ibadf46de922c49f5fdd08c43991e71f852ff7600 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067711
* rsa: Further optimization of multiplications for Cortex-M0Nicolas Boichat2018-05-294-9/+60
| | | | | | | | | | | | | | | | | | | | In RSA, we often need to actually compute (a*b)+c+d: provide some assembly optimized functions for that. With -O3, 3072-bit exponent, lower verification time from 104 ms to 88 ms on STM32F072 @48Mhz. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=make BOARD=hammer test-utils test-rsa3, test on board Change-Id: I80e8a7258d091e4f6adea11797729ac657dfd85d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071411 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_port_power: Use same name for mode set functionEmil Lundmark2018-05-291-2/+2
| | | | | | | | | | | | | | | | | | | | | Dumb USB ports do not have the same notion of charge mode as smart ports. However, the header common/usb_charge.h declares a function for changing charge mode that the dumb USB port power implementation does not define. Instead, it defines a similar function with a different name, albeit with other allowed values for its second parameter. This patch makes the names the same so the function can be used by simply including the aforementioned header file. BUG=none BRANCH=fizz TEST=emerge-fizz chromeos-ec Change-Id: I87863f87f32f538cc1c723d9299afcc7353e1852 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1069272 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver/touchpad_st.c: call full initialization via touchpad_debugWei-Han Chen2018-05-292-1/+14
| | | | | | | | | | | | | | BRANCH=none BUG=b:70482333 BUG=b:78483107 TEST=manual test on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I57f96331d75a54c52f31305fee7090930ed845cd Reviewed-on: https://chromium-review.googlesource.com/1071314 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* driver/touchpad_st.c: add "st_tp_full_initialize"Wei-Han Chen2018-05-292-14/+63
| | | | | | | | | | | | | | | | | | | | This will be called after touchpad firmware is updated. "Full initialization" will trigger auto tuning. This function can also be called by console command `touchpad_st calibrate`. BRANCH=none BUG=b:70482333 BUG=b:78483107 TEST=manual Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I336dfa79ae5133750dc90ba07cbe9fc81318e84e Reviewed-on: https://chromium-review.googlesource.com/1049765 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* driver/touchpad_st.c: wait for event "controller ready" after resetWei-Han Chen2018-05-292-24/+83
| | | | | | | | | | | | | | | | | After resetting touchpad, we should wait for "controller ready" event before sending any commands to touchpad. BRANCH=none BUG=b:70482333 BUG=b:78483107 TEST=manual Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I7049579db23c083e518137055a8243fee400e924 Reviewed-on: https://chromium-review.googlesource.com/1071313 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_pd_protocol: Only print TCPC info if availableNicolas Boichat2018-05-281-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | tcpm_get_chip_info does not modify the parameter info if the function is not implemented on the given chip. This has a interesting side effect on Kevin, where, for whatever reason, info's value ends up being 1, and causes unaligned access exception: [0.039 TCPC p0 init ready] === PROCESS EXCEPTION: 06 ====== xPSR: 61000000 === r0 :00000000 r1 :28000000 r2 :00000001 r3 :00000000 r4 :00000000 r5 :00000000 r6 :00000000 r7 :00000000 r8 :200c60f4 r9 :00000000 r10:100c0c3c r11:00000000 r12:200c52ed sp :200c5320 lr :100a9c71 pc :100abd5a Unaligned mmfs = 1000000, shcsr = 70008, hfsr = 0, dfsr = 0 BRANCH=none BUG=none TEST=On ToT make BOARD=kevin -j; flash, kevin boots Change-Id: Ie7e758d5fb8c31180f36b073b635e54cc720a8a0 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1073179 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-05-287-7/+107
| | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rma_reset: add p256 ECC optionVadim Bendebury2018-05-281-38/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds RMA shared secret generation support using the p256 curve. It is not a simple shoe in replacement for the x25519 because of a different key representations. This new code uses openssl library for all calculations. A new option is being added to indicate that p256 is supposed to be used, the new server Key ID value is used for p256, which allows to pick the correct curve when parsing the previously generated challenge. BRANCH=none BUG=b:73296606 TEST=verified that the same secret value is generated on the client and server side when using either x25519 or p256 curves. ./rma_reset -t ./rma_reset -c <challenge generated by the previous command> ./rma_reset -t -p ./rma_reset -c <challenge generated by the previous command> Change-Id: I9b21b5ae389480d92f0f663fbb846b0f27b15de1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1073757 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: Increase PDU size to 4kNicolas Boichat2018-05-282-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Saves another ~1300 bytes of flash size, as the touchpad hashes can now be computed in blocks of 4K, instead of 1K. This costs 3K of SRAM, which we would not otherwise need on hammer. wand can only fit 2k PDU, so let's stick to that. Also, make sure that util/gen_touchpad_fw is regenerated when the configuration option changes (touchpad FW size, PDU size). Sadly, this will still break bisection from commit after this CL, to before this CL. BRANCH=poppy BUG=b:80167548 TEST=make buildall -j TEST=make BOARD=hammer/staff/wand/whiskers all tests -j TEST=Copy new staff image with old touchpad FW to DUT, verify that FW can be updated. Change-Id: Ic1763684da730dc986bbbcb3312088c8208c84b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070953 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* test/build.mk: Allow boards to specify test listsNicolas Boichat2018-05-289-25/+26
| | | | | | | | | | | | | | | | | Some tests cannot be built on some boards (not enough SRAM, unusual configuration, etc.). Instead of the long list of exceptions in test/build.mk that we currently use, allow each board (or chip) build.mk to set test-list-y, and only use the default list if it is unset. BRANCH=poppy BUG=b:80167548 TEST=make buildalltests -j Change-Id: I803c691f419451aad4396529302a4805cbe3f9b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1074572 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: system: print out message if reset cause is unknownDino Li2018-05-284-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The message will indicate the reset is caused by which program address of jump and link instruction. BRANCH=None BUG=b:79706847 TEST=No error message under these tests: cold reset, soft reset, and sysjump. On bip, declare ".get_cc = NULL" for it83xx tcpm driver. And get the following message. log: --- UART initialized after reboot --- [Reset cause: unknown] ... ===Unknown reset! jump from f824 or f826=== [0.004504 low power idle task started] ... Disassembly: 0000f814 <tcpm_get_cc>: f814: fc 00 push25 $r6, #0 ! {$r6, $fp, $gp, $lp} f816: 46 30 00 17 sethi $r3, #0x17 f81a: 58 31 8a cc ori $r3, $r3, #0xacc f81e: 95 04 slli333 $r4, $r0, #4 f820: 88 64 add45 $r3, $r4 f822: a0 da lwi333 $r3, [$r3 + #8] f824: a0 da lwi333 $r3, [$r3 + #8] f826: dd 23 jral5 $r3 f828: fc 80 pop25 $r6, #0 ! {$r6, $fp, $gp, $lp} Change-Id: I2eaf2ad95eb92c68ce6f8240ea6ec90ac2b4a5c9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1070387 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Nami: Set battery configuration per boardDaisuke Nojiri2018-05-263-10/+55
| | | | | | | | | | | | | | | | | This patch makes EC configure battery parameters differently based on OEM ID. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:79498660 BRANCH=none TEST=make BOARD=nami Change-Id: I782bd950f086bde13b2bc58656dc96e7c3f2aeb3 Reviewed-on: https://chromium-review.googlesource.com/1058718 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Cheza: Support host command over SPIWai-Hong Tam2018-05-263-1/+8
| | | | | | | | | | | | | BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran "ectool version" in userspace. Change-Id: Iee6816c669a18d1203b9f8f88857418185645503 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1005554 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* console_output: Clarify help text for CONFIG_CONSOLE_CHANNELNicolas Boichat2018-05-261-2/+5
| | | | | | | | | | | BRANCH=poppy BUG=b:35647963 TEST=N/A Change-Id: I85dd6553cf3ebace4e19813a308d0a024eba2915 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071412 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* test/utils: Fix memchr testNicolas Boichat2018-05-261-2/+2
| | | | | | | | | | | | | | | | | | memchr does not take into account end of string, so the test `memchr("123", '4', 8)` actually does a buffer overflow. On some boards, a '4' might be found in the 4 bytes that follow "123", and the test might fail. Fix another potential overflow as well. BRANCH=none BUG=none TEST=Flash test-utils to hammer, test passes Change-Id: I53755c0855bbd5b180801e4198341de1cec7b425 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071409 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rma_reset: prepare for expanding for p256 supportVadim Bendebury2018-05-261-60/+83
| | | | | | | | | | | | | | | | | | This is mostly a clean up and refactoring change, which will make it easier to extend rma_reset to supporting more EC curves. BRANCH=none BUG=b:73296606 TEST=verified that the same secret value is generated on the client and server side by running ./rma_reset -t ./rma_reset -c <challenge generated by the previous command> Change-Id: I15c010a4a62306bfaa56b97936318854b28a4945 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1073756 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rma_reset: allow building with debug optionsVadim Bendebury2018-05-261-2/+5
| | | | | | | | | | | | | | | When invoking make with DEBUG=1 add '-g -O0' to the compiler invocation to facilitate debugging with gdb. BRANCH=none BUG=b:73296606 TEST=verified that building with DEBUG=1 adds '-g -O0' to the compiler invocation. Change-Id: Idd80bd481091b91683200c78fe49dc7e9783a730 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1073755 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: Add a config option for enabling mouse LDNFurquan Shaikh2018-05-264-0/+9
| | | | | | | | | | | | | | | Not all boards using ITE83XX use mouse LDN. This change adds a config option to allow boards to explicity enable this device. Currently, this device is enabled only for glkrvp_ite and it83xx_evb. It is disabled for reef_ite and bip. Change-Id: I7149fd0cb35cc9f49f2b7b80f6c2deefe2edda55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1070785 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com>
* chip/it83xx: Clean-up ec2i pnpcfg settingsFurquan Shaikh2018-05-262-58/+54
| | | | | | | | | | | | | | | | | | This change gets rid of enum ec2i_setting and reorganizes pnpcfg_settings into multiple tables each for a logical device that needs to be configured. BUG=b:79897267 BRANCH=None TEST=Verified that bip still boots up. Change-Id: If7a756640c5e72b8494294495693589aaaa8fe74 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1070486 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com>
* console_channel.inc: Add more ifdef to reduce number of channelsNicolas Boichat2018-05-265-7/+18
| | | | | | | | | | | | | | | There are still more ifdef than can be added: this just takes out the low hanging fruits. BRANCH=poppy BUG=b:35647963 TEST=make buildall -j, see that we gain from 0 to 64 bytes on many boards. Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070948 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Makefile.rules: Add buildalltests targetNicolas Boichat2018-05-266-5/+31
| | | | | | | | | | | | | | | | | In rare cases, it is useful to be able to build tests for all boards: buildall only builds the main image, but -paladin builders also builds test cases for each board. Also remove/fix tests for boards that currently fail. BRANCH=none BUG=b:35647963 TEST=make buildalltests -j, wait a long time, tests pass. Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072218 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Add stubs and ifdefs to fix testsNicolas Boichat2018-05-263-0/+5
| | | | | | | | | | | | BRANCH=none BUG=none TEST=make BOARD=cheza tests -j Change-Id: Ifec4653bf71b870b616669f0a32ba528c1e38787 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072217 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ccd_config: Simplify open and passwordRandall Spangler2018-05-253-116/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow setting password from the AP, but not from USB. Remove the old password control logic, which is no longer needed. Allow open if: - Not explicitly blocked - Not blocked via FWMP - One of the following is true: - A password is set - Battery is removed (also doesn't require physical presence) - Dev mode is on, and request came from the AP Reduces cr50 binary by 152 bytes. BUG=b:79983505 BRANCH=cr50 TEST=manual, with a CR50_DEV=1 build ccd oops ccd lock ccd unlock -> fails gsctool -U -> fails from host gsctool -t -U -> fails from AP ccd oops ccd password foo -> fails from console gsctool -P -> fails from host gsctool -t -P -> works from AP ccd get -> confirms password set ccd lock ccd unlock foo -> works ccd lock gsctool -U -> works from host, if correct password supplied ccd lock gsctool -t -U -> works from AP, if correct password supplied ccd open foo -> works ccd lock gsctool -O -> works from host, if correct password supplied ccd lock gsctool -t -O -> works from AP, if correct password supplied ccd oops ccd lock (remove battery) ccd open -> works without physical presence (reattach battery) ccd lock gsctool -O -> works from host ccd lock gsctool -t -O -> works from AP, if dev mode is enabled Change-Id: I364b322d03db250e7dd140767d7a22dbb3ac1eef Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072957 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ccd_config: Ccd vendor command takes params structRandall Spangler2018-05-252-122/+95
| | | | | | | | | | | | | | This is needed so ccd_open() can see p->flags, for a subsequent change. No change to existing command behavior or binary size. BUG=b:79983505 BRANCH=cr50 TEST=gsctool -I still works Change-Id: I614d8c410e8bc55a5045e253469b2ec222078684 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072500 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* careena: Change LED colorsEdward Hill2018-05-258-76/+180
| | | | | | | | | | | | | Careena has non-PWM White/Orange LEDs. BUG=b:79704826,b:79894166 BRANCH=none TEST=make -j buildall Change-Id: Ie85de84fbd6e4ac4c6139d8407a7a25b5f6d5e7e Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072898 Reviewed-by: Jett Rink <jettrink@chromium.org>
* careena: Make GPIOs match hardwareEdward Hill2018-05-255-69/+16
| | | | | | | | | | | | | Update GPIO definitions for Careena to match hardware. BUG=b:79704826 BRANCH=none TEST=make BOARD=careena Change-Id: I755e5fd8123eefdfa8d30ca2314435c28340e488 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070989 Reviewed-by: Jett Rink <jettrink@chromium.org>
* grunt: Move common code to baseboardEdward Hill2018-05-2514-687/+1335
| | | | | | | | | | | | | | | | Move code that will be common to Grunt and Careena to baseboard to avoid duplication when creating the Careena board. Add Careena board files. These are currently just a copy of Grunt and will be modified for Careena next. BUG=b:79704826 BRANCH=none TEST=Grunt still boots ok. Change-Id: I6dd0035bdd62e92a7f3664120fc6ac3f23a0af4d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070988
* test: Make it possible to run rsa tests on hammer boardstabilize-10718.88.Bstabilize-10718.71.Bstabilize-10718.69.Bstabilize-10718.111.Brelease-R68-10718.BNicolas Boichat2018-05-243-2/+4
| | | | | | | | | | | | | BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=make run-rsa run-rsa3 TEST=make BOARD=hammer test-rsa3, test on board Change-Id: Id4bd8d5f550dbc6569d88ced114849b3b6411b2f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071410 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sn5s330: disable under voltage protectionJett Rink2018-05-242-1/+10
| | | | | | | | | | | | | | | | | | We need to disable under voltage protection because it prevents us from enabling the sink path when there is not Vbus on the connector side. We need to enable the sink path before we hibernate otherwise there is no power power to get to the charger which will then assert ACOK. Without this we won't wake up with the ACOK wake when USB power is inserted. BRANCH=none BUG=b:79948623 TEST=bip wakes with USB power insertion Change-Id: Idf16a92dacde63cf943ef68b0258b320d11de44c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Use lid angle to detect tablet modeDaisuke Nojiri2018-05-241-1/+1
| | | | | | | | | | | | | | | | | Tablet mode entry and exit are detected by a GMR sensor on Akali and by lid angles on the rest. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:77298177,b:77754921 BRANCH=none TEST=make BOARD=nami Change-Id: I637f7ab6dec779abbb5e7b7355bbbc665c86391d Reviewed-on: https://chromium-review.googlesource.com/1059936 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* ps8751: add source and sink path controlJett Rink2018-05-241-0/+4
| | | | | | | | | | | | | | PS8751 supports the TCPCI spec for controlling the power source and sink path, which is done through GPIO0 and GPIO1, respectively, by default. BRANCH=none BUG=b:78896495,b:78021059 TEST=verified TCPC drives PPC via reworked yorp board. Change-Id: Ie1de67495947b787ad9cd5aee0db3ca21bec5a10 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1047796 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* BMI160: EVE TOT divide by 0 error at bootSam Hurst2018-05-241-0/+1
| | | | | | | | | | | | | | | | | | | The BMI160 driver's init function generates a divide by 0 error by calling config_interrupt before initializing the range defined in struct accelgyro_saved_data_t. The explicit error is generated by macro BMI160_TAP_TH that's called in config_interrupt. BUG=b:80237518 BRANCH=None TEST=`make -j buildall` EVE boots from TOT Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: I8b7a4a7c63c973bcc639779ee54958f3702f1b36 Reviewed-on: https://chromium-review.googlesource.com/1071847 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* touchpad_elan: Ensure we at least have 1k of shared memoryNicolas Boichat2018-05-241-0/+3
| | | | | | | | | | | | | Debugging commands may request buffers up to that size. BRANCH=poppy BUG=b:63993891 TEST=make buildall -j Change-Id: I6dedfafc4e36d311026f9678e2cac99c85036ce0 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071311 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* touchpad_elan: Reload watchdog when programmingNicolas Boichat2018-05-241-0/+2
| | | | | | | | | | | | | | | | | | When using larger block sizes (e.g. 4096 bytes), the write operations take too long, which often causes a watchdog reset. Fix this by reloading the watchdog after programming every 64 bytes page. BRANCH=poppy BUG=b:80167548 TEST=Copy old touchpad FW to soraka, build staff, make sure FW can be updated. Change-Id: Ic6e7a3e3ef63877a4f2d5011e1fb0d49c04177a6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070952 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* octopus: moving hibernate code to baseboardJett Rink2018-05-243-45/+50
| | | | | | | | | | | | | bip also need to enable the sink path when going into hibernate BRANCH=none BUG=b:79948623 TEST=on bip, verfied that AC_OK, LID_OPEN, and POWER_BTN all wake the EC up. Change-Id: I2c1168f856cc45635b5c76f7ca409007fcf141cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1065203
* ppc: making driver non-constJett Rink2018-05-247-14/+14
| | | | | | | | | | | | | | | We need to update the driver based on the runtime board id, so we need to remove the const attribute. BRANCH=none BUG=b:78896495,b:78021059 TEST=build all -j Change-Id: I5f751c33cf4ec68a38aeb8644170df4987c87d7b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068030 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ppc: flush console regularly during console dumpJett Rink2018-05-242-0/+17
| | | | | | | | | | | | | I noticed data was getting dropped from my console output on bip. Adding the cflush fixes it. BRANCH=none BUG=none TEST=ppc_dump 0 on bip works Change-Id: Ib71cb37c4c8728a7ab958905d3b2627b8c163faa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070626
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