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* util: ec3po: Add presubmit check for ec3po.stabilize-smaug-7800.BAseda Aboagye2016-01-042-0/+26
| | | | | | | | | | | | | | | | | | | | | Added presubmit check to make sure that when any ec3po files are modified, the unit tests should be run as well. BUG=None BRANCH=None TEST=Touched a unit test file, tried repo upload and received an error about running unit tests. Ran run_tests.sh and all tests passed. Tried to repo upload again and this time it succeeded. TEST=Created a failure in one unit test, ran run_tests.sh and verified that the failure was caught and the CL wouldn't pass the presubmit check. Change-Id: I4df4a0fd1107292f693749188491f6286360f557 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/319211 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* keyboard: Fix kbpress after recent keyboard changeDouglas Anderson2016-01-041-1/+11
| | | | | | | | | | | | | | | After commit 98ab7484d331 ("keyboard: prevent races enabling/disabling kb scanning") kbpress was totally broken, which wasn't so good for FAFT. Fix it by making sure we go into polling mode for simulated keyboard presses. BUG=chrome-os-partner:48849 TEST=kbpress works Change-Id: Icd663c2ee7a184e6af4438368595087b35724a4f Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319586 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* wheatley: Add CONFIG_LTO definition to reduce FW size.stabilize-7797.BMulin Chao2015-12-302-1/+2
| | | | | | | | | | | | | | | | | | | Add CONFIG_LTO definition to reduce the size of FW image. Modified drivers: 1. board.h: Add CONFIG_LTO definition. 2. header.c: Add __keep keyword to prevent linker ignore header during optimization. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I6205af37572a68f35f90dbd9b28d86230533ca8b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/319799 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: add debug assert flagKevin K Wong2015-12-301-1/+0
| | | | | | | | | | | | | | | Restore debug assert flag which was previously removed due to limited code space. BUG=none BRANCH=none TEST=make buildall Change-Id: I9617b1221bc6217e8f8ed745ea0ce12418233440 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/319606 Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: npcx: Fix build for ARM host boardsShawn Nematbakhsh2015-12-301-2/+2
| | | | | | | | | | | | | | | | | ecst is used at build / link time, so it should be compiled for the build machine architecture, not the architecture of the host board. BUG=chromium:567232 TEST=Verify 'cros_sdk ... cros_run_unit_tests --board=oak' passes with CL:319256. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic7f6aa989d0760eda1fe64221e41d3230c9ab9b9 Reviewed-on: https://chromium-review.googlesource.com/319633 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chell / chell_pd: Use power-optimized GPIO defaultsShawn Nematbakhsh2015-12-242-14/+22
| | | | | | | | | | | | | | | | | Pull floating pins high, don't duplicate external pull ups, and make a few other minor changes. BUG=chrome-os-partner:48109 TEST=Verify chell continues to boot and S5 power is reduced to ~5.5 mW. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c Reviewed-on: https://chromium-review.googlesource.com/319165 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: add LED supportMary Ruthven2015-12-226-1/+214
| | | | | | | | | | | | | | | Implement LED control for lucid with red, blue, and green LEDs. BUG=chrome-os-partner:48661 BRANCH=none TEST=make sure lucid builds Change-Id: I97ed56daa8fdb40daf8ab06e53913dcff2e41dea Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319224 Commit-Ready: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: implement fast chargingMary Ruthven2015-12-222-0/+150
| | | | | | | | | | | | | | | | | Use custom charging profile to enable charging at a faster rate. BUG=chrome-os-partner:48662 BRANCH=none TEST=load on lucid and charge at room temp. Use "chgstate" command to verify that battery current matches the expected fast charging current for the given temp range and voltage. Change-Id: Ie508d29db091593ff2cfda9d135c73f6a3de5a9a Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319493 Commit-Ready: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: remove some unnecessary features to save spaceAlec Berg2015-12-221-0/+2
| | | | | | | | | | | | | | Remove ADC watchdog and i2cscan console command to save flash space. BUG=none BRANCH=none TEST=make BOARD=lucid Change-Id: I3da8a13fdd962041ccdc830cb1b9b5803917bc2b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319611 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Move rand_bytes implementation from tpm2 to chip/g.nagendra modadugu2015-12-223-21/+35
| | | | | | | | | | | | | BRANCH=none TEST=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: Ic7a850fdf2594ac1981237edda8dceb16cc7cbe6 Reviewed-on: https://chromium-review.googlesource.com/319155 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Enable lower core CLK for power consumptionCHLin2015-12-213-27/+33
| | | | | | | | | | | | | | | | | | | | | Support lower core CLK frequency and configure the baudrate parameter of console UART for current core CLK. Modified drivers: 1. clock.c: Support lower core CLK frequency. 2. uart.c: Add baudrate setting for differenct core CLK. 3. clock_chip.h: Set default core CLK to 16MHz. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Id83ecf92c19bec508ec84e2d271d7e1fa278774f Signed-off-by: CHLin <chlin56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/319030 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: adc: Add support for DMA continuous modeShawn Nematbakhsh2015-12-215-31/+150
| | | | | | | | | | | | | | | | | | | Add support for continuously writing ADC samples to a circular buffer. CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an appropriate sized buffer must be passed to adc_read_all_channels(). BUG=chromium:569994 TEST=Manual on snoball. Verify 'adc' continues to function (single mode). With pending commit, verify that continuous conversion interrupt is called at appropriate frequency and values look consistent. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e Reviewed-on: https://chromium-review.googlesource.com/318505 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: adds the SPI master driverEwout van Bekkum2015-12-214-1/+231
| | | | | | | | | | | | | | | | | Adds the SPI master driver with support for both SPI masters with support for using GPIOs as chip selects or using the hardware's dedicated chip selects. Note this has not been enabled in the cr50 board. BRANCH=none BUG=none TEST=verified through use of the SPI_FLASH module on cr51 Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317329 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Include host/console commands based on HAS_TASK_HOSTCMD/CONSOLEShawn Nematbakhsh2015-12-182-1/+10
| | | | | | | | | | | | | | | | | | | | | Don't build a table of host / console commands if the HOSTCMD or CONSOLE task is not present. This saves space in the .hcmds / .cmds section and allows the linker to prune command handler functions which will never be called. BUG=chrome-os-partner:41959 TEST=Verify ec.RO.flat shrinks on snoball and glados_pd, and remains the same size on chell and samus. Also verify basic functions are still working on snoball and glados_pd. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I79975c18ec1d87fedda8d1f299f30ffc43c24f69 Reviewed-on: https://chromium-review.googlesource.com/319112 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Lars: Update battery settingsRyan Zhang2015-12-181-9/+10
| | | | | | | | | | | | | | Update battery settings from battery spec. BUG=chrome-os-partner:48571 BRANCH=lars TEST=`make -j BOARD=lars`, OS and EC shutdown normally without AC, Charging normally. Change-Id: I4b8fad8ab993f2ea5190898088bd1bd8c2bd7abb Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/318611 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* ec3po: Add graceful exit.Aseda Aboagye2015-12-172-43/+63
| | | | | | | | | | | | | | | | | | | | | | | | The console and interpreter are usually killed by KeyboardInterrupt whether or not it's run standalone or by servod. This commit tries to make the exit graceful by closing pipes, file descriptors, and exiting each process. BUG=chromium:570526 BRANCH=None TEST=Run ec3po standalone and hit Ctrl+C to kill it. Observe no traceback and no leftover processes. TEST=Repeat above test, but inside servod TEST=cros lint --debug util/ec3po/console.py TEST=cros lint --debug util/ec3po/interpreter.py TEST=python2 -b util/ec3po/console_interpreter.py TEST=python2 -b util/ec3po/console_interpreter.py Change-Id: Ia151b9ede8adf7f8dec6c07277f62d097c13e63e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/319252 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
* Refactor crypto subcommands into their own python module.nagendra modadugu2015-12-173-7/+14
| | | | | | | | | | | | | BRANCH=none TEST=tpmtest.py passes BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: I48f426176f17c57c723104d19c963b228f16d985 Reviewed-on: https://chromium-review.googlesource.com/318915 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Implement USB according to Programmer's GuideBill Richardson2015-12-171-213/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a rewrite of the Cr50 USB Device Control Endpoint implementation, using the instructions in the DWC USB 2.0 OTG Programmer's Guide (such as they are). Some of the major differences: * Not every USB interrupt indicates the receipt of an incoming packet. Many merely provide updates on packet transfer status, transaction stages, or other activity. We handle those cases correctly. * We may need to start a new Control transaction at any point, even in the middle of an existing transaction. * Large IN data transfers can be handled with one interrupt by chaining multiple together. * Logical separation of the phases of each transaction (Setup, Data, Status). That said, while this CL matches the Programmer's Guide fairly closely, that Guide is pretty crappy and this is just the first commit. There is still a fair amount to do (marked with comments and bug reports). However, it works at least as well as the previous version and is much closer to what the supplier claims is the correct implementation. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') We also connected this device to Windows, and Mac laptops (and a Chromebook) and used a USB bus analyzer to monitor the behavior. It works on machines those, too. Change-Id: Ic515ea83e217a8d0552d61ac5eb19693661fcd15 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/318864 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* nds32: start_irq_handler() use system stackDino Li2015-12-163-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [symptom] The 'vboot_hash_start()' always return busy error and variable 'in_progress' got a strange value(should be 0 or 1). 'start_irq_handler()' causes scratchpad overflow in first context switch. It must be called after SP switch to system stack in ISR. NOTE: The scratchpad is still also need more size even if 'start_irq_handler()' is using system stack. following is detail: 1. uint32_t scratchpad[19] 0x81d34 ~ 0x81d7f [__task_start:] 2. /* put the dummy stack pointer at the top of the stack in scratchpad */ addi $sp, $r3, 4 * 18 -> SP 0x81d7c 3. syscall push return address (-4) -> SP 0x81d78 [ISR:] 4. push r15, fp, lp, and sp (-0x10) -> SP 0x81d68 5. push r0 ~ r5 (-0x18) -> SP 0x81d50 [__switch_task:] 6. /* save ipsw, ipc, r6, r7, r8, r9, r10 on the current process stack */ (-0x1C) -> SP 0x81d34 Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. hash done. 2. console command 'taskinfo'. 3. the scratchpad does not overflow after first context switch. Change-Id: If5d89ff5c945a777010492fcfb54bf41f434ed69 Reviewed-on: https://chromium-review.googlesource.com/317468 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Kunimitsu: enable power threshold checking in power upli feng2015-12-161-0/+2
| | | | | | | | | | | | | | | | | | In 0% battery case, if the charger can provide power at least 15 Watt(CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW), will allow system to boot up. BUG=chrome-os-partner:48339 BRANCH=none TEST=Verified in Kunimitsu system, system with 0% battery can boot up normally once charger power is 15 Watt. Change-Id: I0c7b23d4ac1e7bd2807ceeb068fc9018a99a03c4 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318891 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: increase retry count in power upli feng2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | During power up, system will wait at most CHARGER_INITIALIZED_TRIES delay to check if battery percentage or negociated charger power can meet minimum requirement. In some cases, it takes longer time(observed negotiated to min power took 2 seconds). So increase CHARGER_INITIALIZED_TRIES from 10 to 40 to give total 4 seconds delay. BUG=chrome-os-partner:48339 BRANCH=none TEST=Verified in Kunimitsu system, negotiation to 5V@3A is done within retry/delay. Change-Id: I18c5fc676076f8d37d0a5360543f54aa85f48f77 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318652 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: fix coding error in charge_prevent_power_on()li feng2015-12-161-1/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make -j buildall Change-Id: If60902ab0176435b41f70ca11e0f73b430b65fe5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318650 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Revise FIFO SRAM settingsBill Richardson2015-12-161-38/+89
| | | | | | | | | | | | | | | | | | | | | | | This allocates more space for FIFO buffers, according to the instructions in the Programmer's Guide. Many more comments and some slight refactoring was added to explain the configuration more clearly. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I1a870a4b1dc628729f7cd1b80bab7ec6dfd11f37 Reviewed-on: https://chromium-review.googlesource.com/318262 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Lars: Update LED settingsRyan Zhang2015-12-161-8/+12
| | | | | | | | | | | | | LEDs are high active now. BUG=chrome-os-partner:48552 BRANCH=lars TEST=`make -j BOARD=lars`, LEDs blink normally. Change-Id: I9a96d4347ebfaa698c762f3c55db0c8d2133ec73 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/318603 Reviewed-by: Shawn N <shawnn@chromium.org>
* Chell: modify led setting for led test command.Bruce2015-12-161-2/+2
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=the test command can control led. Change-Id: Iaae49f35953448e2472196ba9b6411fe8d9487b4 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/318165 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: fix retry counter checking in power upli feng2015-12-161-1/+1
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=`make buildall -j` Change-Id: If015f655c4ccaba147fb886452d5fe756ec54425 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/317644 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Fix uninitialized variable.Shaunak Saha2015-12-161-2/+4
| | | | | | | | | | | | | | | This patch fixes a reported error for an uninitialized return variable. BUG=none TEST=Build and Test EC. BRANCH=none Change-Id: I43a6678049070ef1ee6c71dfbac1fcb21de88957 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://chromium-review.googlesource.com/317352 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Lars: Add ALS console-commandRyan Zhang2015-12-161-0/+1
| | | | | | | | | | | | | To make debug easier. BUG=None BRANCH=lars TEST=`make -j BOARD=lars`, OS can boot up normally Change-Id: I9f73342e3201fef79b99426939f1a2b308be3cb7 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/318143 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: Implement GPIO mode for KBS pins and fix gpio_set_level()Dino Li2015-12-144-2/+37
| | | | | | | | | | | | | | | | | | 1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for keyboard scan function. 2. Critical section for gpio_set_level(). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console commands: gpioset, gpioget, and version. Change-Id: I8edae122525e6dcebaa3489116642d8e48520569 Reviewed-on: https://chromium-review.googlesource.com/318112 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: To config register 'GCR' in gpio_pre_init()Dino Li2015-12-142-2/+2
| | | | | | | | | | | | | | | | | | | | The double-mapping modules(CIR, BRAM, SSPI, PECI, and UART) won't work if GPD2 pin's status is low and GCR register's setting is at default. We move 'IT83XX_GPIO_GCR = 0x06;' to 'gpio_pre_init()' to prevent this case. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Register 'GCR'=0x6 after init. 2. GPD2 is low and UART works. Change-Id: I71b4436ab6c2a8f9e77e0d6f5116e5327a3167e7 Reviewed-on: https://chromium-review.googlesource.com/318131 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* keyboard: prevent races enabling/disabling kb scanningDouglas Anderson2015-12-141-26/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | keyboard_scan_enable() is called from several contexts. From a skim of the code I found: * keyboard_lid_change(), which is called from HOOK_LID_CHANGE * enable_keyboard(), which is called from HOOK_CHIPSET_RESUME * lidangle_keyscan_update(), which is called from motion_sense_task. * check_for_power_off_event() which is called from power_handle_state() which is called from chipset_task. * power_button_interrupt(), which is an interrupt * power_button_change_deferred(), which is a deferred function So, ummm, it's probably not a good idea to do a read-modify-write of a variable without any locking. ...and then to act on the resultant state in various different contexts. It's presumed that's just what happened to poor Julius. Julius found himself in the unfortunate situation where he resumed his device (with the power button, I believe) and that everything worked (including reading the battery state and including the accelerometer) but the keyboard didn't work. Now, it should be noted that Julius is a little strange. Well, maybe he's not strange and maybe just the way he uses his laptop is strange. He uses his veyron_minnie device as a smart keyboard/trackpad. Said another way: it is in tablet mode but is docked to an HDMI monitor, the screen is face flat on his table, and he uses the builtin keyboard and trackpad. Nobody else that I know does this. It's pretty darn cool, but I just don't think anyone else would think of it. Anyway, that might have something to do with how he reproduced this. ...or it might not. He does that a lot and hasn't seen the problem before now. Anyway, I managed to reproduce a number of problems similar to what poor Julius saw by adding a 200ms sleep in keyboard_scan_enable() after we read disable_scanning_mask but before we did anything to it (I skipped the sleep if this happened to be one of those people who was calling from interrupt). Since there appears to be no spin_lock_irqsave() in the EC, let's just have the EC use atomic operations to mess with its masks. Then we'll leave all heavy lifting to the task. This requires thinking through the task code a bit. Conflicts: common/keyboard_scan.c ...due to commit 6112f20679df ("common: keyboard_scan: Add items to .bss.slow.") in ToT. BRANCH=ToT BUG=chrome-os-partner:48470 TEST=Poke a lot with power button and lid; NTF. Change-Id: I61b906505100186b0ca2c48e7b1a7ffaaa8a7d3e Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317896 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 98ab7484d331a78fced870b58b4d82e79e2e0f4e) Reviewed-on: https://chromium-review.googlesource.com/318292
* Cr50: clean up usb_init()Bill Richardson2015-12-141-38/+49
| | | | | | | | | | | | | | | | | | | | | | No new functionality, just a little refactoring and general cleanup of the USB initialization steps. BUG=chrome-os-partner:34893 BRANCH=none CQ-DEPEND=CL:317376 TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: Ia6922acf82a793759870a61217562f4e63608a80 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317319 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* stm32: Don't use HSI48 clock for chips which don't support itShawn Nematbakhsh2015-12-113-3/+6
| | | | | | | | | | | | | | | | | | stm32f03x and stm32f070 officially do not support an HSI48 clock, so configure our 48MHz clock using HSI8 and PLL. BUG=chromium:568717 BRANCH=None TEST=Verify snoball 1us timer is accurate and we can execute approximately 48 million NOPs in a second. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347 Reviewed-on: https://chromium-review.googlesource.com/317459 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: USB: Add stubs for additional EP0 interruptsBill Richardson2015-12-111-19/+71
| | | | | | | | | | | | | | | | | | | | | | No new functionality, just adding stub handlers for some additional USB interupts that we'll eventually need to deal with. BUG=chrome-os-partner:34893 BRANCH=none CQ-DEPEND=CL:317354 TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: I805ac00432c31735d2904227c5d19ad53cfa7ccb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317376 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Cleaner API for USB_DECLARE_IFACE callbacksBill Richardson2015-12-113-32/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | The control endpoint (EP0) can receive some Setup packets that are specific to individual Interfaces. The USB_DECLARE_IFACE macro is used to register the callbacks that an interface implementation provides to handle those Setup packets. This change cleans up the callback API a bit, so that we don't have to export the internal workings of the Cr50's EP0 interrupt handler. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: I9ac22f6a74f360f201c58e9ef39e3576834578a8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317269 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* ALS: wake up ALS task when switched to RW modeJagadish Krishnamoorthy2015-12-111-0/+14
| | | | | | | | | | | | | | | | | | | | Enabling of ALS is done during resume hook. During EC sw sync, resume hook is not called and hence ALS task wont run. Adding init hook to wake up the ALS task. BUG=chrome-os-partner:48418 BRANCH=none TEST= On Kunimitsu board, ensure sw sync is enabled. In OS, cat /sys/bus/iio/devices/iio:devicesx/in_illuminace_input should output valid value and not zero. Change-Id: Iba1a3ab2cf7bfc2d8aa36cf9bb9b762f398882c3 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/317030 Commit-Ready: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Add a few more symbolic names for constantsBill Richardson2015-12-113-7/+55
| | | | | | | | | | | | | | | | | | | No functional changes, just making the code prettier. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: I1301c035eafc054567c1f317a80539197fcdeef4 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317354
* honeybuns: enable updates over USB-PDstabilize-smaug-7731.BVincent Palatin2015-12-112-0/+29
| | | | | | | | | | | | | | | | | | | | | | | Enable the RSA verification of the RW partition, so we are using the RW partition by default and the USB PD flashing VDMs are able to update the firmware over the Control Channel. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:47823 TEST=run the following sequence on a Samus connected to Honeybuns : ectool --name=cros_pd infopddev 1 ectool --name=cros_pd flashpd 5 1 ec.RW.bin ectool --name=cros_pd version and see the honeybuns properly updated and running the new version. Change-Id: I8f1612ee153a412620bae5822d1b354ad8072916 Reviewed-on: https://chromium-review.googlesource.com/312998 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* Cr50: tweaks to debug output and a comment or twostabilize-7729.BBill Richardson2015-12-101-26/+104
| | | | | | | | | | | | | | | | | | | | No functional changes, just some additional debug stuff that's not normally compiled. BUG=none BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: I32b4944c01006f2e9c8cdb2e732a4b1710a60e19 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317560
* cr50: fix calculations determining the image typeVadim Bendebury2015-12-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | The startup message includes the type of the image it is running (RO vs RW currently). cr50 reports RW as RO, which this patch fixes. This issue requires a bit more attention though: first, the RO type can be deduced at compile time. Second, RW and RW_B should be accommodated. RW_B should also be accounted in other places in the code where now only two options are considered: RO vs RW. BRANCH=none BUG=chromium:567938 TEST=the startup message now reads: --- UART initialized after reboot --- [Reset cause: power-on] [Image: RW, cr50_v1.1.4162-f1e71a6-dirty 2015-12-08 16:39:00 vbendeb@eskimo.mtv.corp.google.com] Change-Id: I0db2db4413a13ebe915e1081b47cd4a6f85cbdd8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316922 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add ability to include two identical RW sections in the EC imageVadim Bendebury2015-12-099-8/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical EC image includes two similar in their functionality subsections, RO and RW. CR50 has a small RO subsection, all it does - detects a proper RW image to run and starts it up. To provide for reliable firmware updates, the CR50 image needs to include two RW sections, while the code is running from one RW subsection, the other one can be upgraded. This patch adds the ability to generate two identical RW sections, mapped half flash size apart, and include them into the resulting EC image. To keep things simple the previously existing RW section's name is not being changed, while the new (identical) RW section is named RW_B. Two configuration options need to be defined to enable building of the new image type: CONFIG_RW_B to enable the feature and CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the flash. A new rule added to Makefile.rules allows to generate a different lds file from the same source (core/cortex-m/ec.lds.S) by defining a compile time variable to pick a different base address for the rewritable section, when RW_B is built. BRANCH=none BUG=chromium:43025 TEST=as follows: - make buildall -j still succeeds - verified that regular CR50 image starts successfully - modified chip/g/loader/main.c to launch RW_B first, re-built and re-run the image, observed on the console: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv cr50 bootloader, 20151118_11218@80881, no USB, full crypto Valid image found at 0x00084000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com] [0.001148 Inits done] This FPGA image has no USB support Console is enabled; type HELP for help. > [0.002212 task 2 waiting for events...] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (note that the image base address is 0x840000, which is RW_B). Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316703 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* glados/chell: Do not pull-up RSMRST to PCH in hibernateDuncan Laurie2015-12-092-0/+4
| | | | | | | | | | | | | | | | | | | If deep sleep S5 is supported RSMRST to the PCH should not be high when the PCH is in S5 unless the board is sequencing out of deep sleep and S5 state. Therefore, ensure RSMRST is low when the EC goes into hibernate. This assumes deep sleep S5 is employed. A more appropriate fix is to honor RMSRST state prior to going into hibernate state. Without this change the behavior on certain platforms do not sequence out of S5 when coming out of hibernate. BUG=chrome-os-partner:48133 BRANCH=none TEST=tested on a failing EVT chell board at the factory Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317070 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ec3po: Add setup script.Aseda Aboagye2015-12-082-0/+41
| | | | | | | | | | | | | | | | | | | | | | | This commit adds a setup script for the ec3po package. This is necessary such that ec3po can be included as a part of ec-devutils. BUG=chrome-os-partner:46054 BRANCH=None TEST=Update the ec-devutils ebuild to install the ec3po package. sudo emerge ec-devutils; `python -c 'import ec3po'; print ec3po` in the chroot. Verify that ec3po is installed in the site-packages. TEST=Verify that interpreter and console modules are exported in the package. CQ-DEPEND=CL:316479 Change-Id: I5c8856b530936dc4ce3b09e38802f1e015c4576b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/316701 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org>
* ec3po: Clean up and stylistic changes.Aseda Aboagye2015-12-085-113/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It was brought to my attention that there were some issues with the ec3po code. This commit addresses those issues raised. - executable bits dropped from __init__.py and interpreter.py. - sys.argv[1:] is now passed into console.py:main(). - Added blank lines at top of header. - Removed dummy exception class (MoveCursorError). - Added name of modules in the logger, so that it's not just 'root' when included in other modules. BUG=chrome-os-partner:46054 BRANCH=None TEST=./util/ec3po/console_unittest.py -b TEST=./util/ec3po/interpreter_unittest.py -b TEST=cros lint --debug ./util/ec3po/console.py TEST=cros lint --debug ./util/ec3po/console_unittest.py TEST=cros lint --debug ./util/ec3po/interpreter.py TEST=cros lint --debug ./util/ec3po/interpreter_unittest.py Change-Id: I00db368906958d1089c3662eb253be23f81cc70c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/316479 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org>
* use _DEFAULT_SOURCE for newer glibcMike Frysinger2015-12-082-2/+4
| | | | | | | | | | | | | | | Newer versions of glibc have moved to _DEFAULT_SOURCE and away from _BSD_SOURCE. Trying to use the BSD define by itself leads to warnings which causes build failures. BRANCH=none BUG=None TEST=precq still works Signed-off-by: Mike Frysinger <vapier@chromium.org> Change-Id: Ice24b84dc6a540695fc7b76e8f22a4c85c301976 Reviewed-on: https://chromium-review.googlesource.com/316730 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* README: Add link to quick-build instructionsShawn Nematbakhsh2015-12-071-0/+4
| | | | | | | | | | | | | BUG=None TEST=Pass gmail spellcheck BRANCH=None Change-Id: I4a1101fabdacd58a321cb819ac6719a3ce2e0945 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316432 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Lars: Add Keyboard COL2 InvertRyan Zhang2015-12-072-1/+3
| | | | | | | | | | | | | | | | | The silego in Lars is supposed to be inverted. This CL can not be compiled because of 'MODULE_PWM_KBLIGHT'. I didn't modify this to prevent a merge conflict from https://chromium-review.googlesource.com/#/c/316351/ in ToT. BUG=chrome-os-partner:48205 BRANCH=lars TEST=None Change-Id: Iee6fa996440287fd1f1af456f9842d810597bd23 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/316360 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: i2c: Track controller status for repeated startShawn Nematbakhsh2015-12-071-3/+29
| | | | | | | | | | | | | | | | | If we haven't sent a stop condition, make note of that, and send a repeated start next time. BUG=chrome-os-partner:48294 BRANCH=None TEST=Verify "ectool i2cxfer 1 0x25 1 2" succeeds on glados. Also verify `i2cscan` on EC console succeeds. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id45bfc6540dc1cc3a3d1e9f6916a238bce5ae33f Reviewed-on: https://chromium-review.googlesource.com/316022 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Revert "mec1322: i2c: Assume read-no-write transactions are repeated start"Shawn Nematbakhsh2015-12-071-7/+16
| | | | | | | | | | | | | | | | This reverts commit 4421d75c24738a524ed840935d4495cf1a75a3c3, which was breaking the 'i2cscan' console command. BUG=chromium:561143 TEST=None BRANCH=None Change-Id: If266b73c1009e131ec9c01dcd5d3b923bd981da5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316021 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lars: Fix buildShawn Nematbakhsh2015-12-071-1/+1
| | | | | | | | | | | | MODULE_PWM_KBLIGHT no longer exists. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I801bdf153771f77a4c2704df82a62a7d21e25625 Reviewed-on: https://chromium-review.googlesource.com/316451
View Lorry Controller Status