summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* ec-fans: Make fans configuration const by default.Andrew McRae2019-11-0219-15/+26
| | | | | | | | | | | | | | | | It was pointed out to me that the fans config list was non-const, but there is only 2 boards that require non-const configuration, so by default make it const, but allow an override. BRANCH=none BUG=None TEST=EC compiles, make tests, buildall Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025 Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* mt_scp/gpio: set GPIO_ALT_FUNC_NONE to GPIO_ALT_FUNC_DEFAULTYilun Lin2019-11-021-1/+3
| | | | | | | | | | | | | | | | The common EC code expects that if the func parameter passed to gpio_set_alternate_function() is -1 (GPIO_ALT_FUNC_NONE), that the pin will be reassigned to a GPIO function. TEST=make buildall BUG=b:143710991 BRANCH=kukui Change-Id: I6ba3d3d323e4fb99617ce4baaec662ceab094ad4 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893026 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "usbc: update CRCReceiveTimer"Sam Hurst2019-11-022-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1092c786f7876745ec0d68dd52284d252e1abee5. Reason for revert: <Several Fluffy tests failed due to this CL> Original change's description: > usbc: update CRCReceiveTimer > > Shorten the CRCReceiveTimer and document that either the pe send or > error function will get called in response to a prl_ send message. > > BRANCH=none > BUG=none > TEST=build; > > Change-Id: Icc43886cadfdcd67c943b25aebfdfb55b2693ade > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1825514 > Tested-by: Denis Brockus <dbrockus@chromium.org> > Commit-Queue: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Edward Hill <ecgh@chromium.org> Bug: none Change-Id: I2051b6c2f3f36d5d0612f24ba08f9843f9487f66 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894765 Reviewed-by: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* servo_v4: The polarity is based on the flags in SRC DTS modeWai-Hong Tam2019-11-023-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port in SRC DTS mode, it should not perform the polarity detection. The polarity is predetermined, as a board-specific setting. In the servo case, the polarity is based on the flags. This CL changes the protocol layer to check the port in SRC DTS mode and call the board-specific function board_get_src_dts_polarity() for the polarity. BRANCH=servo BUG=b:140876537 TEST=Configed servo as srcdts and unflipped direction: > cc srcdts cc2 Verified the power negotiation good and detected the correct polarity: > pd 1 state Port C1 CC2, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e Without this patch, it detected the wrong polarity and the power negotiation failed: > pd 1 state Port C1 CC1, Ena - Role: SRC-DFP State: SRC_DISCOVERY, Flags: 0x10608 Change-Id: I32c5dfffeaeb20a21db1417f3a1c98566b7f5e38 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891255 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* max32660: add I2C board address support, refactorJerry Bradshaw2019-11-022-424/+287
| | | | | | | | | | | | | | | | | | | | | | Adds support for a second I2C slave address, modeled on the same feature in the STM32-F4. Also refactored the I2C slave interrupt handler to streamline host read and writes, reduced I2C slave state variable usage, and make better use of I2C slave interrupt types. BRANCH=none BUG=none TEST=Slave tested with EC CMDs and board cmds sent from a custom written EC HOST using another MAX32660 device as an I2C Master. Tested with Raspberry PI that emulates EC HOST and board commands. Change-Id: I575a283a9a6735b16f4b6ac0fcb0aa2d1984ee92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1864791 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Tested-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* fmap: Remove CONFIG_RO_STORAGE_OFF from EC_RO offsetScott Collyer2019-11-011-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The value CONFIG_RO_STORAGE_OFF was being used to define the area_offset for EC_RO. This means that when flashing EC_RO from the DUT, the bootloader region is not being written. This is causing issues when doing RO updates (like in dogfood programs) as the full data section is not being loaded properly. In the case of npcx, the previous bootloader would be coupled with the new RO image, This CL removes CONFIG_RO_STORAGE_OFF from the area_offset field of EC_RO so that both the header and RO image are written. BUG=b:142907781 BRANCH=None TEST=Tested with a script that mimics auto update by writing an older version of FW to RO, then uses the DUT to flash just the RO with a new version and then compares the RO that was read to what was supposed to be written. This script would always fail before, but with this CL now passes multiple iterations. Change-Id: I3d7af7de0dc1dfd24d6d304a8271290e6c6eb94e Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1885107 Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-01204-533/+549
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* kindred: Modify EC fan control tableben.chen2@quanta.corp-partner.google.com2019-11-011-7/+7
| | | | | | | | | | | | | | | | | | | | | Modify EC fan control table by Thermal request. BUG=b:136567378 BRANCH=Master TEST=Manual Verify fan behavior by thermal team. Remove DPTF and check fan speed with temperature. When temperature over 25 degree, the fan start working. When temperature over 55 degree, the fan full run. And check system shutdown when temperature over 75 degree. Change-Id: I1f91eea6e98e65bd93f62c33a52ff3d91558abc1 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* juniper: add new battery for next juniper buildTing Shen2019-11-012-0/+28
| | | | | | | | | | | | | | BUG=b:143334368 TEST=1) See "[0.064610 found batt:PANASONIC]" on EC console 2) battery readings looks reasonable BRANCH=master Change-Id: I5a7091ea7db6ff3f524ac5bd99bc6a7d3bdcd181 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880771 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* puff: Scrub config and generate hardware structuresAndrew McRae2019-11-014-27/+157
| | | | | | | | | | | | | | | | | | Verify all CONFIG items in board/puff/board.h. Generate the necessary hardware reference structures in board.c Generate the minimum GPIO references in order to build cleanly. v2: Remove some of the fan and temp sensors config. BUG=b:143564865 TEST=Compile and link EC image. Change-Id: Ibc073718ad1c85705ab460d96202799f8c4fea06 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893013 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* atlas: initialize max charge currentCaveh Jalali2019-11-011-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | the isl923x is strapped to initialize the charge current to 3A. however, its default max charge current limit is 3.072. when the charge current exceeds the current limit, the charger asserts PROCHOT which means the AP gets throttled to 400MHz until the charge_state machine updates the current limit. on an unlocked system, we don't change the charge limit from its default, so we never apply the 5% derating needed to avoid the isl923x from over-currenting the charger. the solution is to over-ride the 3A strapping of the isl923x by appling a 5% derated current request early when we boot up. BUG=b:141533503 BRANCH=none TEST=atlas no longer boots into PROCHOT on 5v3a charger Change-Id: Idba55edf7b1c0eec36b6583aa0b276c3cb1f0c89 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889312 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* volteer: Add manual power sequencingKeith Short2019-11-014-1/+220
| | | | | | | | | | | | | | | As backup if board driven power sequencing doesn't work, implement EC controlled power sequencing on Volteer. BUG=b:140556273 BRANCH=none TEST=make buildall TEST=make BOARD=volteer VOLTEER_POWER_SEQUENCE=y Change-Id: I62e30e5f153085e2e6c26005a77e2e1abe981b0a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881754 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gpio: add function to set a GPIO and log to the consoleKeith Short2019-11-012-0/+19
| | | | | | | | | | | | | | Add a common function gpio_set_level_verbose() to generate a cprints() statement prior to changing the GPIO pin level. BUG=none BRANCH=none TEST=make buildall Change-Id: I6b3a9e89604fb721d8fa5208ce96df9e9414cdf9 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893633 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-015-20/+74
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* atlas: fix charger selection messagesCaveh Jalali2019-11-011-2/+2
| | | | | | | | | | | | | | | this corrects the printed text and switches from CPRINTF to CPRINTS for time stamping. BRANCH=none BUG=none TEST=buildall passes Change-Id: I4647ef4348a44d3eb433afa96ad04f2483899bc0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886034 Commit-Queue: Sean Abraham <seanabraham@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tcpci: fix tcpc_alert error messageCaveh Jalali2019-11-011-2/+2
| | | | | | | | | | | | | | this adds a missing newline to the end of a CPRINTF format string. BRANCH=none BUG=none TEST=builall passes Change-Id: I4a380983bce107af7a0f6eb7304bb9090c5b621a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886033 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* tglrvp: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-11/+11
| | | | | | | | | | | | | | | | Modified the gpio.inc file to reflect the new changes done for the alternate function parameter. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I3eed1b825f390581975d44734b62b7a73a2acb98 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880975 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-0114-50/+95
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* Cleanup: Renaming pd_is_ufp to pd_partner_is_ufpAyushee2019-11-014-7/+13
| | | | | | | | | | | | | | | | pd_is_ufp function returns port partner CC status, renaming it to pd_partner_is_ufp to avoid ambiguity between host and port partner's CC status. BUG=b:141971044 BRANCH=None TEST=make buildall -j Change-Id: I19da8c8470db134e438271b92918994d77e4eb5d Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894119 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* usbc: Get current DP pin mode and CC stateAyushee2019-11-016-18/+89
| | | | | | | | | | | | | | | | | | | | | | | | To configure Intel virtual mux and burnside bridge retimer, current DP pin mode, cc state and the type of the cable is required. Hence, implemented a board level function that returns the current DP pin mode and added a function that returns the type of cable inaccordance to the cable vdo response. Also added a new version to USB_PD_CONTROL host command, to return the DP mode, cc_state and the cable type BUG=b:141971044 BRANCH=None TEST=Verifed with ectool usbpd command on CPU console, able to get correct CC state, pin mode and cable type Pin mode: USB:0x0 (No DP) DP cable:0x4 (Mode:C) USBC dock:0x8 (Mode:D) Change-Id: If87ae6b77e5fa2ceaa22319dfa2d2c802460edfa Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835030 Reviewed-by: Keith Short <keithshort@chromium.org>
* cometlake: cleanup power signal namesKeith Short2019-10-314-25/+26
| | | | | | | | | | | | | | | Add X86 prefix to the Comet Lake signals names for consistency with other Intel APs. BUG=none BRANCH=none TEST=make buildall Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* docs: ccd_cr50 fix headingsMary Ruthven2019-10-311-18/+18
| | | | | | | | | | | BUG=none BRANCH=none TEST=view docs Change-Id: I68ba4ffcb09942fe80d6c0406bf946795114eb54 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894130 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Use actual utilities dependency, not phony targetStefan Reinauer2019-10-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | This prevents the EC binaries unnecessarily being recreated every time you run make on the target. BUG=none TEST= make BOARD=scarlet [..] make BOARD=scarlet *** 11460 bytes in flash and 10252 bytes in RAM still available on scarlet RO **** *** 24140 bytes in flash and 10252 bytes in RAM still available on scarlet RW **** BRANCH=none Change-Id: I6cabb7d1b7512162c8b24c7664bafc7d98c5eda5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1851106 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com>
* drallion_ish: Remove CONFIG_GMR_TABLET_MODE_CUSTOM from drallion ishMathew King2019-10-312-6/+0
| | | | | | | | | | | | | | | | GMR_TABLET_MODE_CUSTOM is needed on arcada_ish due to a hall sensor which is too sensitive. Drallion should not have the same problem. BUG=b:140311300 TEST='emerge-drallion chromeos-ish' ec log shows tablet mode events BRANCH=none Change-Id: Idde16dafb52c3da51b111031ed5144f5c428d62e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893185 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cr50: Move 30 ms ec_rst delay to after falling edgeMathew King2019-10-311-15/+9
| | | | | | | | | | | | | | | Platfoms with closed EC require at least 30 ms to put the EC in reset. In order to support flashrom over CCD move this 30 ms delay from before the deassertion of EC reset to after assertion. BUG=b:142100741 TEST=Run flashrom over CCD without failures BRANCH=cr50 Change-Id: Ia8bb207a4407733f3cf77c52ac9063cc7bec3f94 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881752 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: add ceil_for function to math_util.hLeifu Zhao2019-10-311-0/+11
| | | | | | | | | | | | | | | | | | During code review for tgl rvp enablement, found it is better to add ceil_for function to math_util.h. BUG=none BRANCH=none TEST=successfully compile for arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Iee350881c88e923c7a70317a9b8d75ee6104dba0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873349 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* tcpm/fusb302: implement low power modeTing Shen2019-10-312-1/+11
| | | | | | | | | | | | | | | | | Implement tcpc_low_power_mode to reduce power consumption in G3. BUG=b:142760774 TEST=measure power consumption on jacuzzi. verify that power consumption is reduced by 3~4mW see b:142760774 comment 3 for more detail. BRANCH=master Change-Id: I04436d3baaa97b7c049ae3f3d9a9510e5a2024d9 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880773 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* pd_protocol: add hard_reset_complete_timerCaveh Jalali2019-10-312-37/+69
| | | | | | | | | | | | | | | | | | | | | | | | certain chargers have noisy CC lines which can prevent overly sensitive TCPCs from detecting a bus idle state. this means the TCPC will not send out messages such as hard_reset. this condition may not clear which means our pd_task() will retry sending hard_resets. although we specify a "timeout" for the event loop in this state, the timeout can be ignored by the event wait when there are pending events. this gets us into a tight event processing loop that starves the watchdog! the solution is to add an explicit timeout timer when processing the PD_STATE_HARD_RESET_SEND state. BUG=b:134702480 BRANCH=none TEST=no more EC watchdog on affected systems Change-Id: I1ae871f5d8fc99f6906ddd18741bbf68dcb6e935 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889431 Tested-by: Nitin Kolluru <nkolluru@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-3125-25/+27
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* system.c: reset statics for testingCaveh Jalali2019-10-312-0/+14
| | | | | | | | | | | | | | | | | | | | this adds a function to reset the state information generated by system_common_pre_init() for testing scenarios that need to call it multiple times. on the EC, main memory (.data + .bss) is reinitialized across sysjumps, so this happens automatically, but we can't really do that from unit tests. so, add a function to reset the relevant static variables to emulate main memory getting reinitialized. BRANCH=none BUG=b:142031466 TEST=make buildall passes Change-Id: I1f65902c21ab6fc17c32388795cfef19c84d8cc8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1855644 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hatch_fp: Configure unused GPIO pins.Ravi Chandra Sadineni2019-10-311-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | By default, STM32F4 pins are configured as inputs, except some JTAG pins which can impact the power consumption of the device in different power modes because pins are very sensitive to external noise in input mode I/O. To avoid extra I/O current, all pins should be configured as analog input (AIN); in this mode the Schmitt trigger input is disabled, providing zero consumption for each I/O pin. For more info please look at "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY"("AN4365") section 1.2.6 and STM32F412 reference manual section 7.3.12. BUG=b:130561737 BRANCH=None TEST=Flash bloonchipper and measure power before and after. fpenroll and fpmatch works fine. Change-Id: I85d76589be22b892c81680763cfb263746004a80 Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1883127 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* trembyle: temperature sensor changesDenis Brockus2019-10-301-11/+51
| | | | | | | | | | | | | | | Changed when thermistors will be valid Changed temperature limits for CPU BUG=b:143611482 BRANCH=none TEST=manual verification on trembyle Change-Id: Iab72844ebee21356a045e57d97ce253f3d23abef Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1890917 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-3029-45/+81
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* Remove GPIOs for eSPI VW sleep signalsAbe Levkoy2019-10-302-11/+0
| | | | | | | | | | | | | | | | | | Remove non-interrupt GPIO configurations for SLP_S3_L and SLP_S4_L for dragonegg and tglrvpu_ite. The GPIO names thus defined are only referenced in the rest of the codebase if virtual wires are not enabled for those signals, in which case the GPIOs will be configured as interrupts. BUG=b:143288478,b:139553375 TEST=Build dragonegg and tglrvpu_ite BRANCH=none Change-Id: I7b59bb315e333ab62257f206159d95a6d3c6a0ca Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881757 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* PCH_PLTRST_L: Use appropriate config optionAbe Levkoy2019-10-308-15/+6
| | | | | | | | | | | | | | | | | Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because that is the configuration option used to enable to use of the the GPIO signal name thus defined. Remove the now unused CONFIG_HOSTCMD_PLTRST_IS_VWIRE option. BUG=b:139553375,b:143288478 TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite BRANCH=none Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* tablet_mode: ensure that tablet mode is always initializedJett Rink2019-10-301-47/+54
| | | | | | | | | | | | | | | | | The board init should ensure that tablet_mode is always set so the rest of the subsystems can rely on this. We assume notebook mode if we don't have any input from the GSR 360 hall sensor. That matches the default up in AP firmware as well. BRANCH=none BUG=b:141494453,chromium:1010343 TEST=put arcada at 200 degrees and see that tablet mode it initialized correctly. Change-Id: I4e23d3ba149f9add84f9667a5af676803cf50da5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1845779 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Revert "smart_battery: add smbus error checking support"Caveh Jalali2019-10-305-269/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit daccb3adea9394116d7ab2c807e4a360cb5a93a1. Reason for revert: <INSERT REASONING HERE> broke USB-C charging. all we get now is: 2019-10-30 01:26:15 New chg p0[49.441303 CL: p0 s2 i500 v5000] 2019-10-30 01:26:16 C0 st5 2019-10-30 01:26:16 C0 Req [1] 5000mV 3000mA 2019-10-30 01:26:16 New chg p0[50.305144 CL: p0 s0 i500 v5000] 2019-10-30 01:26:16 C0 HARD RST RX 2019-10-30 01:26:16 C0 st4 2019-10-30 01:26:16 New chg p0[50.354280 CL: p0 s2 i500 v5000] 2019-10-30 01:26:17 C0 st5 2019-10-30 01:26:17 C0 Req [1] 5000mV 3000mA ... Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> Bug: b:138415463 Change-Id: Ibd8a512dd6d43cca95628f698e7a66a695b7fc59 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889435 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* battery/mm8013: Fix reversed WANT_CHG flag.Yilun Lin2019-10-301-3/+3
| | | | | | | | | | | | | battery_flag()'s return code is 0 on success. TEST=see allowing charge in command battery BUG=None BRANCH=kukui Change-Id: I26d6a69deadca1ad5a0f5d7faaa031ed0dffe78d Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888004 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* usb_pd_protocol: disable VBUS when suspending PD taskCaveh Jalali2019-10-301-0/+1
| | | | | | | | | | | | | | when we suspend a port's PD task, we should also shut off VBUS on that port. BUG=b:143330980 BRANCH=none TEST=ectool pdcontrol suspend now shuts off VBUS Change-Id: Iba20586e07514276c29a91e567bf6abde8f97056 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886450 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* make_linux_ec_commands_h.sh: Fail gracefully outside of chrootStefan Reinauer2019-10-291-0/+6
| | | | | | | | | | | | | | | | | Running make buildall outside of chroot will fail because the make_linux_ec_commands_h.sh script expects CROS_WORKON_SRCROOT to be set. Exit gracefully with a message if it is not. BUG=none TEST=make buildall outside of chroot BRANCH=none Change-Id: I838a3b551405575650f46281598a466d008222e8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1851107 Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* puff: Initial EC files for puffAndrew McRae2019-10-297-0/+957
| | | | | | | | | | | | | | | Skeleton EC files for puff. Enough GPIOs and functions defined to allow files to build, but don't expect anything to work or be complete. BUG=b:143454886 TEST=None, code compiles. Change-Id: I4badd1741cf04c71b4ae687afe9d06d8e0b8a813 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880784 Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd: fix an unit in log message.Pi-Hsun Shih2019-10-292-2/+2
| | | | | | | | | | | | | | From USB PD spec, the voltages encoded in PDO is in 50mV units, not 50V units. BUG=None TEST=None BRANCH=none Change-Id: I20ea308c954fc407b313dd3923ab0112b520108c Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880777 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hatch: Enable ANX7447 internal pu/pd on AUX for hatch variantsScott Collyer2019-10-294-0/+4
| | | | | | | | | | | | | | | | | | This CL enables the config option CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD for hatch variants that have the ANX7447 TCPC. BUG=b:124410548 BRANCH=None TEST=On hatch, connect external monitor,usb device or CCD cable to type-c port0. Verifed each worked as expected. Change-Id: I7cd6ce65dac42dffd41a0f75fc844b634d7d312f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1788333 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Nitin Kolluru <nkolluru@google.com> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* make: Add utils to help messageCraig Hesling2019-10-291-0/+1
| | | | | | | | | | | BRANCH=none BUG=none TEST=make help Change-Id: I912e54927e3e307180e8d80e78105fdfdd6c9dfb Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880322 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* fpsensor: Clean up headers and MakefilesTom Hughes2019-10-2812-42/+63
| | | | | | | | | | | | | | We no longer need the various levels of indirection since the source files are public. BRANCH=none BUG=b:137848573 TEST=make buildall -j Cq-Depend: chrome-internal:2005128 Change-Id: I7483c233dc54c5dbf2907441365feffc9ae9f0a5 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869533
* fpsensor: Add OWNERS for driver/fingerprint directoryTom Hughes2019-10-281-0/+1
| | | | | | | | | | | BRANCH=none BUG=b:137848573 TEST=make buildall -j Change-Id: I1dc902cb74ef902444b43642af52e28394296ae3 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869532 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* fpsensor: Copy BEP and libfp source files from private repoTom Hughes2019-10-2822-34/+1802
| | | | | | | | | | | | | | | | | | These source files have been approved to be released publicly (see http://b/137848573#comment20). There were no source changes in the move, except for small changes to the Makefiles to adjust for the move. For future "git blame"s refer to the history of the files in the private repo if you need to access the full history. BRANCH=none BUG=b:137848573 TEST=make buildall -j Cq-Depend: chrome-internal:2005127 Change-Id: I1a809ac5a4d95637840ee47712e9c80a40a445c5 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869531
* trembyle: Add GPIO_USB_C0_IN_HPD and IOEX_USB_C0_DATA_ENDenis Brockus2019-10-281-0/+2
| | | | | | | | | | | | | | | | | These are not defined and are needed for MB USB-C to run at USB3.0 speeds BUG=b:143460349 BRANCH=none TEST=make buildall -j TEST=Verify USB3.0 when manually asserting these high Change-Id: I8a73b25521a5bcf217b6e0a0d881f00555ceabe9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884268 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* volteer: Remove ISR todoAbe Levkoy2019-10-281-1/+0
| | | | | | | | | | | | | | There is no need to change the ISR for RSMRST, so remove the todo. BUG=b:139553375 TEST=make buildall BRANCH=none Change-Id: I3ccc5c80432aa085f8492b96446456bf0ef1c1a4 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881755 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* test: remove unneeded hack for test waitingJett Rink2019-10-281-6/+0
| | | | | | | | | | | | | | | | | Now that the test time is deterministic (CL:1860474), we do not need to ensure that a task is woken up because it always will be now. BRANCH=none BUG=none TEST=ran usb_prl 100 times without issue. Change-Id: I88d0f705a05f192934b87704483ee2a83eb052ad Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879514 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
View Lorry Controller Status