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* Remove unused definev1.10.0Gwendal Grignou2016-09-091-6/+0
| | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=compile Change-Id: I5eaa69817b16312c32ce546ce20b0a716cc71ba1 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383072 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 00a0353a8860ec362d94c2ac3924142426fe06ac) Reviewed-on: https://chromium-review.googlesource.com/384015 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* g: override RBOX fuses for correct POR behaviorBill Richardson2016-09-091-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sanity tested by powering up cr50 and checking for correct RBOX register values. This patch is mainly to address RBOX debounce issues and key blocking while EC_RST is asserted. A debounce value less than 4, sometimes causes initial pin values to be incorrectly detected. The latter is related to https://chromium-review.googlesource.com/#/c/357590/. As RBOX controls cannot be selectively bypassed (they have to be bypassed as a group), all registers are set up in this patch BUG=chrome-os-partner:54602 BRANCH=None CQ-DEPEND=CL:377621 TEST=manual on Kevin Do three-finger salute, enter recovery mode. Change-Id: Ieb82c94fa33888ead359a77bf77981567998b3fc Signed-off-by: Timothy Chen <timothytim@google.com> Reviewed-on: https://chromium-review.googlesource.com/372001 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* driver: bmp280: Add rangeGwendal Grignou2016-09-093-4/+28
| | | | | | | | | | | | | | | | | | | | Data from the sensor (in Pa) does not fit in 16 bits. Add set_range/get_range to allow the AP to set the precision. For pressure around ~1000 hPa, we need to right shift by 2 bits. BUG=chrome-os-partner:57117 BRANCH=reef TEST=Check data is not truncated anymore: > accelrange 4 Range for sensor 4: 262144 (Pa ~= 2621 hPa) > accelread 4 Current data 4: 24030 0 0 Last calib. data 4: 24030 0 0 (x4 = 961.2 hPa) Change-Id: I3f7280336e5120d903116612c9c830f4150d2ed7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382323 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reef: Add FIFO supportGwendal Grignou2016-09-092-45/+51
| | | | | | | | | | | | | Add FIFO to allow ARC++ sensors. BUG=b:27849483 BRANCH=reef TEST=Check cros_ec_sensor_ring is loaded. Change-Id: Idca3a324530a29f33face8784dcf260fdafce83f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382322 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: rk3399: Minimize resume latency on short suspendShawn Nematbakhsh2016-09-081-0/+25
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:56605 BRANCH=None TEST=Manual on kevin, modify code to force CHECK_ABORTED_SUSPEND() condition to be true for each respective case, verify AP resumes successfully. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib3ec3c287c14ea2b9b410171a173c38c9385a90f Reviewed-on: https://chromium-review.googlesource.com/378078 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* npcx: rtc: Write RTC reg twice to ensure non-volatilityShawn Nematbakhsh2016-09-081-9/+9
| | | | | | | | | | | | | | | | | | TTC must be written twice, otherwise the value will be lost on EC reset, even if VBAT stays stable. BUG=chrome-os-partner:57010 BRANCH=None TEST=On kevin, run 'rtc set 55555' then trigger cold reset through servo. Run 'rtc' on subsequent boot and verify timing ticks did not reset to zero. Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382654 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pwm: PWM is disabled when duty is set to max valueSam Hurst2016-09-082-4/+3
| | | | | | | | | | | | | | | | | | | | | | The CTR was set to 1 less than the max PWM value, so when the DCR is set to max PWM value, duty goes to zero. The bug is fixed by setting CTR to PWM max vlaue. BUG=chrome-os-partner:57052 BRANCH=None TEST=Manual on terminal. > pwmduty 1 raw 0 Setting channel 1 to raw 0 1: disabled > pwmduty 1 raw 65535 Setting channel 1 to raw 65535 verified that screen didn't blank Change-Id: I10885d382f1bd252a5e7355da99dc00bd876e29f Reviewed-on: https://chromium-review.googlesource.com/381632 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* COMMIT-QUEUE.ini: Change builders to no-vmtest-pre-cq.Aseda Aboagye2016-09-081-3/+5
| | | | | | | | | | | | | | | | | | | | (Re-attempt of https://chromium-review.googlesource.com/#/c/372325/) Really, we only care if the chromeos-ec package unit tests fail and not if the VMTest or ImageTest stages fail. Those test stages don't actually test aganist our EC changes anways, so it's kind of a waste of time to run them. Besides, that's what FAFT is for. BUG=chromium:642503 BRANCH=None TEST=cbuildbot --remote chell-no-vmtest-pre-cq Change-Id: I1b4b7fc68a9f8a943f6f5ef3d8b169264c95359e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/381106 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org>
* Cr50: Flag unofficial images in the version stringBill Richardson2016-09-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We often find it handy to build test images that are unlocked or have special powers. To avoid confusing these with production images, this adds a "DEV/" to the version string: "make BOARD=cr50" looks like this: > version Chip: g cr50 B2 Board: 0 RO_A: * 0.0.9/0088a3eb RO_B: 0.0.8/710d4375 RW_A: * 0.0.6/cr50_v1.1.5261-4848d7e RW_B: 0.0.6/cr50_v1.1.5261-4848d7e [...] "CR50_DEV=1 make BOARD=cr50" looks like this: > version Chip: g cr50 B2 Board: 0 RO_A: * 0.0.9/0088a3eb RO_B: 0.0.8/710d4375 RW_A: 0.0.6/cr50_v1.1.5261-4848d7e RW_B: * 0.0.6/DEV/cr50_v1.1.5261-4848d7e [...] BUG=chrome-os-partner:55557 BRANCH=none TEST=make buildall; also.. Build both with and without the CR50_DEV=1 environment variable. Observe that the version string differs even if nothing else does. Change-Id: Ifee9fbf922c2bbb40a1a9d0a716d2d11aa0d3ec2 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382851 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: Better download time for sysjump by increasing clock freq.Mulin Chao2016-09-083-0/+40
| | | | | | | | | | | | | | | | | | | | | In order to improve the performance of sysjump, the CL increases the clock freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps into the other region successfully, the clock freq is restored to the default value (15MHz) in main routine. Modified sources: 1. clock.c: Add clock_turbo for speed up clock's freq to max. 2. clock_chip.h: The declarartion for clock_turbo. 3. system.c: Speed up clock rate before downloading FW. BRANCH=none BUG=chrome-os-partner:34346 TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/381799 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* driver: kionix: Add set_valueGwendal Grignou2016-09-071-74/+45
| | | | | | | | | | | | | | | | Put the common code for set_[data_rate|range|resolution] in the same function BUG=b:27849483 TEST=tested on Cyan, save 128 bytes on minnie. BRANCH=none (cherry picked from commit 79c74a2a662cdc6d9ea0d8729ca4fb1d641400e5) Reviewed-on: https://chromium-review.googlesource.com/379099 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: Ie66f64a478ad73c2a46129a664f2a6c60c5157bc Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/379544
* Cr50: AP console is always available via CCDBill Richardson2016-09-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Input to the EC UART console is restricted by default so that casual passers-by can't type random commands to it through the case-closed debug connection. However, there's no need to restrict the AP UART console, since it's entirely under the AP's control. This CL leaves the AP console enabled by default whenever the CCD cable is connected. It will be disabled when the AP is powered down or while servo is attached, but enabled otherwise. BUG=chrome-os-partner:55322 BRANCH=none TEST=make buildall, test on Cr50 hardware Use the "ccd" command to see and modify the UART console settings, and the "devices" command to observe how things change when servo is connected and things are powered up and down. Change-Id: I5cc453bc60473269e22112cf49f61495733abb10 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382152 Commit-Ready: Bill Richardson <wfrichar@google.com> Tested-by: Bill Richardson <wfrichar@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* common: Add TABLET_MODE hook.Gwendal Grignou2016-09-079-1/+32
| | | | | | | | | | | | | Add a hook to act when the a device is going in tablet mode and back. BUG=chromium:606718 BRANCH=kevin TEST=Test with evtest that an event is sent to the AP. Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380412 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin: Use 32.768KHz input clock for improved RTC accuracyShawn Nematbakhsh2016-09-073-4/+11
| | | | | | | | | | | | | | | BUG=chrome-os-partner:56949 BRANCH=None TEST=Run stopwatch for 10 minutes, verify 'rtc' time difference matches stopwatch. Change-Id: I3aed54b17433f9acfe284e9c8846d4e1e7c1a199 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/381571 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* cr50: provide build mode for signing with fobVadim Bendebury2016-09-074-3/+2206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't really have the ability to build the latest signer yet, but this should not stop us from being able to build a properly signed image using the ec makefiles. As a stopgap measure the suggestion is to keep the latest signer binary in ~/bin/codesigner in chroot, then with this patch applied invoking make with CR50_DEV=1 will cause the proper sighner used and proper signing procedure followed. The signed targets need to be built in series to avoid concurrent use of the signer fob, an addition dependency is being added to enforce that. BRANCH=none BUG=chrome-os-partner:55557 TEST=ran make as follows: CR50_DEV=1 make BOARD=cr50 touched the fob when requested, uploaded the generated build/cr50/ec.bin on a kevin-tpm2 using usb_updater, and observed it boot properly with the new version. Change-Id: Ia9494bdc60b4bd3b8e5e09cbcbd8b27409c739d2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/376885 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Driver: BD99955: Enable trickle chargingVijay Hiremath2016-09-062-12/+20
| | | | | | | | | | | | | | | | | | | | | | | Enabled the trickle charging mode by setting the VPRECHG_TH_SET register[0x18H] to board specific battery voltage minimum value. When the battery voltage drops below the battery voltage minimum value, trickle charging is enabled. BUG=chrome-os-partner:56684 BRANCH=none TEST=Manually verified on Reef. Drained the battery below battery voltage minimum value. On plugging in the charger, State Machine Status register CHGSTM_STATUS [0x00h] is 0x01 which indicates, current state of the charger state-machine is in Trickle-Charge condition. Change-Id: Ic4b985c71ff68ea4f5ab22e18feab03d776ec134 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/376939 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: Add ec_parse_panicinfo tool to parse binary panicinfoNicolas Boichat2016-09-065-110/+173
| | | | | | | | | | | | | | | | | To be able to parse binary panicinfo from feedback reports, we need a host tool: - Move panicinfo generic parsing functions to a separate C file - Create a new host utility to parse panicinfo BRANCH=none BUG=chromium:643062 TEST=base64 -d | ec_parse_panicinfo Change-Id: Idd8560a2894f270d0ab3a9f654c333135759e57f Reviewed-on: https://chromium-review.googlesource.com/379639 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "cr50: remove internal pull up on DIOM0"Mary Ruthven2016-09-064-23/+6
| | | | | | | | | | | This reverts commit 5e6da91fe86301d276b452a660139c27c3786a82. Change-Id: I65b37c087a86fab06f6e23e895ceee2ae2def5ee Reviewed-on: https://chromium-review.googlesource.com/381160 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: I2CS TPM: Added routine to write to HW fifo a word at a timeScott2016-09-053-2/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reads of the TPM fifo by the Host are done in chunks of up to 63 bytes at a time. The existing routine used to copy data read from the TPM layer to the I2CS fifo operates one byte at a time. This method is fine for single and four byte register reads. However, for larger buffers the performace can be improved by aligning the the fifo write pointer to be at a word boundary. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Utilized test code on the host to initiate TPM fifo reads of various lengths and added timing markers on the Cr50 to compare performance between the existing byte at a time and the new full buffer write funciton. Verifed that the fifo reads will still correct and compared the time consumed copy TPM fifo data to the I2CS HW fifo. This test processed 1910 bytes over 34 fifo reads. Byte at a time method: 1910 bytes: 6375 uS: Avg Time = 3.233 uS per byte Full buffer write: 1910 bytes: 3009 uS: Avg Time = 1.57 uS per byte Change-Id: I3a47a350ab7af740a452fd115c33117b453b9611 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/377663 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: I2CS TPM: Changes to support fifo and version registers readScott2016-09-054-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for reading of TPM fifo registers. Since I2C does not provide means to communicate how many bytes the host wants to read there must be some handshake involved between the host and Cr50. The method added by this CL to allow Host reads of the TPM fifo assumes the following steps: 1. Host reads burstcount from Cr50 (which will be set to default 63) 2. Host reads 1st 10 bytes of the TPM response. 3. Cr50 will copy MIN(burstcount, msg_len) bytes into its I2CS HW fifo 4. Host computes msg_len and calculates amount of data still buffered 5. Host does a TPM fifo read of buffered data only (The following steps are repeated until the response read is complete) 6. Host reads burstcount from STS register. 7. Host issues read of burscount bytes from TPM fifo 8. I2CS will copy burstcount amount of bytes in to I2CS HW fifo 9. TPM layer sets burstcount to MIN(63, remaining msg bytes) The version register is treated similar to a fifo access. The data written or the number of bytes is a don't care, but there must be at least one byte of data written with the version register write. In the case of reads, the host must read burstcount bytes of the version register. If burstcount is longer than the Cr50 version string there is no issue because the version register read function always returns the number of bytes requested, stuffing in 0s once the end of the version string is reached. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Created test code in coreboot that exercises TPM register reads and writes. In addition, created a means to spoof a TPM cmd send and response read by Host. For these tests the header length is defined as 10 bytes and used 3 different payload lengths. The results for a payload length of 256 and 39 (message < 63) are shown below. Note the 0xaa and 0x55 have been inserted by the TPM spoof code on the host to mark the end of the header. ================================================= Cr50 TPM Register Read tests TPM Access = 0x0 TPM2 STS = 0x4003f80 TPM2 DID_VID = 0x281ae0 DID = 0x28, VID = 0x1ae0 Ver segment read 1, ret = 0 Version: B2:0 RO_A:0.0.1/84e2dde7 RW_A:0.0.1/cr50_v1.1.5151-acaef21+ ================================================= TPM Cmd: 266 bytes, Hdr = 10, Payload = 256 (last = ff) TPM STS: Sending command_ready fifo wr: burstcount = 63 fifo wr: Sent TPM Cmd: len = 266 bytes TPM STS: Sending TPM GO TPM STS: data_avail set TPM STS: 04 00 3f d0: burst = 63 fifo rd: Msg_len = 266 fifo rd: Hdr Len = 10, fifo_adjust = 53 fifo rd: Drained Cr50 HW fifo of 53 bytes fifo rd: burst = 63 fifo rd: burst = 63 fifo rd: burst = 63 fifo rd: burst = 14 fifo rd: complete 266 byte msg read [0000]: 00 00 00 00 01 0a 00 00 aa 55 00 01 02 03 04 05 [0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 [0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 [0030]: 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 [0040]: 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 [0050]: 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 [0060]: 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 [0070]: 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 [0080]: 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85 [0090]: 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 [00a0]: 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 [00b0]: a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 [00c0]: b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 [00d0]: c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 [00e0]: d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 [00f0]: e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5 [0100]: f6 f7 f8 f9 fa fb fc fd fe ff 00 00 00 00 00 00 ================================================= TPM Cmd: 49 bytes, Hdr = 10, Payload = 39 (last = 26) TPM STS: Sending command_ready fifo wr: burstcount = 63 fifo wr: Sent TPM Cmd: len = 49 bytes TPM STS: Sending TPM GO TPM STS: data_avail set TPM STS: 04 00 3f d0: burst = 63 fifo rd: Msg_len = 49 fifo rd: Hdr Len = 10, fifo_adjust = 39 fifo rd: Drained Cr50 HW fifo of 39 bytes fifo rd: complete 49 byte msg read [0000]: 02 00 00 00 00 31 00 00 aa 55 00 01 02 03 04 05 [0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 [0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 [0030]: 26 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Change-Id: I0e05156d6012c6dc86844e4c0ea80cc04f45734a Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374528 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: I2CS TPM: Unify tpm_registers interface between SPI and I2CScott2016-09-053-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed 3 TPM register definitions which were not used in tpm_registers.c and added missing entries to the I2CS translation table for TPM register address lookup. Moved the SPI specific locality 0 offset from tpm_registers.c to sps_tpm.c so the register defines in tmp_registers.c can be common to both the SPS and I2CS interface. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual For I2CS verification on Reef AP console used the command 'i2cget -y 8 0x50 <addr> b' to read both the TPM access and RID register. For SPI verifcation updated Cr50 FW on Kevin and verified that the AP successfully boots. Additionally, issued the command from the Kevin console 'trunks_client --own' and got the following console output without any errors being listed. [INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK. [INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK. Change-Id: Ib0b70e22cd46de2c59bd2e73f3c9aebd661e66c4 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368621 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Preliminary I2CS TPM2.0 driverScott2016-09-0512-35/+295
| | | | | | | | | | | | | | | | | | This CL includes changes in Cr50 required to support TPM via the I2CS interface. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Limited testing so far. Verified that the I2CS interface is initialized properly and that register reads occur when initiated on the AP console via command i2cget -y 8 0x50 0x1 w Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e Reviewed-on: https://chromium-review.googlesource.com/356241 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* it83xx: flash: remove time-out of checking flash statusDino Li2016-09-051-13/+17
| | | | | | | | | | | | | | | | | | | | | | Remove timeout to avoid fetching unknown instruction from e-flash and causing exception. Also fixed: - To make sure immu(dynamic cache) is reset after a erasing/writing operation. - Verify function is in critical section. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console commands: "flasherase" and "flashwrite". Change-Id: I0c84282ac4689cd762159071afae3efeea31d281 Reviewed-on: https://chromium-review.googlesource.com/380500 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* bd99955: usb_charger: Don't do BC1.2 detection on source portsShawn Nematbakhsh2016-09-051-3/+4
| | | | | | | | | | | | | | | | | | | | | If we're sourcing 5V to the port, consider the port as not providing power, for the purpose of VBUS / BC1.2 detection. BUG=chrome-os-partner:55432 BRANCH=None TEST=Manual on kevin, attach legacy peripheral in one port, zinger in the other, run "reboot" on EC console, and verify zinger port is selected as charge port. Also attach Apple charge-thru accessory w/o charger plugged, verify that charge manager is not informed of a BC1.2 / VBUS supplier. Change-Id: Ifbe587215f28756760e7106e1a00dd96319438e3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380324 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* TCPM: it83xx: fix build errorDino Li2016-09-051-3/+5
| | | | | | | | | | | | | | Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=The "IT83XX_PD_EVB" is non-zero and "make BOARD=it83xx_evb -j" Change-Id: Ie555370754f325fdf61d65c01533f4ca3897b25f Reviewed-on: https://chromium-review.googlesource.com/381135 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sweetberry: add usb fw updateNick Sanders2016-09-0211-32/+678
| | | | | | | | | | | | | | | Port USB firmware update to stm32f4 dwc usb from st usb. This includes usb dwc usb stream inplementation, generic endpoint interfaces, and the sweetberry test case. BUG=chromium:608039 TEST=usb update works BRANCH=None Change-Id: Ia26e4f7e990ee64991468799c99b036f5f32190f Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/377520 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* config: Make memory command optionalGwendal Grignou2016-09-022-1/+2
| | | | | | | | | | | | | | To save space of working image, make the console memory commands optional. BRANCH=veyron BUG=b:27849483 TEST=Compile, save 320 bytes. Change-Id: Ia538b30b4c06955c44b29eb22ed1a09fad83bd9e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/379115 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: fix observation register latch issue for event timerDino Li2016-09-023-31/+54
| | | | | | | | | | | | | | | | | Adding fix of event timer for CL:358730. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:55044 TEST=We simulate the delay time between first and second read, and prove this method can avoid latch fail. Change-Id: I82cd4ce470ffc9a8262d9303e3fd390812c89cac Reviewed-on: https://chromium-review.googlesource.com/380349 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: reset board properties after a hard resetMary Ruthven2016-09-021-0/+6
| | | | | | | | | | | | | | | | | The long life scratch register storing the board properties is not cleared after a hard reset. This change clears the properties before updating them, so we can reset the properties entirely instead of just adding to them. BUG=none BRANCH=none TEST=Update Cr50 with an image. Remove one of the board properties it uses and verify that property has been removed once you update it. Change-Id: I078dc1443d9f2e7f8761159906e1a277d79cb3cb Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380433 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: NvMem: Increase partition size from 0x2800 to 0x4000Scott2016-09-022-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_FLASH_NVMEM_SIZE was set to CFG_TOP_SIZE and then the partition size was computed by dividing this value by 2. Changed this so that now the partition size is set to CFG_TOP_SIZE and the total size is the partition size * 2. Also reduced the CFG_TOP_SIZE to 0x4000 as that should be plenty for TPM requirements and leaves room for future gnubby use. BRANCH=none CQ-DEPEND=CL:379076 BUG=chrome-os-partner:56798 TEST=manual Tested on Kevin, erased the existing NvMem area and verified that TPM was still manufactured and executed the command: trunks_client --own Erased parition 0 and 1 in the new locations and repeated the tests. Change-Id: Ie8910bec641d8d1ff390be5b03b430bf39d18404 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/379095 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: NvMem: Allow for partitions to not be contiguousScott2016-09-027-49/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TPM2.0 needs more NvMem space and currently the whole block is contiguous in memory with 2 partitions. This CL removes the requirement that the partitions are in contiguous which allows for 1 partition to placed at top of RW_A and the other at RW_B. This CL does not change the size of each partition as that will be done in a subsequent CL. BRANCH=none BUG=chrome-os-partner:56798 TEST=manual Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and verified that all tests pass. Tested on Kevin, erased the existing NvMem area and verified that TPM was still manufactured and executed the command: trunks_client --own Erased parition 0 and 1 in the new locations and repeated the tests. Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378675 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: mark updated image as good once a usb request is receivedMary Ruthven2016-09-023-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is now a call to reset the retry counter before the hard reset after an update. Cr50 will use the updated image for the next 5 boots, but on the 6th it sees the retry counter is greater than 5 and then jumps back to the old image. Cr50 needs to call system_process_retry_counter to reset the counter and corrupt the old image header to prevent falling back to the old image. Normally the reset counter would be processed after it receives a TPM command. Reef does not have Cr50 TPM support. Until Cr50 has TPM support for Reef, Cr50 should have a different point to know when the update is good. This change adds a board property to mark the process the reset counter once the Cr50 USB controller receives a set address request from the host. On Reef the controller defaults to the AP PHY when suzyq is not connected, so it should have a connection to the AP or through suzyq after boot. The board property is only added to Reef. Behavior on Kevin and Gru is unchanged. BUG=chrome-os-partner:56864 BRANCH=none TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw 0x4000012c' and verify it is reset to 0. Change-Id: If517202f25a694cd70550e3be047ea502e7c5383 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380354
* reef: Minor corrections to GPIO listDavid Hendricks2016-09-021-3/+5
| | | | | | | | | | | | | | | | | This patch makes a few small changes to gpio.inc: - Correct NC1 assignment (GPIO00) - Add ENG_STRAP (GPIOB6) which is currently not connected to anything. - Cosmetic fix for LEDs (replace spaces with tabs for alignment) BUG=none BRANCH=none TEST=built and booted on Reef Change-Id: Ieca83be6c7423694d88f21ebfc3f57849bf42cde Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380449 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* hadoken: Remove duplicate GPIO assignmentsMyles Watson2016-09-021-5/+0
| | | | | | | | | | | | | | Hadoken has an unpopulated SPI header. Remove older pin assignments. BRANCH=none BUG=none TEST=make buildall -j Change-Id: Icd889a8a312d6086a1a05c97403ff20a5a99c0b0 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380424 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: Enable pdcontrol commandDavid Hendricks2016-09-021-0/+1
| | | | | | | | | | | BUG=chrome-os-partner:56640 BRANCH=none TEST=tested w/ follow-up CL Change-Id: I1dad0bc8e23e265ba043e0d00c3d26ee5654c5e3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380296 Reviewed-by: Shawn N <shawnn@chromium.org>
* button: Add console command to simulate button pressVijay Hiremath2016-09-022-1/+86
| | | | | | | | | | | | | | | BUG=chrome-os-partner:56878 BRANCH=none TEST=Using console command 'button' verified that volume button icon slides on reef. Change-Id: I8051194fd91f989f8887cebce6ea2af1b8c9f731 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/380315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: Debounce extpower signal for 1secDavid Hendricks2016-09-021-0/+2
| | | | | | | | | | | | | | | | | This fixes an issue where the power+charge LED sometimes changes more than once when power is plugged in. BUG=chrome-os-partner:56471 BRANCH=none TEST=Reef power+charger LED changes from one color to another instead of back and forth (unless there are a lot of PD hard resets, but that's another matter) Change-Id: I0ea0dd59cbb7c86b758123fd4e6c8e7b20efa5df Reviewed-on: https://chromium-review.googlesource.com/378756 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pwm: Increse PWM duty resolution to 16bitsSam Hurst2016-09-024-74/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PWM interface allows for a pwm duty setting ranging from 0 to 100, resulting in a very coarse adjustment. To alleviate the problem, the interface now allows for a pwm duty setting in the range of 0 to 65535. BUG=chromium:615109 BRANCH=None TEST=Manual on chell. `ectool pwmsetduty 1 65535` - Verify LCD backlight goes to 100% `ectool pwmgetduty 1` - Prints 65535 `ectool pwmsetduty 1 0` - Verify LCD backlight goes to 0% `ectool pwmgetduty 1` - Prints 0 terminal pwmduty tests: >pwmduty PWM channels: 0: 100% 1: 62% 2: 100% 3: 80% > pwmduty 1 50 Setting channel 1 to 50% 1: 50% > pwmduty 1 0 Setting channel 1 to 0% 1: disabled > pwmduty 1 100 Setting channel 1 to 100% 1: 100% > pwmduty 1 raw 0 Setting channel 1 to raw 0% 1: disabled > pwmduty 1 raw 65535 Setting channel 1 to raw 65535% 1: 65535 > pwmduty PWM channels: 0: 100% 1: 100% 2: 100% 3: 80% > pwmduty 1 raw 30000 Setting channel 1 to raw 30000% 1: 30000 > pwmduty PWM channels: 0: 100% 1: 46% 2: 100% 3: 80% Change-Id: I299b77585f3988e72d9ac918bdde7dc5fa3df6de Reviewed-on: https://chromium-review.googlesource.com/374481 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* chell: Remove redundant GPIO definitionShawn Nematbakhsh2016-09-021-2/+0
| | | | | | | | | | | | | | | I2C2_SENSOR_3V3_SCL/SDA and I2C2_SCL/SDA are in fact the same pin. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I880e77118d1afcecb921f71adb1fbb6330249259 Reviewed-on: https://chromium-review.googlesource.com/380482 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* sweetberry: remove superfluous gpiosNick Sanders2016-09-021-6/+9
| | | | | | | | | | | | | | | | | Sweetberry specifies UART pins as GPIOs, however this is not necessary for uart use. Let's remove these. UART4 is also dup'd with sweetberry's signal gpios, which is fixed with this CL. BUG=chromium:608039 TEST=boots BRANCH=None Change-Id: I81ee2351c0191ff5ec3d5fad37fe10866bf1ad32 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380439 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add tests for dcrypto bn_modinv_vartimenagendra modadugu2016-09-026-7/+189
| | | | | | | | | | | | | | | | | | | This change introduces a larger range of tests for bn_modinv_vartime. The tests are designed to run on a host, and compare results against openssl. BRANCH=none BUG=chrome-os-partner:47524 TEST=bn_test passes Change-Id: I2d6ea4824fa82f78f8797c0cfc2cf0dce03e8923 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/365232 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: bn_modinv: correctly handle even inputsnagendra modadugu2016-09-021-0/+3
| | | | | | | | | | | | | | | | | | | | If both e, and MOD are even, then no modular inverse exists. This change adds handling for this set of inputs. Adding this change for completeness (there are no dcrypto library call paths that generate both e and N as even). BRANCH=none BUG=chrome-os-partner:47524 TEST=bn_test passes Change-Id: Ide64f980501175e9b6078efff92086d12bc1ae2d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/376180 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ryu: remove old workaround on GPIO C15Vincent Palatin2016-09-021-3/+0
| | | | | | | | | | | | | | | | | | | | Before P3 (long time ago), the PI3USB9281 has an I2C requiring a workaround using the GPIO C15. The workaround has been removed when we switched to PI3USB9281A on P3 and the GPIO has been re-used since. Remove the old GPIO definition to avoid conflicts with its new usage. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:31526 TEST=make BOARD=ryu Change-Id: Ieb7071b7ca27f3e9a4719592441b6a0b4c455b27 Reviewed-on: https://chromium-review.googlesource.com/380555 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: clear reset_counter after updateMary Ruthven2016-09-024-3/+37
| | | | | | | | | | | | | | | | If the firmware was just updated clear the reset counter before rebooting. This will ensure that the update can complete even if the TPM isn't being used. BUG=chrome-os-partner:56864 BRANCH=none TEST=Set the reset counter to 7 by running 'rw 0x40000128 1' and 'rw 0x4000012c 7'. Then make sure cr50 can still be updated Change-Id: Ic304fc7a20a4f2af7792f80e970d28e0eb10967e Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380235 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* extpower: Allow board to override signal debounce timeDavid Hendricks2016-09-022-3/+5
| | | | | | | | | | | | | | | | This is for boards on which AC_PRESENT can be expected to fluctuate over a much longer period than the code was originally designed for. Specifically, USB-PD systems may require several hundred milliseconds for the state machine to settle before making decisions based on AC_PRESENT status, for example, changing LED state. BUG=chrome-os-partner:56471 BRANCH=none TEST=Tested on Reef with follow-up patch Change-Id: I370048cb79d1593a14077563ec8db8e8282afb16 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378755
* kevin / gru: Remove internal PU on LID_ACCEL_INT_LShawn Nematbakhsh2016-09-021-2/+2
| | | | | | | | | | | | | | | | | | LID_ACCEL_INT_L is a push / pull interrupt pin which is currently unused by EC FW. Remove the PU to prevent leakage when PP1800_sensor is powered down. BUG=chrome-os-partner:56646 BRANCH=None TEST=On kevin, verify LID_ACCEL_INT_L is consistently logic 0 in S5. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6c748a18bcd183f799b78b4ad9098fff7a7d6567 Reviewed-on: https://chromium-review.googlesource.com/380236 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reef: Trigger interrupt on both the edges for volume button GPIOsVijay Hiremath2016-09-021-2/+2
| | | | | | | | | | | | | | | | | | Both press and release of the volume button has to be detected in order to process volume changes. Hence, trigger the interrupt on both the edges for volume button GPIOs. BUG=chrome-os-partner:56856 BRANCH=none TEST=Volume slider can slide when volume buttons are pressed. Change-Id: I0655f1c494d754904987cc2c76dcb3a39d5670ab Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/379621 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Keep SPIP module disabled in S3 / S5Shawn Nematbakhsh2016-09-021-3/+18
| | | | | | | | | | | | | | | | | | | | SPIP is only used in S0, so keep the module disabled in lower power states. Disabling SPIP through spi_enable() will also restore our CS pin to ODR_HIGH. BUG=chrome-os-partner:56860 BRANCH=None TEST=Verify SPIP is functional on initial power-up, sysjump, and on apshutdown / re-power-on. Also verify GPIO_SPI_SENSOR_CS_L goes low in S5. Change-Id: I14d845895a43700d2133a532cff63d08f0e64018 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380215 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin: Don't charge from source portsShawn Nematbakhsh2016-09-021-2/+21
| | | | | | | | | | | | | | | | | | BC1.2 detection may still occur on multi-purpose ports which we are currently sourcing. Don't charge from such ports, and don't incorrectly indicate that external power is present. BUG=chrome-os-partner:55907 BRANCH=None TEST=Manual on kevin, plug Apple charge-thru accessory with no charger attached, verify we don't charge from it. Change-Id: I9a74f1123fc51c7fc622f985bd528e96b9526946 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378595 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reef: Shutdown the AP before hibernatingVijay Hiremath2016-09-021-24/+12
| | | | | | | | | | | | | | | | | To support hibernate called from console commands, ectool commands and key sequence added code to shutdown the AP before hibernating. BUG=chrome-os-partner:56490 BRANCH=none TEST=Using console command, ectool command & key sequence verified both EC and AP are hibernated. Change-Id: I7708377596d7d4175a44c202ae2385a239ca3d01 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/379157 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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