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* kracko: Update battery configTommy Chung2021-04-202-230/+6
| | | | | | | | | | | | | | | Updates the battery config on kracko. BUG=b:183664617, b:178092096 BRANCH=dedede TEST=Make sure battery charging, battery cutoff works. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: Icc00f8bc23f73e9f7287a0f6980667c166bcba57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784330 Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* TCPC/PPC: Add code for Cypress EZ-PD CCG6DF, CCG6SFVijay Hiremath2021-04-204-0/+30
| | | | | | | | | | | | | | | | | | | | | | CCG6DF and CCG6SF are dual-port and single-port USB Type-C controllers respectively. These can act as either PD or TCPC based on the Phy firmware flashed on the internal flash. These chips use standard TCPCI driver. BUG=none BRANCH=none TEST=With the initial Phy F/W able to test following on ADL RVP 1. Single port Type-C is validated 2. Dead battery boot 3. Source & Sink path 4. SOP* 5. USB, DP, TBT 6. 100K, 400K, 1MHz I2C Change-Id: I1b1a2f759139ac1c7aab42d851b8a7866664e28a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2551653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Cleanup: Enable PPC from PD or Power MUXVijay Hiremath2021-04-2012-11/+33
| | | | | | | | | | | | | | | Some PD chips have integrated SRC FET and control the SRC/SINK FET from GPIOs hence cleaned up the code to enable Power Path Control from either from PD or from Power MUX. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I77f96b681fd2e5fca35bce425e4bd5ec87d5ccfd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2828980 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: hooks: store deferred data in .rodata on non-posixFabio Baltieri2021-04-191-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the deferred data section from .data.hooks to .rodata.hooks, matching the ECOS behavior. This was apparently done for compatibility with native_posix, so only make this change when we are not on ARCH_POSIX. The change means that the hooks data is not copied in RAM anymore, which saves a significant amount of device memory. For volteer, before: text data bss dec hex filename 223934 9716 40092 273742 42d4e build-ro/zephyr/zephyr.elf After: text data bss dec hex filename 225730 7924 40092 273746 42d52 build-ro/zephyr/zephyr.elf Compared to ECOS: text data bss dec hex filename 203680 6384 33676 243740 3b81c volteer/RO/ec.RO.elf BUG=b:183748844 BRANCH=none TEST=build and run on volteer Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: Ia23e9c0dc5ee9eaeee674f943b22762355ad5efe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2836100 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* copano: Enable AP-driven alt mode entryMichael5 Chen12021-04-191-0/+2
| | | | | | | | | | | | | | | Wait for the AP to direct the EC to enter USB PD alternate modes. BUG=b:183773805 TEST=make buildall BRANCH=firmware-volteer-13672.B Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: Ifc436f4043430f70ddba8563210b0a09cd5daf18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2835256 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* asurada/spherion: Remove CONFIG_SYSTEM_UNLOCKEDYu-Ping Wu2021-04-192-2/+0
| | | | | | | | | | | | | | | | Remove CONFIG_SYSTEM_UNLOCKED for asurada, hayato and spherion to avoid unnecessary sysjump when flashing EC with write protect enabled. BUG=b:160229421, b:185433646 TEST=emerge-asurada chromeos-ec TEST=firmware_WriteProtectFunc passed on Hayato BRANCH=asurada Change-Id: I76c9f381a1dd3b4f0e4e3e990ceb7a8c3c0e4128 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2834754 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
* Homestar:BMI160:Adjust the initial orientation of the BMI160tongjian2021-04-191-2/+2
| | | | | | | | | | | | | | BUG=b:185631804 TEST=make -j BOARD=homestar Verify build on EVT board BRANCH=Trogdor Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: I91de1f34af210103b12b30f8cfa6a17e7692a301 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2833032 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
* voema: support kx022/bma255 with ssfc bits mapBen Chen2021-04-194-10/+81
| | | | | | | | | | | | | | | | config kx022 or bma255 motion sensor by ssfc bits map, and rename volteer ssfc bits map. BUG=b:178447173 BRANCH=main TEST=Using ectool 'motionsense' verified lid angle now goes from 0 to 360 and swtiches to tablet mode after crossing 200 threshold on re-work kx022/bma255 DUT. Change-Id: I2901b0cc980e50324eb4f20d073c5f3a4c3f80e3 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825719 Reviewed-by: Keith Short <keithshort@chromium.org>
* honeybuns: Add C2 initialization with power button on/offScott Collyer2021-04-177-85/+79
| | | | | | | | | | | | | | | | | | | | | | | This CL refactors code required for the user facing usbc port. This port was only being initialized at init time and therefore would not function properly following a power button off/on. To avoid duplicating code, the functions used to initialize this port and control VBUS were moved to usbc_support in baseboard so they can be common and are now guarded by a GPIO macro so this can be board specific for variants which don't have a PPC to control on this port. BUG=b:164157329 BRANCH=quiche TEST=Verifed that port C2 attaches as expected following power button off/on sequence. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2f9500f7e58de674c6f7c12a95cebad45de166cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785198 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* zephyr: validate interrupt flags at build timeKeith Short2021-04-171-0/+23
| | | | | | | | | | | | | | | | | | The name spaces for GPIO interrupt flags are similar between Chromium EC and Zephyr. Add a build time check that the flags are valid for Zephyr. BUG=b:182398910 BRANCH=none TEST=zmake testall TEST=Set a GPIO interrupt flag to an invalid value and verify build error. Cq-Depend: chromium:2825909 Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I27caff1fed3827c09450c743cb62ce8a7cbdaac4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826415 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* flash_ec: introduce early Ti50 supportVadim Bendebury2021-04-171-17/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the purposes of UUT based EC programming Ti50 is very close to Cr50, the only difference is that Ti50 does not allow enabling UUT mode before EC reset is asserted. This patch makes sure that processing path for Ti50 and Cr50 is the same, and adds asserting of the EC reset before UUT programming mode is enabled. Also done some clean up, declaring variables 'local' in functions this patch touches. BRANCH=none BUG=b:161483597, b:184770575, b:185265453 TEST=the procedure is as follows, inside chrome OS chroot: $ sudo servod --board brya -c ccd_ti50.xml In a different terminal in the EC tree: $ make BOARD=brya $ ./util/flash_ec --board=brya Verify that the EC is up and running the latest image. Also verified Cr50 CCD operation by programming a bobba EC image: $ sudo servod --board bobba In a different terminal in the EC tree: $ # place a booba image into build/bobba/ec.bin $ ./util/flash_ec --board=bobba Verify that the bobba device was programmed using UUT and is running the updated EC image. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ib266078c66586591d0115fe76214ae8c8921a547 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826701 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* brya: Tune mp2964 settingsCaveh Jalali2021-04-163-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tunes some parameters in the MP2964 IMVP9 to improve system stability. In this round, the only tuning we have identified is to change the SVID alert delay time to 200ns. The tuning is applied to the PMIC registers, then committed to the PMIC non volatile memory. On subsequent boots (including power cycle), the tuned values are used and no further tuning is required. 1st boot: mp2964_on_startup: attempting to tune PMIC mp2964: tuning reg 0x3f from 0xe001 to 0xe081 mp2964: tuning reg 0x3f from 0xe001 to 0xe081 mp2964_store_user_all: updating persistent settings mp2964: reg 0x3f already 0xe081 mp2964: reg 0x3f already 0xe081 2nd+ boot, also after removing battery: mp2964_on_startup: attempting to tune PMIC mp2964: reg 0x3f already 0xe081 mp2964: reg 0x3f already 0xe081 BRANCH=none BUG=b:185424011 TEST=unplugged battery, verified new values are persistent Change-Id: Idcb540eed6f893586853b8fed6e84e24b4a2f9e3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823634 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
* gitlab: Add kohaku and delbinSimon Glass2021-04-161-0/+11
| | | | | | | | | | | | | | Add these two boards so we get coverage on gitlab. BUG=b:178731498 BRANCH=none TEST=try on gitlab Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ia0d46554c93ffb9eeb5697a4c84d4e93864b928d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2817961 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* gitlab: Use a template to make it easier to add more boardsSimon Glass2021-04-161-14/+19
| | | | | | | | | | | | | | It is a pain to repeat the build steps, so use a template instead. BUG=b:178731498 BRANCH=none TEST=try on gitlab Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I2515627af230182e0e663f5d2ab6d7b3a77d3d2c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2817960 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* driver: bmi: fix use of I2C_PORT_ACCELYuval Peress2021-04-168-145/+169
| | | | | | | | | | | | | | | | | | | | | The BMI driver is currently using I2C_PORT_ACCEL incorrectly as a CONFIG_ value. Update the use cases to a new config option that selects between SPI and I2C communication specifically for the chip. To avoid a lot of device.h changes, the value of the config value is automatically inferred if not explicitly set. BRANCH=none BUG=b:185392974, b:146065507 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I6196cc595dc61877ab2b8ed5416bebee51276927 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829010 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* driver: icm: fix use of I2C_PORT_ACCELYuval Peress2021-04-168-133/+175
| | | | | | | | | | | | | | | | | | | | | The ICM driver is currently using I2C_PORT_ACCEL incorrectly as a CONFIG_ value. Update the use cases to a new config option that selects between SPI and I2C communication specifically for the chip. To avoid a lot of device.h changes, the value of the config value is automatically inferred if not explicitly set. BRANCH=none BUG=b:185392974, b:146065507 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I8b1a507a76031c2bb1aaf4ca7b14b92252a941f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826920 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* guybrush: Refactor FP6 mux driver to retry in S0Rob Barnes2021-04-161-74/+80
| | | | | | | | | | | | | | FP6 USB mux is not ready until sometime after S0. Refactor driver to keep trying every 1 second until mux is ready. BUG=b:184680878, b:184966860 TEST=C0 and C1 display connects on B1 and B2 BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: If744182879461d8452426deaf0e74a84dacfd510 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2819023 Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr: override the sysworkq stack size for npcxFabio Baltieri2021-04-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | This lowers the stack size for the sysworkq task to bring it close to the 75% target watermark. This is the Zephyr workqueue thread, it is used by the k_work_submit() API and started showing up after 783543b32: uart:~$ kernel stacks ... 0x200c7ed0 sysworkq (real size 288): unused 80 usage 208 / 288 (72 %) BUG=b:183748844 BRANCH=none TEST=kernel stacks Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: I9aa733dc63e08abf689f9e0c265cbe5afe533cc1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2830818 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zmake: Fix test deadlineYuval Peress2021-04-161-0/+4
| | | | | | | | | | | | | | | In CQ sometimes IO operations take a while, set a deadline of 1 minute for the util tests which read/write to files. BRANCH=none BUG=b:185257506 TEST=pytest zephyr/zmake/tests Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ie1dd9aed3d3556f748aaa087f47a10724169529d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829979 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: lazor: Fix GPIO interrupt tableDawid Niedzwiecki2021-04-161-10/+15
| | | | | | | | | | | | | | | | | | We use GPIO edge falling interrupts for some events. These one were initialized incorrectly with EC GPIO flags instead of Zephyr GPIO flags, thus the interrupts were not triggered. Change GPIO_INT_* to GPIO_INT_EDGE_* for all of them. BUG=b:182398910 BRANCH=none TEST=Build Zephyr EC for Lazor, flash Limozeen board and boot to OS, Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Id10aa010071d44f2d714eb9673ec7cad300bdf60 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825909 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* drive: lsm6dso: Modify interrupt from high active to low activeOwen_Ou2021-04-161-2/+3
| | | | | | | | | | | | | | | | | | | HW design the motion sensor interrupt pin to active low, but in the EC codebase, the sensor initial value for LSM6DSO_CTRL3_ADDR (0x12) didn't set the bit 5 (LSM6DSO_H_L_ACTIVE) to high. BUG=b:185282500 BRANCH=none TEST=ectool motionsense can read the base accel and gyro value. Signed-off-by: Owen_Ou <owen_ou@compal.corp-partner.google.com> Change-Id: Iaecdab388a218ae7ae8c586b70f576612c7f85de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825989 Reviewed-by: Owen Ou <owen_ou@compal.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Tested-by: Owen Ou <owen_ou@compal.corp-partner.google.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: test_util: Add TEST_SUITE macroTomasz Michalec2021-04-162-1/+7
| | | | | | | | | | | | | | | TEST_SUITE macro allows to define Zephyr test as test suite instead of test_main(). Test suite can be used as part of bigger test. BUG=b:185205123 BRANCH=none TEST=zmake testall TEST=make runhosttests Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I834ccf38e256c918623e96bb39597a0b22a874c0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825910 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* raa489000 : control ALERT_B when wake from hibernationYongBeum.Ha2021-04-161-0/+11
| | | | | | | | | | | | | | | | When 'Enable ADC' on Control3 is cleared, EN_DIS_MCU_LDO_IN_BAT on Control8 and EN_DIS_GP_COMP_IN_BAT on Control4 must be cleared to set ALERT_B. BUG=b:185434129 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I6f77c0cfb727a66128ef95115a02d2fd49a04ad9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2830654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: lazor: add the write-protection switch interruptWai-Hong Tam2021-04-161-0/+1
| | | | | | | | | | | | | | | | | | Add the write-protection switch interrupt. The switch state can be updated in time. BRANCH=None BUG=b:182398910 TEST=Changed the write-protection switch in Cr50 console. Checked the interrupts were triggered and showed the messages: [225.050900 SW 0x05] # The WP bitmask is 0x4. [230.853700 SW 0x01] Change-Id: I8bd801ac872b9f7b91895e504069f91921c9592f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2831051 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* include/system: support interrupt_disable_all of RISCV in zephyrtim2021-04-161-0/+2
| | | | | | | | | | | | | | | We need to call the function of interrupt_disable_all in the case of not cortex_m CPU. BUG=b:185202623 BRANCH=none TEST=zmake -lDEBUG configure -b -B zephyr/build_ite zephyr/projects/it8xxx2_evb/ (no warning) Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I852d530ba1e319dbe4656e23d8f143566dd7a626 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2797684 Reviewed-by: Keith Short <keithshort@chromium.org>
* careena: Add thermal protectionDevin Lu2021-04-163-1/+23
| | | | | | | | | | | | | | This patch adds thermal protection to prevent AP runaway. BUG=b:185082703 BRANCH=firmware-grunt-11031.B TEST=Verify thermal halt/alert as expected. Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I4fccc93b0cb89a2e5d2784dfc0a41aa866f691f2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822269 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* Zephyr: dts: npcx: reshuffle the default IRQ priority of KBSJun Lin2021-04-162-2/+2
| | | | | | | | | | | | | | | | | Lower the interrupt priority of keyboard scan module to meet the original ECOS's setting. BRANCH=none BUG=b:184881816 TEST=Boot up on Volteer and test keyboard function. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ic6b587e505edd8a3eeaeb7996a4e21ab16fdf159 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822278 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* cleanup: delete unused legacy kconfig implementationJack Rosenthal2021-04-1639-19988/+0
| | | | | | | | | | | | | | | | | | | | | | | This code is currently unused. It was from an effort to bring Kconfig to CrOS EC OS. Our EC will receive Kconfig by means of Zephyr-based devices, making the effort to bring it to the legacy OS likely obsolete. However, if for some reason we want to bring it to the legacy OS in the future, we would probably want to use kconfiglib instead of this C implementation, as Depthcharge and Zephyr have migrated to it, and Coreboot is in the process of migrating to kconfiglib. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: If53d0c6bd752a0adba775b8638a4f612ccb399ef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2824033 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* mp2964: Add PMIC driverCaveh Jalali2021-04-168-2/+217
| | | | | | | | | | | | | | | | | This adds a driver for the mp2964 IMVP9.1 PMIC. This driver enables programming control registers within the PMIC. BRANCH=none BUG=b:185424011 TEST=buildall passes. functional testing was done with the follow-on patch. Change-Id: I9b2d89007b5f6933ceeb9a1bcd3bbefb819888a3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2827950 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* bq25710: Sort registers in numerical orderCaveh Jalali2021-04-162-14/+14
| | | | | | | | | | | | | | | | This sorts the register reporting in the charger_dump command to be numeric order. The original order was probably motivated by the bq25710 datasheet which lists registers out of order. The bq25720 datasheet lists registers in numeric order which makes cross referencing easier. BRANCH=none BUG=b:185190976 TEST=buildall passes Change-Id: I79eca2d1926bd87d77d710e812fc6d18e4b4d2e8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2819587 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: add lid_open interruptBoris Mittelberg2021-04-152-1/+2
| | | | | | | | | | | | | | | | | | | Any change on LID_OPEN line coming from GMR will trigger an interrupt. Notes: on P0 there is no magnet, so the interrupt will never be triggered on P1 the magnet is upside down, so lidstate would always report "open" BRANCH=none BUG=b:185322560 TEST=manual test with a magnet: when magnet approaches the GMR sensor with correct orientation - lid close event happens. Depending on the OS state the system shuts down or enters sleep. When the magnet is removed the system wakes up Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I427c15d4f75add34266701089e05f99a924a5b3a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2827411 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* system: Wait 1s for EC to quiesce before hibernateAseda Aboagye2021-04-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The EC can enter hibernate via a keyboard shortcut alt+vol_up+H when in S0. However, the EC will never actually hibernate from S0; instead, it waits until the system is in S5/Pseudo G3 for 1hr (default setting). If the system is in S0 when hibernate is requested, it performs an unclean shutdown and then enters hibernate immediately. However, this can allow spurious interrupts to wake up the EC again. This commit simply adds a 1s delay after the unordely shutdown and before entering hibernate. BUG=b:185302895,b:185206379 BRANCH=dedede TEST=Build and flash DUT, boot to S0, press alt+vol_up+H, verify DUT turns off and stays off. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I98e094a64ae716811e44fe1858ad981403da7b39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829116 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add MEC1723 board: sklrvp_mchp1723Scott Worley2021-04-157-0/+934
| | | | | | | | | | | | | | | | | | | | Add new board, sklrvp_mchp1723 using MEC1723-SZ and based upon the intelrvp baseboard. Users may switch to the MEC1727-SZ variant with internal 512KB SPI flash by changing the variant name to mec1727sz in the board's build make file. BRANCH=none BUG=none TEST=Build MEC172x chip and sklrvp_mchp1723 board. Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ia044a2149cf797aa620ad023be133c97b6183ac5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2749516 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add lfw/gpio.inc in chipmartin yan2021-04-158-261/+118
| | | | | | | | | | | | | | | | | Add gpio.inc in chip, and update build.mk; Delete lfw/gpio.inc under all mchp boards; BRANCH=none BUG=none TEST=Build sklrvp_mchp172x. Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd98d4d93cb31f70592d6668e598fbc88e727450 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2810884 Reviewed-by: Martin Yan <Martin.Yan@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Metaknight: Support motion sensor 2nd sourceYu-An Chen2021-04-152-1/+67
| | | | | | | | | | | | | | | | | | Support motion sensor 2nd source: -Base : ICM-426xx BUG=b:177868819 BRANCH=dedede TEST=rework ICM-426xx to DUT, check ectool motionsense lid_angle is correct. Signed-off-by: yu-an.chen@quanta.corp-partner.google.com Change-Id: I8aa344662654d2f02d8cdd5101fcfe568931085f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825720 Tested-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Auto-Submit: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Cret: Modify HDMI enable/disable conditionjohnwc_yeh2021-04-151-27/+16
| | | | | | | | | | | | | | | | | | Cret does not support DB, the HDMI implement at MB side. Need to remove HDMI enable/disable condition(by FW_Conifg) and enable function in board init directly. BUG=b:185434117 BRANCH=dedede TEST=make BOARD=cret Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: I2a2eedc89b163c7629c1650fdb56de9f206dfd42 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825715 Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* honeybuns: override function for pd_can_source_from_deviceScott Collyer2021-04-151-0/+12
| | | | | | | | | | | | | | | | | | | This CL adds honeybuns policy for power role swap. Always return false so we will request a power role swap if in a sink role and port partner is DRP capable. BUG=b:182441965 BRANCH=None TEST=verfied that on quiche when attaching as a sink that a power role swap request is generated. Previously, quiche relied on the host requesting a power role swap. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I9c81519b845b15611ed503fc5e582b15a75b72ad Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2768138 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* honeybuns: Allow for board specific mf preferenceScott Collyer2021-04-155-11/+59
| | | | | | | | | | | | | | | | | | This CL enables a given board to have its own policy regarding the mf preference bit which is used by a UFP to signal its preferred pin configuration in the DP Status message. BUG=b:175434634 BRANCH=None TEST=Verfied that the mf bit in the DP status message follows the board preference. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ied7cdb72d1e302aab25dd5531856b1c7c148e64f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2765422 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* zephyr: i2c: Fix use of I2C_PORT_VIRTUAL_BATTERYYuval Peress2021-04-151-1/+2
| | | | | | | | | | | | | | | | | | In Zephyr builds, the I2C_PORT_* values are enums generated from devicetree (instead of #define values). This means that in Zephyr, it should suffice to just check VIRTUAL_BATTERY_ADDR_FLAGS. BRANCH=none BUG=b:185392974 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ifedaf45ec8bcfa33bb75c8381604ad565ca08d6a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826919 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: npcx: Remove the comment for cros_system_npcx initWealian Liao2021-04-151-4/+0
| | | | | | | | | | | | | | | | | | The original limitation for cros_system_npcx_init() is from the WDRST_STS register will reset unexpectedly by the other driver. zephyr CL:2784074 add a mask for the bit and it shouldn't have this limitation anymore. Remove the comment for cros_system_npcx init priority. BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I6982de5e1384d157a82ceba96bc38bf2906b2072 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825721 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* test/cbi: allow to use test with WP GPIO active lowTomasz Michalec2021-04-151-0/+11
| | | | | | | | | | | | | | CBI test is usable without setting CONFIG_WP_ACTIVE_HIGH option. BUG=b:185205123 BRANCH=none TEST=make run-cbi Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I3f33167eac0a6545f8f323ff6935c079e706560b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2821698 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* test/cbi: refactor test to by usable in ZephyrTomasz Michalec2021-04-151-95/+137
| | | | | | | | | | | | | | This change refactors test/cbi.c to use macros common for EC and Zephyr tests. It is based on docs/ztest. BUG=b:185205123 BRANCH=none TEST=make run-cbi Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I1c8eb5263b8bd8f435bb3c64b9dacfd14deb01e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2821697 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* zed: update touchpad parameterTing Shen2021-04-153-19/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update touchpad parameter for zed. There's no integer solution for CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y (calculation appended below), this CL also modified the runtime check in elan tp driver to allow rounding errors. Math details: Given dpi_y = 800, LOGICAL_MAX_Y = 1811, we want to find an integer PHYSICAL_MAX_Y such that dpi == 254 * LOGICAL_MAX_Y / PHYSICAL_MAX_Y. The closest solution is 1) PHYSICAL_MAX_Y = 574, 254 * LOGICAL_MAX_Y / PHYSICAL_MAX_Y = 801.3832 != dpi_y, or 2) PHYSICAL_MAX_Y = 575, 254 * LOGICAL_MAX_Y / PHYSICAL_MAX_Y = 799.9895 != dpi_y Both cannot pass our runtime verification. BUG=None TEST=No "TP mismatch" in ec console BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I9d0c54d029bb2f9e78114341a6246857b41937b4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2825473 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* garg: Add simplo 916QA141H batteryDevin Lu2021-04-152-0/+30
| | | | | | | | | | | BUG=b:184920909 BRANCH=firmware-octopus-11297.B TEST=Test on charging/discharging/battery cut off pass. Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I80d15bdef79e8e228c68d866c32e87d445bcf28e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2817139 Reviewed-by: Diana Z <dzigterman@chromium.org>
* brya: add function to enabled/disabled keyboard backlightJosh Tsai2021-04-151-0/+17
| | | | | | | | | | | | | | | | | Enabled keyboard backlight when system resume to S0 Disabled keyboard backlight when system suspend BUG=b:184103439 BRANCH=none TEST=Keyboard backlight can work normally Signed-off-by: Josh Tsai <Josh_Tsai@compal.corp-partner.google.com> Change-Id: Idd4454bfba48d92bdfd75144141afac34c3781c6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822275 Reviewed-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Commit-Queue: Josh Tsai <josh_tsai@compal.corp-partner.google.com>
* raa489000 : clear 'Enable ADC' bit on port 1YongBeum.Ha2021-04-151-9/+10
| | | | | | | | | | | | | | 9mW is reduced on S0iX power consumption by clearing 'Enable ADC' bit. BUG=b:178356507 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I585ce87bf778f8386edfe8ccaaf1aa53f0374eff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2801175 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: use interrupt based RX bufferingYuval Peress2021-04-155-43/+141
| | | | | | | | | | | | | | | | | | | | Poll-based RX was technically incorrect since Zephyr was setting up the UART to FIFO mode (instead of byte mode). This change replaces polling the RX UART with interrupt based callbacks. When calling uart_shell_stop(), the ISR will be replaced and will instead queue items to a ring buffer which can be read from uart_getc() (it can also be cleared via the uart_clear_input() function). BRANCH=none BUG=b:181352041 TEST=Build volteer, run, see expected 0xec07 from the GSC. Cq-Depend: chromium:2730870, chromium:2730869 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I5d2b61e914b56f678a259b373969522da87e8df3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2728824 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* TCPMv2: Generate Hard Reset eventAbe Levkoy2021-04-153-0/+8
| | | | | | | | | | | | | | | Inform the AP when the PRL completes a Hard Reset. BUG=b:183946291 TEST=Observe event during transition-to-default states TEST=With kernel patch, observe mode reentry after Hard Reset BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I4af576bd3a8fb57d820bd91d74817040214eaa5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2799924 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* zephyr: Adjust watchdog warning timer value and delay timeMulin Chao2021-04-145-21/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjusts the watchdog warning timer value and its delay time definitions to meet original chromium ec behavior. The system handles the warning event at CONFIG_AUX_TIMER_PERIOD_MS & issues the watchdog reset event at CONFIG_WATCHDOG_PERIOD_MS. Zephyr NPCX watchdog provides a config WDT_NPCX_DELAY_CYCLES for watchdog timeout delay. Set the zephyr timeout to CONFIG_AUX_TIMER_PERIOD_MS as warning time. So the NPCX watchdog hardware issue reset event at CONFIG_AUX_TIMER_PERIOD_MS + WDT_NPCX_DELAY_CYCLES. BUG=b:184683548 BRANCH=none TEST=Build & boot ec on volteer. TEST= `waitms 1000` warning doesn't issue & ec doesn't reboot `waitms 1200` warning issue & ec doesn't reboot `waitms 1500` warning issue & ec doesn't reboot `waitms 1700` warning issue & ec reboot Cq-Depend: chromium:2813911 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Ibee9c18cd9d2bae6d34ee9366755dec99687c3d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2814728 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* TCPMv2: Soft reset on Vconn_Swap sequence interruptionDiana Z2021-04-141-0/+12
| | | | | | | | | | | | | | | When a non-interruptible AMS is interrupted, the unexpected message should yield a soft reset on the SOP* of the incoming message. Before sending PS_RDY, check for this condition and soft reset if necessary. BRANCH=None BUG=b:182221344 TEST=on sasuke, confirm charger can successfully connect reliably Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I6612cb5d5d74cf99155cac99894a7746462a7b9e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823633 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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