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* cr50_fuzz: Re-enable this fuzz target now that chromeos-ec is fixed.Allen Webb2019-01-021-1/+1
| | | | | | | | | | | | | | | | A new symbol was added to third_party/tpm2 that needed a mock implementation in cr50_fuzz to fix compilation. CQ-DEPEND=CL:1370404,CL:1377383 BRANCH=None BUG=chromium:911310 TEST=USE="ubsan asan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec Change-Id: I3e2546829646e89361bfa2a8b4084c95b346f78f Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1370747 Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* ISH: HID: enable HID subsystemstabilize-atlas-11512.BHyungwoo Yang2019-01-011-0/+3
| | | | | | | | | | | | | | | | enable HID subsystem. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279433 Change-Id: I50ce44c76abe823a68745ee8114cc8f0fabbe36c Reviewed-on: https://chromium-review.googlesource.com/1279314 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ISH: HECI: enable HECIHyungwoo Yang2019-01-012-0/+3
| | | | | | | | | | | | | | | | enable HECI. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279432 Change-Id: I3184f822e5ad026164b86efbd4b6dabf1102db86 Reviewed-on: https://chromium-review.googlesource.com/1279313 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ISH: IPC: enable IPC for HECIHyungwoo Yang2019-01-012-1/+4
| | | | | | | | | | | | | | | | enable IPC for HECI BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279363 Change-Id: I98568b537b4b812e97c22dff610e1147ed12701d Reviewed-on: https://chromium-review.googlesource.com/1279311 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* mt_scp/ipi: Support host command.Yilun Lin2018-12-294-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | mt_scp is the first chip which uses IPI to do host command communication. This CL implements the host command over IPI. TEST=Run ec.RW.bin on kukui by "echo start > /sys/class/remoteproc/remoteproc0/state" and see that there are HC logs from SCP uart [0.000385 hostcmd init 0x0000000000002000] [0.049958 HC 0x0b] [0.050061 HC 0x400b] [0.050108 HC 0x400b err 1] [0.050204 HC 0x08] [0.050240 HC 0x08 err 3] [0.050370 HC 0x8d] [0.050406 HC 0x8d err 1] [0.050821 HC 0x0d] BUG=b:117917141, b:120953723 BRANCH=None Change-Id: I2c2b701d92504a74cc2ee90ab05912e99378acde Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1379410 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Support inter-process interrupt/communication (IPI).Yilun Lin2018-12-2910-4/+400
| | | | | | | | | | | | | | | | | | This CL enables the IPI/IPC functions in mt_scp on MTK SOC. TEST=Run ec.RW.bin on kukui, and see EC version string in AP console: remoteproc remoteproc0: powering up scp remoteproc remoteproc0: Booting fw image scp.img, size 29800 mtk-scp 10500000.scp: scp is ready. kukui_scp_v2.0.519+164255084 BRANCH=None BUG=b:117917141, b:120172001, b:120953723 Change-Id: I2a43aee13141535bf71f839cf9e6cc0460b65844 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1351924 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* karma: update thermal tableSue Chen2018-12-281-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | on off RPM step0 0 step1 30 5 2180 step2 49 46 2680 step3 53 50 3300 step4 58 54 3760 step5 63 59 4220 step6 68 64 4660 step7 75 70 4900 Prochot degree: active when t >= 81C release when t <= 77C Shutdown degree: when t >= 82C BUG=b:121154903 BRANCH=master TEST=fan target speed follows table, make -j buildall pass Change-Id: I80a0b05cf1b693114fe664e5961973ed550fcc19 Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1379417 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ISH: HID: implement HID subsystemHyungwoo Yang2018-12-283-0/+531
| | | | | | | | | | | | | | | | | | Introduce HID subsystem. HID subsystem provides interface for a HID device to communicate with host. Using this API, a HID device can use hid-core in host. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279432 Change-Id: I0547a07e1c1cb5d34ba11b245ca539cf53b7d30d Reviewed-on: https://chromium-review.googlesource.com/1279433 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ISH: HECI: implement HECI layerHyungwoo Yang2018-12-286-0/+1418
| | | | | | | | | | | | | | | | | | | Introduce Host Embedeed Controller Interface for ISH. HECI is bi-directional fully asynchronous communication interface between host and ISH. It enables a host software to communicate with a ISH software(a HECI client). BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279363 Change-Id: I5fdc3018e9575c5fd0c804a883293f6c9f8aa2e7 Reviewed-on: https://chromium-review.googlesource.com/1279432 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Makefile: Drop warning about using ASAN by defaultNicolas Boichat2018-12-281-1/+0
| | | | | | | | | | | | | | | | The warning is distracting in build output. If TEST_FUZZ is set, it is sensible to use TEST_ASAN by default, let's not print any warning. BRANCH=none BUG=none TEST=make buildall -j >/dev/null => No more warnings. Change-Id: I8875b7f63154a4e051a5bb29f6640d4ee2923c19 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389990 Tested-by: Allen Webb <allenwebb@google.com> Reviewed-by: Allen Webb <allenwebb@google.com>
* Makefiles.rules: Clean up fuzz test targets rulesNicolas Boichat2018-12-281-5/+5
| | | | | | | | | | | | | | | | | We want to be able to build fuzzing tests individually, and running one test should not require to build them all. Move the environment change to each fuzz-test-target. BRANCH=none BUG=none TEST=make host-host_command_fuzz works Change-Id: Ic80c32d4b17fd30f30e8de0cfea7eee341c68978 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389989 Tested-by: Allen Webb <allenwebb@google.com> Reviewed-by: Allen Webb <allenwebb@google.com>
* ISH: IPC: implement generic IPC layerHyungwoo Yang2018-12-275-0/+1009
| | | | | | | | | | | | | | | | Introduce new IPC API supporting MNG and HECI protocols. Currently it supports communication with host(x64) BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. Change-Id: Iea6d1f96c89228b425861d045618d58f9d146f08 Reviewed-on: https://chromium-review.googlesource.com/1279363 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/minute-ia: fix atomicsHyungwoo Yang2018-12-231-16/+13
| | | | | | | | | | | | | | | | | | | | | | this fixes a few wrong implementation on atomic. atomic_read_clear() and atomic_clear() were functinally broken. Due to this, key control flow which rely on these functions were out of order. Also modified ATOMIC_OP() and bool_compare_and_swap_u32() to give more accurate directives to compiler. BUG=b:119628522 BRANCH=none TEST=tested on atlas Change-Id: Ide8397e4f7b754a7094c66326ecc2450ef2f0cc9 Reviewed-on: https://chromium-review.googlesource.com/1305118 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* atlas: disable PD communication when EC is lockedCaveh Jalali2018-12-231-0/+1
| | | | | | | | | | | | | | | | | | this config option disables PD communication when the EC is still running in RO and the system is "locked". for now, atlas is still configured to be unlocked, so changing this config will not affect PD negotiation. BUG=b:121222819 BRANCH=none TEST=verified we still charge at 15v in RO Change-Id: I389b6c7e3bef9c348f929b84240370d8a7930644 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1387999 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bobba: Change FIFO settingsEnrico Granata2018-12-231-1/+1
| | | | | | | | | | | | | | | | | | | Overly large sensor batches lead to timestamp synchronization issues on bobba, causing - among others - CTS to sometimes fail the sensor batching tests. This patch reduce the size of the FIFO, with the same rationale as CL:1354484 did for Nocturne. BUG=b:120508077 TEST=run CTS, observe tests passing Change-Id: I40cde8e4570e87a6fd192331d69e6deb2891cbf7 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1387348 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver/led/lm3630a: Wait 1ms for I2C to be readyEdward Hill2018-12-231-0/+6
| | | | | | | | | | | | | | | | | | | LM3630A will NAK I2C transactions for 1ms (tWAIT in the datasheet) after HWEN asserted or after SW reset. Add msleep(1) to start of lm3630a_poweron(). BUG=b:119849255 BRANCH=grunt TEST=keyboard backlight still works after resume from S3: suspend_stress_test -c 1 --suspend_min=15 --suspend_max=20 ectool pwmsetkblight 0 ectool pwmsetkblight 100 Change-Id: Ie98e8759c85db6a6f2d8beeee834cabbecfec2c0 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389060 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Support SCP reset stepping stone function.Yilun Lin2018-12-234-1/+28
| | | | | | | | | | | | | | | | | | | | SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m resetting, it would load 0x0 to SP(r13) and load 0x04 to PC(r15). Stepping stones copy these two very special values from CONFIG_RAM_BASE, CONFIG_RAM_BASE + 0x04 to 0x0, 0x4 resepctively. TEST=make BOARD=kukui_scp -j, and see the value from 0x0, 0x4 in kukui_scp/RW/ec.RW.flat are the same as 0x800, 0x804 respectively. TEST=Puts ec.RW.bin on kukui and see that SCP boots. BUG=b:120825336 BRANCH=None Change-Id: I71670d5d4b5ba3aaad17c264a2a3bc3076703a9c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373950 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/cortex-m: Support prevent chip memory region from GC.Yilun Lin2018-12-232-0/+13
| | | | | | | | | | | | | | | | | | | We would like to keep a symbol in a chip memory region from GC in link time. However __attribute__((used)) cannot fulfill the requirement in such situation. This CL adds a "name.keep" section to prevent all the symbols in this section in a chip memory region from GC. Also, we would like to support a non-NOLOAD section, which can load default value on runtime. BUG=b:120825336 TEST=make buildall -j BRANCH=none Change-Id: I76cf445f6b4c0b61c20182a1aaf5a44f962049ae Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373949 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp/uart: Do not use usleep in tx_flush/write_charNicolas Boichat2018-12-231-3/+2
| | | | | | | | | | | | | | | These functions may be called in interrupt/exception context, especially when panic_printf is used. We need to busy-loop. BRANCH=none BUG=b:119929419 TEST=crash divzero works Change-Id: Ie97243afcc433226e78ea1b1225227c6ffbf2a04 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1373288 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/hrtimer: Fix race condition in timer_read_raw_systemNicolas Boichat2018-12-231-2/+11
| | | | | | | | | | | | | | | | | | | When the 32-bit bit timer @26Mhz wraps around, there is a short amount of time when the 32-bit timer value (@1Mhz) is incorrect. Fix this by manually adjusting sys_high if an interrupt is pending. BRANCH=none BUG=b:120173036 BUG=b:120763595 TEST=Boot kukui_scp, leave it running for 200 seconds taskinfo "time in exceptions" look reasonable Change-Id: I053972d018e3e5e9c46cb73a0edb16b0354d5c43 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372871 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* Octopus: correct keyboard backlight flagsstabilize-atlas.11448.BDiana Z2018-12-201-1/+3
| | | | | | | | | | | | | | | Since we're allowing deep sleep on the NPCX EC in the S0 power state, the keyboard backlight should be configured to stay on during sleep in order to prevent it from flashing. BRANCH=octopus BUG=None TEST=builds Change-Id: I1f41b9b00e2808520e773497991d389d23bf25fb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1383195 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Karma: Enable 3A power supply over USB-C portDaisuke Nojiri2018-12-201-1/+1
| | | | | | | | | | | | | | | | This patch makes Karma supply 3A over the USB-C port. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:120794301 BRANCH=none TEST=Verify 5V,3A supplied to Samus, Pixel phone, and Sona. Change-Id: I7b955d470cde9cf5ca44acf685f91cfcadd201ca Reviewed-on: https://chromium-review.googlesource.com/1370933 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* audio_codec: add audio codec featureCheng-Yi Chiang2018-12-204-0/+9
| | | | | | | | | | | | | | | | | | | | This CL adds support for the audio codec feature required to support dmic and I2S operation. BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: I2b3ba097aaf6a7854551db2033914d00ac3ec275 Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1192702 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* Kalista: Remove charger and USB-PD DRP supportDaisuke Nojiri2018-12-204-154/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Kalista doesn't have a battery, thus, doesn't need to manage charging or monitor battery status. Kalista is always a source device. Its USB-C doesn't need to toggle. Since it's not a mobile device, it doesn't need to put a TCPC in low power mode. * Charge Pixel phone via USB-C port at 1.5A, 5V * Display picture on HDMI monitor via Hoho * HP 240s (DRP monitor) * USB3 flash driver via USB-C to A dongle - Suzy-Q doesn't work (as expected) Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:111571989,b:118386334 BRANCH=none TEST=See above. Change-Id: I5771d77483472f918072e339311fb1c392df5d5d Reviewed-on: https://chromium-review.googlesource.com/1300617 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* rammus: reconfig the PS8751 i2c port according to the board versionZhuohao Lee2018-12-204-2/+34
| | | | | | | | | | | | | | | | | | | | | | | On Shyvana, we found that if we put the Parade PS8751 and Analogix ANX3447 on the same i2c bus, the ANX3447 would be broken because of PS8751 i2c bus error. To avoid this kind of problem, we decided to separate the TCPC i2c bus starting from board version >= 2. The new assignment are ANX3447:i2c_0_0, PS8751:i2c_0_1. This patch also adds a new config CONFIG_USB_PD_TCPC_RUNTIME_CONFIG for enabling runtime switching the TCPC setting. BUG=b:118063849 BRANCH=firmware-rammus-11275 TEST=verified on DUT with board_version <= 1 verified on reworked DUT with board_version >= 2 Change-Id: I0bdc930c1a5e691239f5f5c256d380d0111eed91 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1381600 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nocturne: Discharge VBUS when stopping sourcing.Aseda Aboagye2018-12-201-1/+7
| | | | | | | | | | | | | | | | When the source power path is turned off, we should discharge VBUS. BUG=none BRANCH=firmware-nocturne-10984.B TEST=Flash nocturne, PR_SWAP, verify that VBUS is discharged instead of floating during the swap. Change-Id: I30cbb85cefc70ef161853758ece57b324eab0014 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1385445 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50_fuzz: Fix build errors related to nvmem_wipe_cache.Allen Webb2018-12-202-6/+10
| | | | | | | | | | | | | | | | The declaration of nvmem_wipe_cache is now inside the extern "C" section and a definition was added to cr50_fuzz. BRANCH=None BUG=None TEST=make -j buildall Change-Id: Ie7401d8880e7982c84fa6a5df5015cbd145fc6d1 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1370746 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: lpc: don't set SHCFG[7:5] in the driver's initializationCHLin2018-12-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | In older Nuvoton EC chips (prior NPCX5), the Semaphore register is mapped to offset 0 of the Shared RAM Window by default. We usually disable it in the driver by setting SHCFG[7:6] both to 1 if we want to disable the Semaphore mechanism. However, in NPCX5 and later chips, this behavior is deprecated (the Semaphore register is not mapped to offset 0 of the Shared RAM Window by default). These bits (including bit 5) were removed. The driver should keep these bits at their default state. Otherwise, the Semaphore mechanism may not work as expected. BRANCH=none BUG=b:73018524 TEST=pass make buildall. TEST=build and flash reef/grunt/yorp image, stress test the host command and host event, no symptom occurs. Change-Id: I63031f3957d0485f18fb8c4f1b13ad56c2dc5804 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1383675 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kukui: Add initial kukui_scp board for SCP developmentRong Chang2018-12-206-2/+156
| | | | | | | | | | | | | | | | | | | Kukui is the first project with Chromium OS EC based SCP. This is an base board to develop SCP functionalities. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j Change-Id: I65897d5439e88cebdc6543e5a8e07cd5657303e7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208772 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scp: Add mt_scp chipRong Chang2018-12-2010-0/+1618
| | | | | | | | | | | | | | | | | | | | | | | SCP is a Cortex-M4 based sensor hub in Mediatek SoC. This change adds the chip folder and system level drivers. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j copy ec.bin to /lib/firmware/scp.img echo 'stop' > /sys/class/remoteproc/remoteproc0/state echo 'start' > /sys/class/remoteproc/remoteproc0/state check EC uart console Change-Id: I6629149f352184108fa520e80b59fd2ce94c76f7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208770 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/minute-ia: enable cacheKyoung Kim2018-12-201-0/+9
| | | | | | | | | | | | | | | | Enable cache CR0.CD and CR0.NW Trackpad frame processing improved with cache on. BUG=b:120885570 TEST=check overall performance improvement including TP frame processing. Change-Id: I18d27b28255d5775c71b7562e18a1d102ee35feb Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1378659 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* Makefile.rules: Add buildfuzztests to buildall.Allen Webb2018-12-193-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This incorporates the fuzz targets into buildall and adds a quick sanity check to each fuzz target to make sure it exits successfully for an empty input. This adds roughly 5.88 seconds to "make -j buildall" (This includes an addtionally target that will be enabled in a later CL). time make -j buildall # BEFORE real 1m19.519s user 23m9.220s sys 5m1.690s time make -j buildall # AFTER real 1m25.399s user 23m35.753s sys 5m12.609s BRANCH=None BUG=None TEST=make -j buildall Change-Id: Ib77a57297ee896569c509d0c8c998552d2a3a76c Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1370934 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* core/minute-ia: default_fp_ctx[] should be staticRushikesh S Kadam2018-12-191-1/+1
| | | | | | | | | | | | | | | | Define the default_fp_ctx[] for initial FP state as static variable. BRANCH=none BUG=b:120582727 TEST=Succesfully compile for ISH target Change-Id: Iac60a814ab7a9c3090b47472adebf05b1341c5fb Reported-by: Caveh Jalali <caveh@google.com> Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1365155 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* system: Make system_can_boot_ap return true for AC-only systemsDaisuke Nojiri2018-12-191-16/+14
| | | | | | | | | | | | | | | | | | This patch makes system_can_boot_ap return true for systems which can be powered only by a fixed AC power (e.g. barrel jack AC adapter). Such systems do not need to check a battery percentage or AC power. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Icd59b508e944c43253d416da78d0f1a87fedb13d Reviewed-on: https://chromium-review.googlesource.com/1301935 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* USB-PD: Fix build errors for non-DRPDaisuke Nojiri2018-12-191-2/+8
| | | | | | | | | | | | | | | | | | | This patch fixes build errors for devices which don't use DRP ports. pd_restart_tcpc is called within DRP context. So, the static definition has to be excluded accordingly. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG= BRANCH=none TEST=buildall Change-Id: I51decb0a2071230da3cdd91139f77d94b685ca5f Reviewed-on: https://chromium-review.googlesource.com/1300616 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* casta: Add flash_ec supportPhilip Chen2018-12-181-0/+4
| | | | | | | | | | | | | BUG=b:119174492 BRANCH=octopus TEST=None Change-Id: I978bebd91f1098d4de799e2cceff0df6e1af3f3c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1380712 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Ampton: modify the led behavior when battery errorJames_Chao2018-12-181-2/+2
| | | | | | | | | | | | | BUG=none BRANCH=octopus TEST=check the led behavior when battery error Change-Id: I9680b7011bb88e5e064f67ae3625534945b5dff7 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1381597 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpc: remove reset check in alert handlerJett Rink2018-12-181-4/+12
| | | | | | | | | | | | | | | | | | | If the image supports TCPC low power mode, then we already initialized the devices after exiting low power mode. No need to check again. BRANCH=none BUG=chromium:875274 TEST=On an octopus board, PS8751 and ANX3447 work with TCPC smoke test of plugging/unplugging Change-Id: I54e9038db87f9cf998431263df0cf8fa254bde83 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1379705 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* core/minute-ia: Reset Task-switched flag during initRushikesh S Kadam2018-12-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | It is observed that CRO.TS may be set prior to main ISH FW entry. In such case, an ESC instruction such as fninit assembly instruction for FPU initialization, will cause a fault. The execution handlers are not setup this early in FW initialization phase, and will lead to ISH CPU reset. This patch resets the TS flag in early FW initilization. BRANCH=none BUG=b:120051132 TEST=Test host FW loading for main ISH FW. Change-Id: I7e330e2d1f39cc4a349f308ec0d046c19db281de Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316702 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* core/cortex-m: Support chip with no flash.Rong Chang2018-12-181-2/+15
| | | | | | | | | | | | | | | | | Linker script verifies flash size and layout when generating firmware binary. This configuration macro removes FLASH section and asserts. BRANCH=none BUG=b:114326670 TEST=make buildall -j Change-Id: I3c9ce6f930260d780839e52b45055f88cc22f85f Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208771 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/cortex-m*/task: Record 32-bit exception timesNicolas Boichat2018-12-182-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | "time in exceptions" looks unreasonable after > 4294s (when 32-bit microsecond timer wraps around). This is because core/cortex-m/task.c:svc_handler records time exc_start_time just before the interrupt handler for 32-bit timer interrupt runs, so the high word of the system clock (clksrc_high) is not updated yet (while the low 32-bits already wrapped around). After the handler runs, clksrc_high is updated, so there appear to be a 4294s gap between the 2 measurements. Fix this by recording the low 32-bit timer value only. There will never be more than 4294s between exceptions, and this fixes the wrap-around issue as well. BRANCH=none BUG=chromium:914208 TEST=Flash kukui (cortex-m0) and kukui_scp (cortex-m), let system run for 4300+s, no more accounting error in "Time in exceptions". Change-Id: If52855ef093ac1a1d38432555694c83742feb8f1 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372876
* core/minute-ia: Add missing #ifdef CONFIG_FPURushikesh S Kadam2018-12-181-0/+2
| | | | | | | | | | | | | | Fix compilation error generated with CONFIG_FPU disabled. BRANCH=none BUG=b:120051489 TEST=Disable CONFIG_FPU and verify code compiles fine. Change-Id: I0ddfe610a33cc2bdebebed4e149afbfa92f2543a Reported-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316701 Reviewed-by: Caveh Jalali <caveh@google.com>
* it83xx/intc:add type-c plug in interruptRuibin Chang2018-12-185-0/+53
| | | | | | | | | | | | | | | When tcpc detect type-c plug in (cc lines voltage change), it will interrupt fw to wake pd task, so task can react immediately. BRANCH=None BUG=None TEST=GRL USBPD test Change-Id: I194b2fcad1d0c62dde2d3296753abd47af8feea6 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1333207 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpc: wait for TCPC wake up upon first accessJett Rink2018-12-183-90/+98
| | | | | | | | | | | | | | | | | | | | Previously we tried to perform i2c communication with the TCPC when it was in low power mode and only if the i2c transaction failed did we wait for the device to wake up. Now that the PS8751 will respond to i2c transaction (ACK them) when it is in LPM, ensure the init happers before we start talking to the device to handle an interrupt. BRANCH=none BUG=b:118063849,b:121109893 TEST=verify that plug and unplug for PS8751, ANX3429, and ANX3447 LPM still works. Change-Id: I8c18195e55ee6d04af7d4ff24230a3bd2d147d53 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1375102 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* atlas: enable active discharge on all railsCaveh Jalali2018-12-182-4/+22
| | | | | | | | | | | | | | | | this enables active discharge on all 12 power rails controlled by the ROHM ROP PMIC. BUG=b:120619543 BRANCH=none TEST=discharge behavior verified by sajedfarzam@ Change-Id: I842dbdcc1eab596230e12130dca272a1f449e268 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1371226 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: clear confidential TPM Data on TPM disablingNamyoon Woo2018-12-181-0/+24
| | | | | | | | | | | | | | | | | | | | On TPM disabling, AUTH/SEED/PROOF data in TPM persistent data set and the loaded objects shall be cleared for better security. CQ-DEPEND=CL:1362203 BRANCH=cr50 BUG=b:119221935 TEST=Tested manually on eve-campfire dual boot dut. Checked S3 resume from short|long suspend on Windows. Checked Warm reboot from Windows to Chrome OS. Checked Warm reboot from Windows to Windows. Checked Chrome OS login info preserving. Change-Id: I8e03f6242cf04e7c824ee54cca99413eb809edea Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372029 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* board/atlas_ish: remove CONFIG_ISH_30 flag in atlas_ish boardShine Liu2018-12-181-1/+0
| | | | | | | | | | | | | | | | As we have replaced all all CONFIG_ISH_xx flags in in chip/ish/* files with CHIP_FAMILY and CHIP_VARIANT, abandoning original CONFIG_ISH_xx flags. BRANCH=none BUG=b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: Ie0635a49585d456504bd1027406c5d6929dc5a8c Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367011 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* chip/ish: replace CONFIG_ISH_xx flags with CHIP_FAMILY and CHIP_VARIANTShine Liu2018-12-184-19/+17
| | | | | | | | | | | | | | | | | Replace all CONFIG_ISH_xx flags in chip/ish/* files with CHIP_FAMILY and CHIP_VARIANT. Which provides more structural defines between ISH generations. BRANCH=none BUG=b:120295222 b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: Ica92eee11034447c9f0828aa986fb1736d20cf27 Signed-off-by: Shine Liu <shine.liu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367010 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board/atlas_ish: add CHIP_FAMILY and CHIP_VARIANT to atlas_ishShine Liu2018-12-181-0/+2
| | | | | | | | | | | | | | | | To accommodate the changes coming to ISH chip generations including CHIP_FAMILY and CHIP_VARIANT instead of current defines of CONFIG_ISH_xx. BRANCH=none BUG=b:120295222, b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: I03af74aa1b45cd4d1f030489a171506064721b3c Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367009 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32mon: Add link to SPI protocolTom Hughes2018-12-171-1/+4
| | | | | | | | | | | | | Also fix misspelling. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6e17407be36abd83567a2e09ae1c2684e1bc5090 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1378907 Reviewed-by: Jett Rink <jettrink@chromium.org>
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