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* chgstv2: Unify power-on and shutdown battery thresholdsDaisuke Nojiri2021-06-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, power-on battery SoC and shutdown battery SoC are independently configured by each board. This patch will unify the setting as follows: CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%) CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%) BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%) CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed) CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1 This allows us to show the low battery alert whenever we can because EC doesn't inhibit power-on even if it knows the host would immediately shut down. With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery threshold (and the SoC will be agreed between the EC and Powerd). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the same threshold. This is for avoiding degrading the UX by increasing the power-on threshold (even though a question that 1% may not be enough for soft sync to finish consistently remains to be answered). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a lower threshold but we think 2% is enough to finish the software sync. A lower threshold also improves the UX by showing the low battery alert in the situation where otherwise the system would leave the user uninformed by not responding to a power button press. BUG=b:191837893 BRANCH=None TEST=buildall Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* config: Rename CONFIG_CROS_BOARD_INFOPhilip Chen2021-06-161-1/+1
| | | | | | | | | | | | | | | | | | Rename CONFIG_CROS_BOARD_INFO to CONFIG_CBI_EEPROM to make it clear that the information comes from on-board EEPROM. It sets up the groundwork for adding more options of CBI sources later. BRANCH=None BUG=b:186264627 TEST=make buildall -j Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I9a6feee0a8b35bbf29e445544243485507767ad8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2945792 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* bq25710: Consolidate NARROW_VDC definitionCaveh Jalali2021-03-231-1/+0
| | | | | | | | | | | | | | | | | This consolidates the selection of CONFIG_CHARGER_NARROW_VDC to config.h for the bq25710 and bq25720 charger chips. The driver requires NARROW_VDC to be enabled, so move this setting to config.h similar to other chargers. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I6c1768aff5d581544c4b7182f32ec45851a3a243 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2780831 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* config: Fix inconsistent VBUS measurement configAbe Levkoy2021-01-221-5/+0
| | | | | | | | | | | | | | | | | | Remove CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT from boards that define CONFIG_USB_PD_VBUS_MEASURE_CHARGER. This change is a no-op, because charge_manager.c is the only place where CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT is checked, and it is only checked if CONFIG_USB_PD_VBUS_MEASURE_CHARGER is not defined. BUG=b:178102402 TEST=make buildall TEST=Build sizes before and after change are the same BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ia3caa57a8531a5cba549b64c9087c337996af9c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2642892 Reviewed-by: Diana Z <dzigterman@chromium.org>
* config: Provide default VCONN Swap delayAbe Levkoy2021-01-221-1/+0
| | | | | | | | | | | | | | | | | Almost every relevant board copy-pastes 5000 us. Make that the default and get rid of the redundant definitions. This is the approximate result of this command: find . -type f -name *.h | xargs sed -i -E \ '/#define CONFIG_USBC_VCONN_SWAP_DELAY_US[[:space:]]+5000[[:space:]]/d' BUG=b:144165680 TEST=make buildall BRANCH=none Change-Id: Ife86f9752971abcd7ab5ad5a5e607eb2ccbde2ba Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* config: Make VCONN Swap delay a documented optionAbe Levkoy2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This is the approximate result of the following command, run from platform/ec: find . -type f -\( -name '*.c' -o -name '*.h' -\) | \ xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g' Fix some latent formatting errors in usb_pd_protocol.c, because they were preventing pre-upload hooks from passing. BUG=b:144165680 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Move tcpic.h header into include/driverSimon Glass2021-01-072-2/+2
| | | | | | | | | | | | | | | | | | This header cannot currently be accessed by Zephyr since it is in a driver directory, not an include directory. This header has quite a bit of public stuff in it, so it seems reasonable to consider everything public. Move the header file and update all users. BUG=b:175434113 BRANCH=none TEST=make buildall -j30 build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ibba37f47a06783fafb5095f853f2a68d92b6df87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607745
* tcpm: Move tcpm.h into an include directorySimon Glass2020-12-221-1/+1
| | | | | | | | | | | | | | | | | | This header file is used from quite a few files, relying on the EC build system to find includes in the driver/tcpm directory. For Zephyr we don't want to add that as an include. It makes more sense for header files to be in an include directory, so move it and fix up the users. BUG=b:175434113 BRANCH=none TEST=build Zephyr and ECOS on volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985 Reviewed-by: Keith Short <keithshort@chromium.org>
* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-051-1/+1
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: enable selecting EC's VCCDino Li2020-10-081-0/+2
| | | | | | | | | | | | | | | | | | | The VCC is the power source of EC's GPM0~6, will connect to 1.8v or 3.3v depended on platform design. This change was made to ensure voltage level setting of GPM0~6 matches the corresponded VCC level. So we can enable internal pull-up no matter VCC is connected to 1.8v or 3.3v BUG=b:168783892 BRANCH=none TEST=- buildall. - The level setting is correct on these boards: asurada, drawcia, and reef_it8320 Change-Id: I4eae368e569987381a0437494262d588436bb011 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2397931 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Charger: Add dynamic charger chip countDiana Z2020-07-111-1/+0
| | | | | | | | | | | | | | | | Different DB options may cause different numbers of charger chips to be present on the system. Remove constant count for charger chips, and instead always call into the overridable function to query the count. BRANCH=None BUG=b:155963446 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0e65b8af351ecabe6f7b823e0e56f1932cc280a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2277833 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd: Rename CONFIG_CMD_PD_CONTROL to CONFIG_HOSTCMD_PD_CONTROLVijay Hiremath2020-05-151-1/+1
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLakeKeith Short2020-04-091-0/+13
| | | | | | | | | | | | | | | | | | | | | Configure PWROK generation related signals for Ice Lake, Tiger Lake, and Jasper Lake SoCs. The array driven sequencing provides better flexibility for the PWROK signals, some of which may be automatically handled by the platform and some require EC control. BUG=b:150726713 BRANCH=none TEST=make buildall TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and verify signals are deasserted when exiting S0. TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK, verified JPL sequences to S0. Change-Id: Iceae29c65398643839b31f6cd757352282849fda Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* it83xx/gpio: disable unused cc port moduleRuibin Chang2020-04-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | To prevent cc pins leakage and cc pins can be used as gpio. We will check if the chip supported tcpc physical port count is more than board active ITE port count. If yes, we will disable unused cc port module. BUG=none BRANCH=none TEST=1) on board it8xxx2_pdevb with chip it81202, check the pd port connection with adapter and dongle when hibernate and resume. adapter: connect dongle: disconnect then re-connect 2) on board it83xx_evb with chip it8320, set cc pins as gpio, check output level when hibernate and resume. Change-Id: I13511741b2e066dd87277db9f71f2b4a9323ad6d Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994693 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_mux: retimer: mux as chained mux and retimerDenis Brockus2020-02-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes retimers appear as generic muxes. By allowing a chain of muxes they can be stacked up to the new configurations that zork requires and will continue to work as they did before on configurations that only have a single mux. The code used to have two different arrays, 1) muxes and 2) retimers. On one of the zork configurations the processor MUX stopped being the primary mux and the retimer took its place. In a different configuration of that same platform it left the primary and secondary alone but the mux_set FLIP operation had to be ignored. Since the same interfaces needed to be available for both it stopped making sense to have two different structures and two different methods of handling them. This consolodates the two into one. The platforms that do not have retimers, this change will not make any difference. For platforms like zork, it will remove the retimers and make them chained muxes. So testing on trembyle makes sense to verify, BUG=b:147593660 BRANCH=none TEST=verify USB still works on trembyle Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMV1/2: Make the PD Config Flags more consistentSam Hurst2020-02-221-0/+2
| | | | | | | | | | | | | | | | | | | | The current use of the PD Config Flags are a bit confusing and has been changed to the following: The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY is enabled, one of the following must be enabled: CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine CONFIG_USB_PD_TCPMV2 - current power delivery state machine BUG=b:149993808 BRANCH=none TEST=make -j buildall Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519 Reviewed-by: Diana Z <dzigterman@chromium.org>
* driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2Ruibin Chang2020-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PD driver for chip it8xxx1/8xxx2 series. BRANCH=none BUG=none TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1 (set cc toggle by console cmd): 1.pin configuration console cmd "gpioget" check gpio settings. memory dump check cc pin alternate settings. 2.Tx data error handle Message discard, No GoodCRC, Tx not enable, Timeout errors happen, corresponding INT will be triggered then do properly handle. 3.basic pd connection SNK:connect with adaptor, request max power (15V,3A), state SNK_READY. SRC:enable DRP role, connect with dongle, provide power (5V,1.5A), source Vconn 5v, get ack of cable discover id, state SRC_READY. 4.pd module disable SNK:connect with adapter. console cmd "hibernate sec", driver disable pd module, check still connection with adapter via dead battery rd. And when resume from hibernate, pd init can re-enable pd module, re-connect with adapter. SRC:connect with dongle. console cmd "hibernate sec", driver disable pd module, check cc pin (not Vconn source pin) volt power down to ~0v. And when resume from hibernate, pd init can re-enable pd module, re-connect with dongle. 5.Tx hard reset console cmd "pd port hard", check hard reset message by lecroy analyzer. 6.Tx cable reset check cable reset message by lecroy analyzer. 7.SOP' enable SRC:connects to SNK via E-mark cable. Source Vconn successfully, and receives cable's ack of discover id request. Not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 8.power role swap console cmd "pd port swap power", check pd protocol by lecroy. Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Charger: Convert boards to use new driver structureDiana Z2020-02-041-0/+11
| | | | | | | | | | | | | | | This commit removes the temporary common charger chip configuration and instead puts the configuration in each board. BRANCH=none BUG=b:147672225 TEST=builds, runs on waddledoo and octopus Change-Id: If81aef31e48c65999a87e202494f286716114bbb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: cleanup pd_get_data_roleDenis Brockus2020-01-091-1/+2
| | | | | | | | | | | | | | | This is the second half of b/147290482 Cleaning up to use pd_data_role instead of int BUG=b:147314832 BRANCH=none TEST=make buildall -j Change-Id: I2445b06f5f5469fb1f3a968034a83e3ee792e7c7 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991845 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* usb_pd_policy: Make a lot of objects commonAseda Aboagye2019-12-101-315/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a board specific usb_pd_policy.c file that contains a lot of code for handling DisplayPort Alternate mode, Google Firmware Update Alternate mode, as well as some PD policy functions such as deciding to Accept or Reject a data role swap or a power role swap. Several boards simply copy/paste this code from project to project as a lot of this functionality is not actually board specific. This commit tries to refactor this by pulling the functions that are not mainly board specific into common code. The functions are made overridable such that boards that truly do require a different implementation may do so. Additionally, this consolidation changes the policy behaviour for some boards, but they should be for the better. Some examples include that data swaps are always allowed if we are a UFP (no system image requirement), power swaps are allowed to become a sink if we are no longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is not entered if the AP is off. In order to facilitate this refactor, a couple CONFIG_* options were introduced: - CONFIG_USB_PD_DP_HPD_GPIO /* HPD is sent to the GPU from the EC via a GPIO */ - CONFIG_USB_PD_CUSTOM_VDO /* * Define this if a board needs custom SNK and/or SRC PDOs. * * The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating * Dual-Role power, USB Communication Capable, and Dual-Role data. * * The default SNK PDOs are: * - Fixed 5V/500mA with the same PDO_FIXED_FLAGS * - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV, * operational current PD_MAX_CURRENT_MA, * - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power * PD_OPERATING_POWER_MW */ BUG=chromium:1021724,b:141458448 BRANCH=<as many as we can that are still supported> TEST=`make -j buildall` TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety of DP peripherals TEST=Repeat above with a nocturne TEST=Repeat above with an atlas Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-013-8/+8
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-311-1/+1
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+2
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tglrvpu_ite: Adding VCONN supportAyushee2019-08-231-1/+1
| | | | | | | | | | | | | | | Added GPIOs pin config to support VCONN on tglrvp. Also added power switch function to enable/disable VCONN according to the cc lines. BRANCH=None BUG=b:139763031 TEST=Able to get characteristics of an E-marked cable Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591 Reviewed-by: Keith Short <keithshort@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-202-5/+5
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-192-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-132-36/+0
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* icelake: Add option to turn-off 5V-rail in power sequencingVijay Hiremath2019-06-111-0/+1
| | | | | | | | | | | | | | | | | | | Need to enable or disable the 5V-rail in power sequencing to support boards with 5V-rail. This CL is a derivative of Cometlake CL. Change-Id: Ia1acd5a592f60973a3b852a987e93283f10d0ac0 Reviewed-on: https://chromium-review.googlesource.com/1503956 BUG=b:134688223 BRANCH=none TEST=Able to control 5V-rail of ICLRVP Change-Id: Iefaa1091e863c1c431ea784d2e02478ce67f8911 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647369 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-2/+7
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-04-171-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* hatch: Add support for charging and USB type CScott Collyer2019-01-291-0/+1
| | | | | | | | | | | | | | | | | This CL adds board specific files and functions required for both battery/charging and Type C support. BRANCH=none BUG=b:122251649 TEST=make buildall, tested both port 0/1 operation at factory. Battery can be charged via both ports. Change-Id: Ia01eabe109e3df780ec053831a71a16a41047f01 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1387585 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* dragonegg: Enable ESPI & MKBP host command configVijay Hiremath2019-01-092-1/+5
| | | | | | | | | | | | | | | | | | | | | | 1. CONFIG_HOSTCMD_ESPI - Enabled host commands over ESPI at baseboard level. 2. CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS - Enabled virtual wire sleep signals. 3. CONFIG_MKBP_EVENT - Enabled MKBP events needed for PD events. 4. CONFIG_MKBP_USE_HOST_EVENT - Trigger MKBP event from host events as there is no dedicated GPIO for it. BUG=b:119091888 BRANCH=none TEST=EC console command 'powerindebug' shows virtual wires Change-Id: Ic2e190c47e8eccbf44cce35e58be797692aebe8d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1318219 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Enable CBI functionality.Scott Collyer2018-10-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds config options required for CBI EEPROM functions. BUG=b:117120739 BRANCH=none TEST=On Dragonegg with only SKU_ID set. > cbi [611.873160 CBI Reading board info] CBI_VERSION: 0x0000 TOTAL_SIZE: 12 BOARD_VERSION: (Error 1) OEM_ID: (Error 1) SKU_ID: 2 (0x2) 43 42 49 3b 00 00 0c 00 02 02 02 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Change-Id: Ica731af20e50976d365ab72cf562f06e94e13167 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1262856 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Shelley Chen <shchen@chromium.org>
* DragonEgg: Rely on BATT_PRES_ODL for battery_hw_presentScott Collyer2018-10-101-3/+11
| | | | | | | | | | | | | | | | | | P0 boards required a FW workaround for the battery present signal as it always read high. Starting with P1, this issue has been fixed in HW. This CL relies on the board id to determine which method to use for determing battery presence. BUG=b:117120739 BRANCH=none TEST=Tested on P0, verified that battery charging still works. Change-Id: I28eeca9f27244c6cac54ce032caf7c1073a110c2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1256183 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add support for BC 1.2 detectionScott Collyer2018-10-022-2/+26
| | | | | | | | | | | | | | | | This CL adds board specific support for BC 1.2 detection. BUG=b:113267982 BRANCH=none TEST=Tested on DragonEgg with both USB DCP and SDP chargers. Verified HW ramp set charge level when attaching suzyq cable. Change-Id: Ic610d3cea62883325a02a7fc9f244764842e424d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208523 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-2/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* DragonEgg: Add support for port 2 Type CScott Collyer2018-09-133-3/+54
| | | | | | | | | | | | | | | | | This CL adds support for Type C port 2 which uses the TI USB422 TCPC and NX20P3481 PPC. BUG=b:111281797 BRANCH=none TEST=Verifed that port 2 works as a sink and source. Change-Id: I7ad200768d81fd95aee625e5871b2350412a4f79 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178997 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add support to Type C port 1Scott Collyer2018-09-042-2/+28
| | | | | | | | | | | | | | | | | | | | Port 1 uses the ITE builtin TCPC, Silergy SYV682A PPC, and the parade PS8818 redriver. Port 1 is intended to use the EC ADC to detect VBUS, but port 0 and 2 require different methods. The Silergy can detect VBUS (not safe0V or safe5v), so currently the PPC is being used to detect VBUS. BUG=b:111281797 BRANCH=none TEST=Verified that port 1 can attach as both a sink or source. Change-Id: Iad0c3d509961c836cd55f77cd5f276c1a3e5aacf Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159829 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* DragonEgg: Add config options and task for keyboard scanScott Collyer2018-08-082-0/+30
| | | | | | | | | | | | | | | | Keyboard scan was not working as the KEYSCAN task was not added and some of the keyboard config options were not defined. BUG=b:112110028 BRANCH=none TEST=Verified that keyboard inputs are received now and sent to AP Change-Id: I36c053d807e83477e044857f5087dcccdf891bfa Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159835 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add control for display backlightScott Collyer2018-08-011-0/+4
| | | | | | | | | | | | | | | BUG=b:111901516 BRANCH=none TEST=Verfifed with gpioget that this signal is high following 'lidopen' EC console command and low following 'lidclose' command. Change-Id: I34bad96c747f254b339c4a7fafb56f6d09cb61c8 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1153552 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add vboot config options to baseboard.hScott Collyer2018-08-011-0/+5
| | | | | | | | | | | | | | | | This CL adds the config options required for VBOOT_HASH. BRANCH=none BUG=b:111892098 TEST=Verified that AP boots into depthcharge. Change-Id: I051472322d0aab2047246150a2770b34c49b0b0e Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1152233 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Workaround for EC_BATT_PRES_ODL being incorrectScott Collyer2018-08-012-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The signal EC_BATT_PRES_ODL reads high unless the battery is connected and a cold reset is applied to the board. The signal is floating at ~2V and that issue is being investigated. To enable the battery to be charged, this CL replaces reading the GPIO signal with the ability to read the Operation Status register. BUG=b:111704193 BRANCH=none TEST=Verified that when connected the battery is recognized and can be charged. > battery Status: 0x0080 INIT Param flags:00000003 Temp: 0x0bd4 = 302.8 K (29.7 C) V: 0x21cc = 8652 mV V-desired: 0x2260 = 8800 mV I: 0x0beb = 3051 mA(CHG) I-desired: 0x103e = 4158 mA Charging: Allowed Also tested that after issuing cutoff command, the battery wakes up when I connect AC. Change-Id: Id591329071396bd33ade5d773c77ed584979802a Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1149503 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add support for Type C port 0, charging, and batteryScott Collyer2018-07-315-0/+700
| | | | | | | | | | | | | | BRANCH=none BUG=b:111281797 TEST=make buildall Change-Id: I2f4342f2c9ddfb4a6b2debbf94c1b0589227b58c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1135928 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add power sequencing supportScott Collyer2018-07-272-1/+118
| | | | | | | | | | | | | | | | This CL enables power sequencing for DragonEgg. BRANCH=none CQ-DEPEND=Iab4423abc9102164d4f43296a279c24355445341 BUG=b:111121615 TEST=make buildall Change-Id: Id8c48a74b7b83153dc253222edc515c2488e7af5 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126407 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add I2C pins/alt functions and config tableScott Collyer2018-07-032-1/+26
| | | | | | | | | | | | | | | | | | This CL adds the gpio definitions for I2C pins and the I2C configuration table. BRANCH=none BUG=b:110880394 TEST=make buildall Change-Id: I9d239573257dbd6a3a3110875b1c970721f73677 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1117361 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Rachel Nancollas <rachelsn@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Initial skeleton for DragonEggScott Collyer2018-06-273-0/+26
This CL adds DragonEgg in /board and /baseboard. Only minimal gpio signals are defined to allow successful build. The /baseboard files are currently empty, but the plan is to use baseboard for functions that will be common for ite EC and ILK. BRANCH=none BUG=b:110880394 TEST=make buildall Change-Id: Ia018692f277efaceef85a060b6585accc82fddfd Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1117133 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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