| Commit message (Collapse) | Author | Age | Files | Lines |
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Once Sensors are enabled, there is a lot of host command traffic.
Change chan mask to prevent printf overload.
BUG=None
BRANCH=master
TEST=Less printf on the console.
Change-Id: I5462e1220949821034fa4001bb5cd11942d48c70
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1593952
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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This CL enables CONFIG_CMD_CHARGER_DUMP which enables the EC console
command 'charger_dump'.
BUG=b:130209125
BRANCH=none
TEST=manual
>charger_dump
2019-04-30 17:47:16 25710 REG 12: e70e
2019-04-30 17:47:16 25710 REG 14: dc0
2019-04-30 17:47:16 25710 REG 15: 2260
2019-04-30 17:47:16 25710 REG 20: 8400
2019-04-30 17:47:16 25710 REG 21: a804
2019-04-30 17:47:16 25710 REG 22: 3b00
2019-04-30 17:47:16 25710 REG 23: b700
2019-04-30 17:47:16 25710 REG 24: 0
2019-04-30 17:47:16 25710 REG 25: 0
2019-04-30 17:47:16 25710 REG 26: 0
2019-04-30 17:47:16 25710 REG 30: 210
2019-04-30 17:47:16 25710 REG 31: 40b7
2019-04-30 17:47:16 25710 REG 32: 30
2019-04-30 17:47:16 25710 REG 33: 265
2019-04-30 17:47:16 25710 REG 34: 8124
2019-04-30 17:47:16 25710 REG 35: 40
2019-04-30 17:47:16 25710 REG 3b: 0
2019-04-30 17:47:16 25710 REG 3c: 0
2019-04-30 17:47:16 25710 REG 3d: 1c0
2019-04-30 17:47:16 25710 REG 3e: 1800
2019-04-30 17:47:16 25710 REG 3f: 3b00
2019-04-30 17:47:16 25710 REG fe: 40
2019-04-30 17:47:16 25710 REG ff: 89
Change-Id: I614f5afd78f2d8a3c4e6e28d0cc186616a3e5540
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1580183
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Reset polarity was added to tcpc_config so that the reset function
could be common across different boards which have different TCPC
selections. This was applied to pd_reset_mcu(), however, that CL did
not take into account the reset polarity in the tcpc_get_alert_status
function. This CL fixes that oversight.
In addition, this CL fixes the name for kohaku's port 0 TCPC reset
line to match the schematic.
BUG=b:130194031
BRANCH=none
TEST=verified on Hatch that both ports 0/1 function correctly.
Change-Id: I0d75d3655c799d4c74f4a6fb1805c06c1fe99c06
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1582964
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This CL moves bc1.2 configuration from baseboard.c/.h to the
board.c/.h files for hatch and kohaku.
BUG=b:130197995
BRANCH=none
TEST=make -j BOARD=hatch and make -j BOARD=kohaku both are successful
Change-Id: I2aa44d37a7a1d23196a766c95c59737838e9e09f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1574788
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Hatch baseboard contained HDMI support, but Kohaku does not have HDMI
support, so that code is moved to Hatch board specific code instead.
BUG=b:130577280
BRANCH=none
TEST=Kled device still works with HDMI; detects when HDMI is plugged in
and correctly uses the extra display.
Change-Id: Idfcea36068b441c8ad499c1f42f0f0ecf681f978
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1574698
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Move USB Type A support from Hatch baseboard to Hatch board because not
all Hatch variants support Type A.
BUG=b:130577280
BRANCH=none
TEST=Kled device still recognizes Type-A USB flash drive.
Change-Id: I23b21b069727d57b8fea29de5bbf4e255cf3a3a9
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1573019
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Kohaku uses PS8751 for port 0 TCPC. Therefore, the TCPC config and mux
config tables can't be common and must be moved out of baseboard into
their respective board.c files.
BUG=b:130194031
BRANCH=none
TEST=make -j buildall
Change-Id: Iea39e60d675a5ea0df346c52e78f5f472768984c
Signed-off-by: Scott Collyer <scollyer@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1551582
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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tcpc_config contained a field for both the alert polarity and open
drain/push pull configuration. There is also a possible difference in TCPC
reset polarity. Instead of adding yet another field to describe this
configuration, it would be better to convert alert polairty, open
drain and reset polarity into a single flags field.
This CL modifies the tcpc_config struct to use a single flags field
and adds defines for what existing flag options can be.
BUG=b:130194031
BRANCH=none
TEST=make -j buildall
Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e
Signed-off-by: Scott Collyer <scollyer@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1551581
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Enable the shiny new S0ix failure detection code that will wake the AP
after a specified timeout if the system attempted to go into S0ix but
went into a shallower state instead.
BUG=b:123716513
BRANCH=None
TEST=Test S0ix with a modified EC firmware and kernel changes.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ia981cdc34a98bcf877dec78067173bf1c0f9e700
Reviewed-on: https://chromium-review.googlesource.com/1509717
Commit-Ready: Evan Green <evgreen@chromium.org>
Tested-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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EC should send an event to host when the mode change
BUG=b:125355874
BRANCH=none
TEST= On proto boards, rotate your lid sensor until the lid_angle is
270 degree, you will see the log in ec console.
[146.851540 tablet mode enabled]
[146.851961 event set 0x0000000010000000]
And then rotate it back to 90 degree, you will see the log in ec console.
[219.552181 tablet mode disabled]
[219.552606 event set 0x0000000010000000]
Change-Id: Id0f3b5b18fdfd5117fc5feab4472cd2709cb1705
Signed-off-by: zack_yang <zack_yang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1523269
Commit-Ready: Zack Yang <zack_yang@compal.corp-partner.google.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
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This CL adds the config option CONFIG_POWER_PP5000_CONTROL which
enables both power sequencing and bc1.2 detection to request PP5000_A
rail to be either on or off.
BUG=b:122265772
BRANCH=none
TEST=Verfied that bc1.2 detection no longer fails when the AP is in G3.
Change-Id: Iff0d33ce302a0f15687248621fb5d1c6c6df9129
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1503957
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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BUG=b:125933998
BRANCH=none
TEST=build
Change-Id: I4633fc18b259710fd27ecec700d9dc9b5ab462aa
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1510513
Commit-Ready: Philip Chen <philipchen@chromium.org>
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
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This has been enabled on the kernel side now so adding the
corresponding EC config option.
BUG=b:124316213
BRANCH=none
TEST=Manual
Was seeing these messages:
[93.430899 ACPI write 0x06 = 0x8a (ignored)]
[93.431952 ACPI write 0x07 = 0x03 (ignored)]
[93.433216 ACPI write 0x05 = 0x02 (ignored)]
Verfied these messages are no longer being logged and fan is in RPM
mode.
Change-Id: I5109cb1a09ac4ffac47f2cd8e934ce6f1682e916
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1512136
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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The charge hw ramp implementation in the bq25710 is implemented by
enabling ICO (input current optimizer) mode, waiting for it to
complete, then reading optimized current value from the IIN_DPM
register. This is not the correct use case for ICO mode. It has
certain issues, the most serious of which is that if a battery isn't
present or if the battery doesn't have enough charge to power the
system, it will cause PPVAR_VSYS to collapse.
To avoid the issue mentioned above, disable the hw ramp config until
the hw ramp implementation of the bq25710 is reworked.
BUG=b:126229130
BRANCH=none
TEST=make BOARD=hatch and verifed that ICO mode is not longer
activated.
Change-Id: I736c21ad269742650cc62939995c4caa77154b6b
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1512135
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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CL:1479877 has enabled bq25710 charger to measure VBUS.
BUG=b:124968142
BRANCH=none
TEST=build
Change-Id: Id08797e6c668acc96a4fc6c7805e1bd01885b0be
Signed-off-by: Philip Chen <philipchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1496159
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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This CL adds the config options required for the BMA253 lid accel
sensor. It also adds the configuration table, mutex, and rotation
matrix.
BUG=b:124337208
BRANCH=none
TEST=Verified the sensor readings using 'accelinfo on 10000' and the
numbers change on the desired axis when the sensor is moved. The signs
can't be verified yet because it's not properly mounted on P0.
Change-Id: I2943a82a91472d105d97dba76917f40817f5624e
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1468865
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This CL adds the motion_sensor_t table, config options, gpio interrupt
signal, and rotation matrix required for the bmi160 base accel/gyro
sensor.
BUG=b:124337208
BRANCH=none
TEST=Verfied with 'ectool motionsense' that sensor readings are
present and that values move in the expected direction as I rotated
the unit along it's X and Y axis. Also verified the gyro sensor
returns non-zero values when moving the system.
Change-Id: I57c323916662a4ee0b9aa3fc00c3a4bf18aaef40
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1464393
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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EC_PROCHOT_ODL is active low.
BUG=b:123931545
BRANCH=none
TEST=boot the board and verify EC doesn't pull EC_PROCHOT_ODL low
Change-Id: Ida070a106e29aaf830dc38f76bb4f046c6d1fb49
Signed-off-by: Philip Chen <philipchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1471283
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This CL adds the config options and GPIO signals and interrupt handler
required for bc1.2 for the pi3usb8201 chip.
BUG=b:123995100
BRANCH=none
TEST=Verified that bc1.2 detection occurs following connecting a charger
and a EC reboot. Verified that the D+/D- switches are closed in both
client and host mode as expected.
Change-Id: I43ca74f02d2515dc4dfa3dd8dc689d719779e4b5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1459822
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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These config options were commented out to remove S0iX for initial
board bring up. But, now these should be enabled.
BUG=b:124332057
BRANCH=none
TEST=Manual
Issued the following commands on the AP console to force S0iX:
iotools mmio_write32 0xfe001b1c 0xabc0900a
echo freeze > /sys/power/state
Then verified the EC sees the S0iX state:
> powerinfo
[100.716103 power state 4 = S0ix, in 0x003e]
> powerindebug
power in: 0x003e
debug mask: 0x0000
bit meanings:
0x0001 0 SLP_S0_DEASSERTED
0x0002 1 SLP_S3_DEASSERTED
0x0004 1 SLP_S4_DEASSERTED
0x0008 1 RSMRST_L_PGOOD
0x0010 1 PP5000_A_PGOOD
0x0020 1 ALL_SYS_PWRGD
Change-Id: Ied116e9e1e3c90eba5077ba22f03573d9e51e1c3
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1469161
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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BUG=b:123950652
BRANCH=none
TEST=EC console shows reasonable battery display pct
Change-Id: I1ef72976359f4e187e9a5f46461299b15bbcf40f
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1459819
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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The MST chip for Hatch needs to be enabled when HPD signal from either
the Port 1 TCPC or HDMI port is high. This CL adds support to
enable the MST chip based on this criteria. For the Port 1 type C
port, the HPD signal level is derived from the USB PD policy level
where the HPD update driver method is called.
BRANCH=none
BUG=b:123894908
TEST=Used external HP Z27n monitor and verifed the display is extended
as expected when it's connected to either port 1 type C port or the
HDMI connector.
Change-Id: I1c46534bc7f32221f9e379dd9c74d5618c8f57e1
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1406496
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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BUG=b:123738227
BRANCH=none
TEST=manually program CBI through 'ectool cbi set' command,
and then confirm the CBI info in flash dump (through
cbi command in ec console)
Change-Id: I616ed2872835ae111336a7342ca906b3fcbbacfd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1453318
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This CL adds the alternate function defines for the 4 PSL wake source
pins, populates the wake pins table, and enables the config option for
PSL mode.
BRANCH=none
BUG=b:123343366
TEST=Use EC console command to force hiberate and verified EC wakes
from hibernate via power button, EC reset, connecting AC
power, and opening of lid switch.
Change-Id: I6d5ad282f53e9090aafd4164510741d7cfe7907a
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1435971
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: Ib831eecb7e6df270a266f723e2fc5040b741e72f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387592
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL adds board specific config options, functions and GPIO signal
required for keyboard backlight support.
BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: Ib60a7c861d2a85939592556437bd6202e6815947
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387590
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL adds config options and GPIO alternate function definitions
required for adding keyboard scan functionality.
BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: I9511f936e12d25276fa2685afbf7edaa6330d2cf
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387589
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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There are 2 USB-A ports, but 5V power is controlled by the same signal
for both of them. This CL adds support for 5V control for these ports.
BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: I21328688ec653d91f9e37d2c441a3b5f816206f3
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387588
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: Iec06940c92fd430c7759c2e4ec25b7bc86344aa1
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387587
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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This CL adds board specific files/functions required to support the
battery LED. Similar to Coral or Octopus, the LEDs are controlled by
GPIO on/off instead of PWM.
BRANCH=none
BUG=b:122251649
TEST=make buildall. Verfied charging LED turns when external power is
connected.
Change-Id: Ic16d4192aaeba6e765e97743ded772d52ca47111
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387586
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Zack Yang <zack_yang@compal.corp-partner.google.com>
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This CL adds board specific files and functions required for both
battery/charging and Type C support.
BRANCH=none
BUG=b:122251649
TEST=make buildall, tested both port 0/1 operation at factory. Battery
can be charged via both ports.
Change-Id: Ia01eabe109e3df780ec053831a71a16a41047f01
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1387585
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL adds config options, board specific functions and GPIO signals
required to add power sequencing support.
BRANCH=none
BUG=b:122251649
TEST=make buildall, verified at factory that AP reaches S0
Change-Id: I5c7e8331b0f46a830b6e0f6722e7b05ba05212cb
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1377571
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL adds hatch in /board and /baseboard. Only some GPIO signals,
flash configuration, and I2C port map/pins required for NPCX to
successfully build have been included.
BRANCH=none
BUG=b:122251649
TEST=make buildall
Change-Id: Ief19223473f31b1f3a55e1466cc47d7cfeef8060
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1377569
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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