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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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MECC1.1 is defined for ADL+ platforms. To simplify the the BOM
stuffing options and also to remove dependency on H1 by MECC vendors,
H1 is added on RVP as AIC.
BUG=b:197659347
BRANCH=none
TEST=make buildall -j
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Change-Id: I5c3b4b2b2a116ec8dc5a7448c71a6b8654a78bba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114218
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Li Feng <li1.feng@intel.com>
Commit-Queue: Keith Short <keithshort@chromium.org>
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BRANCH=none
BUG=b:178648877
TEST=view in gitiles
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I0ac5581ba7bc512234d40dbf34222422afa9c725
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2650551
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Following features are enabled and verified.
1. Power sequencing
2. Host communication
3. USB TYPE-C - TCPC over PD AIC
4. H1 Close Case Debug
5. LED
6. Keyboard
BRANCH=None
BUG=b:169551130
TEST=Build, flash and boot the Alderlake RVP platform to OS
make BOARD=adlrvpp_ite -j;
sudo util/flash_ec --board=adlrvpp_ite --image=<path>
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
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Add new configuration for MECC-0.9 version and update JSL,TGL RVP boards
to use this config option. Support for new version of MECC-1.0 will
be required for ADL-RVP.
BRANCH=None
BUG=b:169551130
TEST=make buildall -j
Signed-off-by: pandeyan <anshuman.pandey@intel.com>
Change-Id: Ic1118c460a7052ffd0141a45c9153dbdac421d1b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435175
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: Poornima Tom <poornima.tom@intel.com>
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Intel-RVP supports Chrome EC via an Add In Card called as MECC
(Modular Embedded Controller Card). MECC has a standard spec
which defines pin routing and purpose of these pins. These MECC
pins are same across all the platforms hence we can have a baseboard
for Intel-RVPs and reuse the code for RVP board specific codes.
Chrome MECC spec is standardized for Icelake and successor RVPs hence
this baseboard code is applicable to Icelake and its successors only.
BUG=b:132061907
TEST=Using this baseboard implemented board code for ICLRVP, and
it can boot all the way to Chrome OS.
BRANCH=none
Change-Id: I4de891d4720e8cad83888caf9635f61f2ca11b8b
Signed-off-by: Daniel Gonzalez <daniel.d.gonzalez@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1594171
Commit-Ready: Jett Rink <jettrink@chromium.org>
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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