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* Intelrvp: Enable power configs.Deepti Deshatty2021-01-211-0/+9
| | | | | | | | | | | | | | | Don't allow the system to boot to S0 when the battery is low and unable to communicate on locked systems which haven't PD negotiated. BRANCH=none BUG=none TEST=ADLRVP-P booted to OS with only battery connected. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Change-Id: Ia9855fcd095dabb10051d9f70bfca9f600d68326 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2635876 Reviewed-by: caveh jalali <caveh@chromium.org>
* TCPMv2: Update source-out configsDiana Z2020-12-241-1/+1
| | | | | | | | | | | | | | | | | | | | Now that the DPM will be handling source-out decisions for TCPMv2, remove references to its old configuration options from TCPMv2 boards in order to avoid any confusion as to what code is running now. Also remove the charge manager notifications of sink attach/detach since the policy is being centralized into the DPM. Note that the previous configuration options only ever allocated one 3.0 A port, and so the default number of 3.0 A ports has been set to 1. BRANCH=None BUG=b:168862110,b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie452e3da32b04226503539daa67b6b9f4a58aa58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597431 Reviewed-by: Keith Short <keithshort@chromium.org>
* ADLRVP:Support for 100w typeC power adapterPoornima Tom2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | ADL SOC has a TDP of 45W and the RVP can support up to 200W power.Hence, increased the power support to 100W. BRANCH=None BUG=b:173081793 TEST=use chgsup command and list charger type negotiated values. Tested below on ADL: When Typec Charger connected to Port3: > chgsup port=3, type=0, cur=3000mA, vtg=20000mV, lsm=1 when TBT dock connected to Port1: > chgsup port=1, type=0, cur=4500mA, vtg=20000mV, lsm=1 when AC charger connected: > chgsup port=4, type=3, cur=5263mA, vtg=19000mV, lsm=0 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I0677519a68013dbc593539b692bad5016b52654f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531771 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp:Separate battery configuration into board specific filesAyushee Shah2020-11-251-8/+0
| | | | | | | | | | | | | | | | | | This CL adds the battery configuration from interlrvp baseboard to board specific file for Alderlake, Tigerlake and jasperlake platform so that same manufacturer battery but with different config params can be used on intended platforms. BUG=b:174129818 BRANCH=None TEST=Able to see correct battery configuration in "battery" EC command and can see the battery charging and discharging. Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: I639eb4466c49dbdc01d31feb4ace8844a6b1ac87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557763 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* usb: Remove references to usb23Caveh Jalali2020-11-061-1/+0
| | | | | | | | | | | | | | | | | The TCSS port mapping is not used by the EC and the higher layers no longer query the EC for this mapping. We can remove this feature and disable CONFIG_INTEL_VIRTUAL_MUX which was added to enable it. BRANCH=none BUG=b:153941950 TEST=buildall passes Change-Id: I2d7f51212f3e64d74827d7f82654eb93534b8db4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427632 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-051-1/+1
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* intelrvp: Keep PPC specific code generic in baseboardVijay Hiremath2020-10-311-0/+2
| | | | | | | | | | | | BUG=none BRANCH=none TEST=PPC interrupt is invoked on ADL-RVP Change-Id: Ib41be079d0d5731627193d15b66bb9949bd2722f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508156 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* adlprvp: add Alderlake RVP supportPoornima Tom2020-10-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. USB TYPE-C - TCPC over PD AIC 4. H1 Close Case Debug 5. LED 6. Keyboard BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpp_ite -j; sudo util/flash_ec --board=adlrvpp_ite --image=<path> Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: update usb_pd files to indicate MECC version complianceName2020-10-131-0/+3
| | | | | | | | | | | | | | | | | Add new configuration for MECC-0.9 version and update JSL,TGL RVP boards to use this config option. Support for new version of MECC-1.0 will be required for ADL-RVP. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: Ic1118c460a7052ffd0141a45c9153dbdac421d1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435175 Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: Poornima Tom <poornima.tom@intel.com>
* intelrvp: Enable temperature sensor only when SOC is on.Madhu M2020-10-131-0/+1
| | | | | | | | | | | | | | | | | | | | As thermistors are on A-rail need to enable temperature sensor only when SOC is on. BUG=none BRANCH=none TEST=Tested on TGLRVP-Y Temperature sensor reading is disabled when A-rail is off Ambient : Not powered DDR : Not powered Skin : Not powered VR : Not powered Signed-off-by: Madhu M <madhu.m@intel.corp-partner.google.com> Change-Id: If64cd5c3503b4e802c4dc9bebc0475d055e63bc5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2454986 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Move board specific changes to respective board filesName2020-10-071-4/+2
| | | | | | | | | | | | | | | | | Move board specific GPIO definitions and TCPC configuration from baseboard to JSL/TGL boards to accommodate changes in MECC spec 0.9 vs 1.0. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: I53a0545674f22e6cba05f777a4095909c231cfd2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435174 Commit-Queue: Poornima Tom <poornima.tom@intel.com> Tested-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Add battery "Getak SMP-HHP-408"Sooraj Govindan2020-10-071-0/+1
| | | | | | | | | | | | | | BRANCH=none BUG=b:169551130 TEST=make buildall -j Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: Ieabae7bb8e4d0645ad480dd16026e5d8414362b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435173 Commit-Queue: Poornima Tom <poornima.tom@intel.com> Tested-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Enable runtime control over PD debug levelMadhu M2020-09-021-1/+0
| | | | | | | | | | | | | | | | Enable runtime control of the PD debug level on intelrvp boards. This change reduces intelrvp flash space by 1404 bytes. BUG=none BRANCH=none TEST=make buildall TEST=Manually run pd dump 3 and ensure more pd protocol logs Signed-off-by: Madhu M <madhu.m@intel.corp-partner.google.com> Change-Id: I03dddaf9aca8d44236fc015643d14bc18c690380 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2387127 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp: Enable TCPMv2Ayushee2020-08-271-4/+12
| | | | | | | | | | | | | | | | This patch enables support for TCPMv2 for Intelrvp BUG=b:142340399 BRANCH=none TEST=TCPMv2/PD3.0 works properly on tglrvp. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: If15fc23efbcd9716c322ad06bc78a8e16f957d8e Signed-off-by: ravindr1 <ravindra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2299841 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Enable apreset host command needed for CSE LiteVijay Hiremath2020-08-191-0/+2
| | | | | | | | | | | | | | | | | This CL is derived from CL published on Volteer. Change-Id: Iff6fa572c5660b67152f9930b9bad9f82ff6c6ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2360454 BUG=none BRANCH=none TEST='etool apreset' resets the AP Change-Id: Ie2dd1fcd55dfdc42bd75a8c9b6846bce2f149b98 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2361103 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* tglrvp: Enable early firmware selection EFS2Vijay Hiremath2020-08-151-0/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=Software sync enabled Coreboot selects EC RW at early stage Change-Id: Ib10a15b8e0b006ea830fe1b07725bf4e8ce4591f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351624 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_pd: Rename CONFIG_CMD_PD_CONTROL to CONFIG_HOSTCMD_PD_CONTROLVijay Hiremath2020-05-151-0/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMV1/2: Make the PD Config Flags more consistentSam Hurst2020-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | The current use of the PD Config Flags are a bit confusing and has been changed to the following: The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY is enabled, one of the following must be enabled: CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine CONFIG_USB_PD_TCPMV2 - current power delivery state machine BUG=b:149993808 BRANCH=none TEST=make -j buildall Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519 Reviewed-by: Diana Z <dzigterman@chromium.org>
* volteer/intelrvp: Enable "pe" console commandVijay Hiremath2020-02-041-0/+1
| | | | | | | | | | | | BUG=none BRANCH=none TEST=Able to observe all the SVIDs presented by port partner Change-Id: I2fdb851b0683782555b6b10cbbd16446a914a40a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036590 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* intelrvp: Enable PD 3.0 supportVijay Hiremath2020-01-301-0/+4
| | | | | | | | | | | BUG=b:148528594 BRANCH=none TEST=tglrvp can negotiate with TBT3 docks Change-Id: I180ebb26ad8bb4fbbb0685c16b677ce4cc2608ba Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2027754 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-311-1/+3
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+2
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* tablet_mode: Renaming for GMR sensorPhilip Chen2019-09-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GMR sensors can be used to (1) detect clamshell/tablet mode (2) detect lid open/closed But hall sensors can only do (2). Therefore the naming related to "hall sensor" for tablet mode application is incorrect. This patch performs the following renaming to better reflect the reality: config: CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR -> CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR GPIO: HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L functions: hall_sensor_disable() -> gmr_tablet_switch_disable() hall_sensor_isr() -> gmr_tablet_switch_isr() hall_sensor_int() -> gmr_tablet_switch_init() variable: hall_sensor_at_360 -> gmr_sensor_at_360 BUG=b:139378190 BRANCH=none TEST=make buildall Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* intelrvp: Enable USB-C SRC current limitingVijay Hiremath2019-09-051-0/+3
| | | | | | | | | | | | | | | | | | | Enable SRC current limit pin of the type C current-limited power switch to provide more current when sourcing on only 1 port. BUG=b:140404596 BRANCH=none TEST=Manually tested on tglrvp a. 1 port is connected: ILIM pin of respective port's current limited power switch is high and able to source 3A. b. 2 ports are connected: ILIM pin of both port's current limited power switch is low and able to source 1.5A on each port. Change-Id: Ic6ce897e25a25b526c3c52bce8cbdc843ad419f9 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1783517 Reviewed-by: Keith Short <keithshort@chromium.org>
* tglrvpu_ite: Enable fan and temperature sensorVijay Hiremath2019-08-241-6/+0
| | | | | | | | | | | BUG=b:139882986 BRANCH=none TEST=Manually tested on tglrvp. Fan works as per thermal profile. Change-Id: I04b9b5b6319c484932ccdd0703b4cd56d203b9d9 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1768931 Reviewed-by: Keith Short <keithshort@chromium.org>
* tglrvpu_ite: Adding VCONN supportAyushee2019-08-231-0/+12
| | | | | | | | | | | | | | | Added GPIOs pin config to support VCONN on tglrvp. Also added power switch function to enable/disable VCONN according to the cc lines. BRANCH=None BUG=b:139763031 TEST=Able to get characteristics of an E-marked cable Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591 Reviewed-by: Keith Short <keithshort@chromium.org>
* baseboard/intelrvp: Avoid including "usb_pd_tcpm.h" from baseboard.hYu-Ping Wu2019-08-211-1/+0
| | | | | | | | | | | | | | | | | | | | | board/tglrvpu_ite/board.h includes baseboard.h, which includes usb_pd_tcpm.h, which includes ec_commands.h, which includes board.h again, leading to compilation failure in CL:1535086. This patch breaks the circular dependency by removing "usb_pd_tcpm.h" inclusion in baseboard.h. To make baseboard/intelrvp/retimer.c compilable, "compile_time_macros.h" is also included since it is where BUILD_ASSERT is defined. BRANCH=none BUG=b:109900671,b:118654976 TEST=make buildall -j Change-Id: Ifdf6594f4eb3a2f732bc5979c0fbb0c79ee15ddf Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1760656 Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tglrvp_ite: Add TGL-U/Y RVP base codeDaniel Gonzalez2019-08-151-10/+18
| | | | | | | | | | | | | | | | | | | | | | Added TGL-U/Y RVP base code using ITE EC. Following features are enabled. 1. TCPC + retimer 2. Charger 3. Battery 4. Power sequencing 5. Host communication 6. LED 7. Keyboard BUG=b:138597987 BRANCH=none TEST=Both TGLRVP U&Y can boot to ChromeOS Change-Id: Idf6be38796c26b31be6e13485a63ec13487bf954 Signed-off-by: Daniel Gonzalez <daniel.d.gonzalez@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1726943 Reviewed-by: Keith Short <keithshort@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-19/+1
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Intelrvp: Adding PECI ifdef in temp_sensor_id enumAyushee2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | When PECI is undefined, updating the memory map after initializing the sensors causes an illegal temp_sensor_read and raises an out of bound array index error. Hence, adding PECI ifdef to prevent accessing out of bound index. BUG=b:132061907 BRANCH=None TEST=Able to boot iclrvpy_ite all the way to chrome os Change-Id: I65dd0c3fd8419384e632d24ce137ebde2b9dc5ed Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1631932 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ayushee Shah <ayushee.shah@intel.corp-partner.google.com> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* Intelrvp: Add baseboard for Intel RVPsDaniel Gonzalez2019-05-211-0/+239
Intel-RVP supports Chrome EC via an Add In Card called as MECC (Modular Embedded Controller Card). MECC has a standard spec which defines pin routing and purpose of these pins. These MECC pins are same across all the platforms hence we can have a baseboard for Intel-RVPs and reuse the code for RVP board specific codes. Chrome MECC spec is standardized for Icelake and successor RVPs hence this baseboard code is applicable to Icelake and its successors only. BUG=b:132061907 TEST=Using this baseboard implemented board code for ICLRVP, and it can boot all the way to Chrome OS. BRANCH=none Change-Id: I4de891d4720e8cad83888caf9635f61f2ca11b8b Signed-off-by: Daniel Gonzalez <daniel.d.gonzalez@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1594171 Commit-Ready: Jett Rink <jettrink@chromium.org> Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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