| Commit message (Collapse) | Author | Age | Files | Lines |
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EFS2 boards need to call system_jumped_late in HOOK_INIT to avoid
running init code twice per boot.
system_jumped_to_this_image and system_jumped_late are functionally
equivalent for non EFS2 boards.
This patch will prevent system_jumped_to_this_image from being used
for EFS2 boards when code is copied from a past project.
BUG=chromium:1072743
BRANCH=none
TEST=buildall
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I73fb5cedc5325d1c80825f9346954013046ee1df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2267685
Reviewed-by: Keith Short <keithshort@chromium.org>
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BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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RVP uses MAX6818 to digitize the apreset physical button.
The EC SYS_RESET_L is connected to input of the digitizer.
From MAX6818 Data sheet, range of 'Debounce Duration' is
Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms.
Hence, implemented an override function to wait for an appropriate delay.
BUG=b:153128296
BRANCH=none
TEST=manually tested on TGLRVP, aprset EC console command triggers
warm boot
Change-Id: I4f883c925a82d32bfaaeed8120671869d3744843
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2134326
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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To prevent cc pins leakage and cc pins can be used as gpio.
We will check if the chip supported tcpc physical port count is
more than board active ITE port count. If yes, we will disable
unused cc port module.
BUG=none
BRANCH=none
TEST=1) on board it8xxx2_pdevb with chip it81202, check the pd
port connection with adapter and dongle when hibernate
and resume.
adapter: connect
dongle: disconnect then re-connect
2) on board it83xx_evb with chip it8320, set cc pins as
gpio, check output level when hibernate and resume.
Change-Id: I13511741b2e066dd87277db9f71f2b4a9323ad6d
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994693
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This makes retimers appear as generic muxes. By allowing a
chain of muxes they can be stacked up to the new configurations
that zork requires and will continue to work as they did before
on configurations that only have a single mux.
The code used to have two different arrays, 1) muxes and 2)
retimers. On one of the zork configurations the processor
MUX stopped being the primary mux and the retimer took its
place. In a different configuration of that same platform
it left the primary and secondary alone but the mux_set
FLIP operation had to be ignored. Since the same
interfaces needed to be available for both it stopped making
sense to have two different structures and two different
methods of handling them. This consolodates the two into
one.
The platforms that do not have retimers, this change will
not make any difference. For platforms like zork, it will
remove the retimers and make them chained muxes. So
testing on trembyle makes sense to verify,
BUG=b:147593660
BRANCH=none
TEST=verify USB still works on trembyle
Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794
Commit-Queue: Jett Rink <jettrink@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The current use of the PD Config Flags are a bit confusing and
has been changed to the following:
The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable
the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY
is enabled, one of the following must be enabled:
CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine
CONFIG_USB_PD_TCPMV2 - current power delivery state machine
BUG=b:149993808
BRANCH=none
TEST=make -j buildall
Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238
Signed-off-by: Sam Hurst <shurst@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Add PD driver for chip it8xxx1/8xxx2 series.
BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
(set cc toggle by console cmd):
1.pin configuration
console cmd "gpioget" check gpio settings.
memory dump check cc pin alternate settings.
2.Tx data error handle
Message discard, No GoodCRC, Tx not enable, Timeout
errors happen, corresponding INT will be triggered
then do properly handle.
3.basic pd connection
SNK:connect with adaptor, request max power (15V,3A),
state SNK_READY.
SRC:enable DRP role,
connect with dongle, provide power (5V,1.5A),
source Vconn 5v, get ack of cable discover id,
state SRC_READY.
4.pd module disable
SNK:connect with adapter.
console cmd "hibernate sec", driver disable pd module,
check still connection with adapter via dead battery rd.
And when resume from hibernate, pd init can re-enable
pd module, re-connect with adapter.
SRC:connect with dongle.
console cmd "hibernate sec", driver disable pd module,
check cc pin (not Vconn source pin) volt power down
to ~0v. And when resume from hibernate, pd init can
re-enable pd module, re-connect with dongle.
5.Tx hard reset
console cmd "pd port hard", check hard reset message by
lecroy analyzer.
6.Tx cable reset
check cable reset message by lecroy analyzer.
7.SOP' enable
SRC:connects to SNK via E-mark cable.
Source Vconn successfully, and receives cable's ack
of discover id request.
Not source Vconn to cable, and receives nothing
of discover id request (this isn't effect on
request SNK flow).
8.power role swap
console cmd "pd port swap power", check pd protocol
by lecroy.
Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>
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BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8eab72a146dd410af4f5e5c056f3393766284c5e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055884
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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The action_delay_sec field hasn't actually been referenced by
any code since 2013. Removing the corresponding struct field.
BUG=None
BRANCH=None
TEST=builds
Change-Id: Ia7334c26b85d0161ff61bb51fbdda61bb921595a
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054945
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BUG=none
BRANCH=none
TEST=Able to observe all the SVIDs presented by port partner
Change-Id: I2fdb851b0683782555b6b10cbbd16446a914a40a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036590
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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BUG=b:148528594
BRANCH=none
TEST=tglrvp can negotiate with TBT3 docks
Change-Id: I180ebb26ad8bb4fbbb0685c16b677ce4cc2608ba
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2027754
Reviewed-by: Keith Short <keithshort@chromium.org>
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combine the optional control variables into a union of
structures to reduce the amount of space needed for a
particular board type.
BUG=b:147593165
BRANCH=none
TEST=make buildall -j
Change-Id: If02c4c8065f4570aba210c3e34b30bc0d5c7a852
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001134
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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Following features are enabled and verified.
1. Power sequencing
2. Host communication
3. Battery
4. Charger
5. USB TYPE-C MUX, DP/HDMI, USB2/3
6. TPM-SOC communication
7. LED
8. Keyboard
BRANCH=none
BUG=b:146693933
TEST=Build, flash and boot the Jasperlake RVP platform to OS
make BOARD=jslrvp_ite; sudo util/flash_ec --board=jslrvp_ite
Change-Id: I80227833fcfca5636ac8f30abc099db5717bfa05
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980091
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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There is a board specific usb_pd_policy.c file that contains a lot of
code for handling DisplayPort Alternate mode, Google Firmware Update
Alternate mode, as well as some PD policy functions such as deciding to
Accept or Reject a data role swap or a power role swap. Several boards
simply copy/paste this code from project to project as a lot of this
functionality is not actually board specific.
This commit tries to refactor this by pulling the functions that are not
mainly board specific into common code. The functions are made
overridable such that boards that truly do require a different
implementation may do so.
Additionally, this consolidation changes the policy behaviour for some
boards, but they should be for the better. Some examples include that
data swaps are always allowed if we are a UFP (no system image
requirement), power swaps are allowed to become a sink if we are no
longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is
not entered if the AP is off.
In order to facilitate this refactor, a couple CONFIG_* options were
introduced:
- CONFIG_USB_PD_DP_HPD_GPIO
/* HPD is sent to the GPU from the EC via a GPIO */
- CONFIG_USB_PD_CUSTOM_VDO
/*
* Define this if a board needs custom SNK and/or SRC PDOs.
*
* The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating
* Dual-Role power, USB Communication Capable, and Dual-Role data.
*
* The default SNK PDOs are:
* - Fixed 5V/500mA with the same PDO_FIXED_FLAGS
* - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV,
* operational current PD_MAX_CURRENT_MA,
* - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power
* PD_OPERATING_POWER_MW
*/
BUG=chromium:1021724,b:141458448
BRANCH=<as many as we can that are still supported>
TEST=`make -j buildall`
TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety
of DP peripherals
TEST=Repeat above with a nocturne
TEST=Repeat above with an atlas
Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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BUG=b:145560203
BRANCH=none
TEST=BB retimer can communicate via I2C
Change-Id: Ibc9b61d909ff1d07794e13927796e26aa1e53e03
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1947427
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Changed the driver interface for BB virtual mux retimer to
stop using global functions and use the usb_retimers array
instead.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I56befaca1720eb2f4e0599a983629b4df45dc76b
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928121
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
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BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I7fe9ab23254dbd8515936d10ad6782305e76236c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925173
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Need to cleanup naming around USBC Retimers for adding
PI2DPX1207 code
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I7e18e0abbe5bfd89bf0e20fa7b5174669689778f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911296
Reviewed-by: Edward Hill <ecgh@chromium.org>
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It was pointed out to me that the fans config list was non-const, but
there is only 2 boards that require non-const configuration, so
by default make it const, but allow an override.
BRANCH=none
BUG=None
TEST=EC compiles, make tests, buildall
Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Tested-by: Andrew McRae <amcrae@chromium.org>
Commit-Queue: Andrew McRae <amcrae@chromium.org>
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Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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this changes the declaration and definitions of
typec_set_source_current_limit() to take an enum tcpc_rp_value instead
of int.
BRANCH=none
BUG=none
TEST=buildall passes
Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into
separate options controlling SLP_S3 and SLP_S4. Allow volteer to
configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a
build error if virtual wires are configured, but eSPI is not.
BUG=b:139553375,b:143288478
TEST=make buildall
TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but
CONFIG_HOSTCMD_ESPI undefined; observe build error
BRANCH=none
Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758
Reviewed-by: Keith Short <keithshort@chromium.org>
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GMR sensors can be used to
(1) detect clamshell/tablet mode
(2) detect lid open/closed
But hall sensors can only do (2).
Therefore the naming related to "hall sensor" for tablet mode
application is incorrect.
This patch performs the following renaming to better reflect the reality:
config:
CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE
CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM
CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR ->
CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
GPIO:
HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L
functions:
hall_sensor_disable() -> gmr_tablet_switch_disable()
hall_sensor_isr() -> gmr_tablet_switch_isr()
hall_sensor_int() -> gmr_tablet_switch_init()
variable:
hall_sensor_at_360 -> gmr_sensor_at_360
BUG=b:139378190
BRANCH=none
TEST=make buildall
Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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Enabling the FAN at 15 deg C as Intel SOC is not soldered down on the
RVP and the FAN is mounted slightly above the SOC hence it might get
heated immediately and assert PROCHOT when random high performance
tests are triggered at room temperature.
BUG=b:139882986
BRANCH=none
TEST=FAN is on at room temperature
Change-Id: Ia94623d74cbafced7e3224ec530c676ca0937cbb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799285
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also
defined. Remove references to CONFIG_CHARGER_V2 from board header files.
Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when
appropriate.
BUG=b:139699769
BRANCH=none
TEST=make buildall -j
Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Enable SRC current limit pin of the type C current-limited power switch
to provide more current when sourcing on only 1 port.
BUG=b:140404596
BRANCH=none
TEST=Manually tested on tglrvp
a. 1 port is connected: ILIM pin of respective port's current
limited power switch is high and able to source 3A.
b. 2 ports are connected: ILIM pin of both port's current
limited power switch is low and able to source 1.5A on each
port.
Change-Id: Ic6ce897e25a25b526c3c52bce8cbdc843ad419f9
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1783517
Reviewed-by: Keith Short <keithshort@chromium.org>
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BUG=b:139882986
BRANCH=none
TEST=Manually tested on tglrvp. Fan works as per thermal profile.
Change-Id: I04b9b5b6319c484932ccdd0703b4cd56d203b9d9
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1768931
Reviewed-by: Keith Short <keithshort@chromium.org>
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Added GPIOs pin config to support VCONN on tglrvp. Also added
power switch function to enable/disable VCONN according to the
cc lines.
BRANCH=None
BUG=b:139763031
TEST=Able to get characteristics of an E-marked cable
Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591
Reviewed-by: Keith Short <keithshort@chromium.org>
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board/tglrvpu_ite/board.h includes baseboard.h, which includes
usb_pd_tcpm.h, which includes ec_commands.h, which includes board.h
again, leading to compilation failure in CL:1535086.
This patch breaks the circular dependency by removing "usb_pd_tcpm.h"
inclusion in baseboard.h. To make baseboard/intelrvp/retimer.c
compilable, "compile_time_macros.h" is also included since it is where
BUILD_ASSERT is defined.
BRANCH=none
BUG=b:109900671,b:118654976
TEST=make buildall -j
Change-Id: Ifdf6594f4eb3a2f732bc5979c0fbb0c79ee15ddf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1760656
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Added TGL-U/Y RVP base code using ITE EC.
Following features are enabled.
1. TCPC + retimer
2. Charger
3. Battery
4. Power sequencing
5. Host communication
6. LED
7. Keyboard
BUG=b:138597987
BRANCH=none
TEST=Both TGLRVP U&Y can boot to ChromeOS
Change-Id: Idf6be38796c26b31be6e13485a63ec13487bf954
Signed-off-by: Daniel Gonzalez <daniel.d.gonzalez@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1726943
Reviewed-by: Keith Short <keithshort@chromium.org>
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Before entering into alternate mode, state of the USB-C MUX needs to be
in safe mode so that the USB-C pins cab be re-purposed without getting
damaged or do not damage their Port Partner. Hence, sending the DP
safe mode info to virtual MUX from EC.
BUG=b:139140865
BRANCH=none
TEST=Manually tested on Intel RVP, MUX is able to configure to safe mode
before entering alternate mode.
Change-Id: I3715b5118112b7744407ac5e652f63f6d7cd0a1b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1745540
Reviewed-by: Keith Short <keithshort@chromium.org>
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Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an
embedded TCPC.
This patch adds bus_type field to struct tcpc_config_t so that a TCPC
location on other type of bus can be specified.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b
Reviewed-on: https://chromium-review.googlesource.com/1640305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Added get_dp_pin_mode function to get the current state of the
DP pin to configure the virtual mux on Intel SOC.
BUG=None
BRANCH=None
TEST=Verified the correct DP mode status on iclrvpy_ite
Change-Id: I52cdb7bfbb87074d48d61a0a1cd21d0afcb9c59a
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646534
Tested-by: Ayushee Shah <ayushee.shah@intel.corp-partner.google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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When PECI is undefined, updating the memory map after initializing
the sensors causes an illegal temp_sensor_read and raises an out of
bound array index error. Hence, adding PECI ifdef to prevent accessing
out of bound index.
BUG=b:132061907
BRANCH=None
TEST=Able to boot iclrvpy_ite all the way to chrome os
Change-Id: I65dd0c3fd8419384e632d24ce137ebde2b9dc5ed
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1631932
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Ayushee Shah <ayushee.shah@intel.corp-partner.google.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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Intel-RVP supports Chrome EC via an Add In Card called as MECC
(Modular Embedded Controller Card). MECC has a standard spec
which defines pin routing and purpose of these pins. These MECC
pins are same across all the platforms hence we can have a baseboard
for Intel-RVPs and reuse the code for RVP board specific codes.
Chrome MECC spec is standardized for Icelake and successor RVPs hence
this baseboard code is applicable to Icelake and its successors only.
BUG=b:132061907
TEST=Using this baseboard implemented board code for ICLRVP, and
it can boot all the way to Chrome OS.
BRANCH=none
Change-Id: I4de891d4720e8cad83888caf9635f61f2ca11b8b
Signed-off-by: Daniel Gonzalez <daniel.d.gonzalez@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1594171
Commit-Ready: Jett Rink <jettrink@chromium.org>
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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