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* adlrvp: Add custom board ID reading functionVijay Hiremath2021-07-143-1/+7
| | | | | | | | | | | | | | | ADLRVP has a I/O expander + EEPROM based board ID reading implementation hence added overridable custom board ID reading function. BUG=none BRANCH=none TEST='ectool version' gives intended result Change-Id: I98e49de710f54683b8fbe9f6e9615b7de0aeb4ed Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3024669 Reviewed-by: AndreX Andraos <andrex.andraos@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* system: Clean up system_get_board_version()Philip Chen2021-07-091-1/+0
| | | | | | | | | | | | | | | | | | | Refactor system_get_board_version() a bit so that we can remove CONFIG_BOARD_VERSION_CUSTOM and CONFIG_BOARD_VERSION from config.h. BRANCH=None BUG=b:186264627 TEST=make buildall -j TEST=zmake testall Cq-Depend: chromium:3015243 Change-Id: Id5ab809493c297b7d330ea13dcd6934ec00042a6 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004112 Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* adlrvp: Fix the change in cbi config nameThejaswani Putta2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | Rename CONFIG_CROS_BOARD_INFO to CONFIG_CBI_EEPROM in adlrvp to allign with other boards and get cbi utility working. BRANCH=none BUG=none TEST=build ec image and flash on adlrvp, cbi set/get works fine. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Change-Id: I787bb5e874daa930787c2010a551c8f9e494de96 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999432 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* mchp: Add MEC1727 MECC board: adlrvpp_mchp1727martin yan2021-06-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Add new board, adlrvpp_mchp1727 using MEC1727-SZ with integrated 512KB SPI flash and based upon the intelrvp baseboard. BRANCH=none BUG=b:190638460 TEST=Build MEC1727SZ MECC and ADL-P board. Tested basic functions: 1: Power on sequence: G3->S5->S3->S0 2: ESPI enumeration / VW / FC 3: Temperature measurements 4: Smart battery information acquisition 5: Type C Port 0 and 1 - enter ALT mode 6: UART console 7: Sleep / wake / hibernate - woken by powerbtn 8: Powerbtn override Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ib474e1134a47a6fa219d741fc5c094cf2f4a560c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891908 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chgstv2: Unify power-on and shutdown battery thresholdsDaisuke Nojiri2021-06-231-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, power-on battery SoC and shutdown battery SoC are independently configured by each board. This patch will unify the setting as follows: CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%) CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%) BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%) CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed) CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1 This allows us to show the low battery alert whenever we can because EC doesn't inhibit power-on even if it knows the host would immediately shut down. With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery threshold (and the SoC will be agreed between the EC and Powerd). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the same threshold. This is for avoiding degrading the UX by increasing the power-on threshold (even though a question that 1% may not be enough for soft sync to finish consistently remains to be answered). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a lower threshold but we think 2% is enough to finish the software sync. A lower threshold also improves the UX by showing the low battery alert in the situation where otherwise the system would leave the user uninformed by not responding to a power button press. BUG=b:191837893 BRANCH=None TEST=buildall Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* adlrvp: Cache BB retimer's power stateVijay Hiremath2021-06-191-0/+14
| | | | | | | | | | | | | | | | | | | Ports with cascaded retimers share common load switch and reset pin hence no need to set the power state of retimer again if the 1st retimer's power status has already changed. Otherwise, it will add additional delay to enable the 2nd retimer. Thus, added code to cache the power state of the retimer per port instead of individual retimer. BUG=none BRANCH=none TEST=Tested on ADL-P-DDR5 board that has cascaded retimer topology, no delay added when enabling SOC side retimer. Change-Id: I4b67b6aca96bf20776424b3e56f382b021d4084d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954730 Reviewed-by: caveh jalali <caveh@chromium.org>
* bb_retimer: cleanup: Change the power handler func name & paramsVijay Hiremath2021-06-181-2/+2
| | | | | | | | | | | | | | Changed the power handler function name from bb_retimer_power_handle() to bb_retimer_power_enable() and on_off param to enable. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ifad4c71a5d76b4841ea369a991160e221c051ec5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973375 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* adlrvp: enable retimer firmware updateli feng2021-06-151-0/+1
| | | | | | | | | | | | BUG=b:189974129 BRANCH=none TEST=make BOARD=adlrvpp_ite pass Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I06e85f651b6aada465b990215d2cde7c3ecc282c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954731 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* bb_retimer: Return status from bb_retimer_power_handle()Caveh Jalali2021-06-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | This allows the implementation of bb_retimer_power_handle() to return a status value indicating whether the request was successful. The default implementation simply controls a GPIO and is expected to succeed unconditionally. More complex implementations may run into failure cases that leave the BB unreachable. When this happens, device initialization returns an error so the caller can take mitigating action. USB MUX operations tend to be called from timing sensitive code paths in the TCPM, so careful error handling helps avoid cascading problems like PD negotiation failures. BRANCH=none BUG=b:181743576,b:188826559 TEST=buildall passes, PD still works on brya Change-Id: If79078be26e47d758e2cd6cc385ff2b34fecff63 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954198 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* adlrvp: Enable CBI utilityAnil Kumar2021-06-091-0/+7
| | | | | | | | | | | | Branch=none Bug=b:190523663 Test=build ec image and test on adlrvp. cbi set/get works OK Change-Id: I51cae596a389a3859dccbb893495bb9b25172098 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947901 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Add dual retimer configurationPoornima Tom2021-05-272-0/+42
| | | | | | | | | | | | | | | | DDR5 based sku has dual retimer based topology for port0 & port1. Identify DDR5 board & reconfigure usbmux at run time to support dual retimer topology. BUG=b:189190982 BRANCH=none TEST=Able to configure the retimers and TBT is detected. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I0ff859f7770a6c55931d413b2ea366d4f6aafe84 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712214 Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvpp_mchp1521: Add code for ADL-P-DDR4 RVP using Microchip ECPoornima Tom2021-05-201-1/+1
| | | | | | | | | | | | | | | | | | | ADL-P-DDR4 RVP has on board Microchip EC-MEC1521. This code enables RVP powering ON using this on board EC, instead of Mica EC. As this onboard EC doesn't have internal flash memory, EC binary of 512KB size generated is flashed to external SPI Flash1(32MB size) available on RVP over SPI using servo.This image from flash1 is then bootloaded by MEC1521, when powered ON. BUG=b:186669325 BRANCH=none TEST=ADL-P-DDR4 board with Microchip 1521 EC booted to S0. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I39f937f60e2f79b0d2de195621084e3276e36bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2755363 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* Specify type for forward-declared enumsTom Hughes2021-05-061-1/+2
| | | | | | | | | | | | | C++ does not allow enums to be forward declared unless they have a type. BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I6fcdedc81f2b60a44b750554939e60552a4c6a77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740567 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* adlrvp: Add TBT & USB4 overridable functionVijay Hiremath2021-04-292-2/+32
| | | | | | | | | | | | | | | | Type-C ports are not symmetrical on RVP to test various combinations. ADL-P-LP5 RVP doesn't have a platform level AUX & LSx MUX on port-2 hence do not perform USB4 & TBT operations on port-2. BUG=none BRANCH=none TEST=Connected TBT3 device on Port-2 of ADLRVP_P_LP5 board, only DP+USB is selected as expected. Change-Id: I52bbd4b8518d040cad637559cad0fd3533fcd5ea Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2791780 Reviewed-by: caveh jalali <caveh@chromium.org>
* ADLRVP: Make code robust for validating TCPC vendorsVijay Hiremath2021-04-264-5/+26
| | | | | | | | | | | | | | | | | Intel Reference Validation Platform is designed to test multiple combinations of hardware thus help enable vendors seamlessly. Added task based TCPC code enablement so that TCPC vendors can easily hook their hardware, make the code changes and validate their TCPC. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I989b6a35c6ff3f96150d09de11458886f9642d1f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823167 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Use PCA9675 I/O expander driver structureVijay Hiremath2021-04-233-80/+98
| | | | | | | | | | | | | Updated the code use PCA9675 I/O expander's standard driver structure. BUG=b:169814014 BRANCH=none TEST=ADLRVP can configure retimer & CCD works Change-Id: I61eef08214a64382338321f4a2dae9f7cfd980da Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2845014 Reviewed-by: caveh jalali <caveh@chromium.org>
* thermisor: move header to include dirDawid Niedzwiecki2021-04-221-1/+1
| | | | | | | | | | | | | | | | Move the "thermistor.h" header to the include/driver/temp_sensor directory. It is used by the Zephyr shim, so the change is useful to include the header. BUG=b:180403276 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I0e83df97e50a3b324440b65ddb900ddf135f2439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2843323 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* adlrvp: initialise over current indicationSooraj Govindan2021-04-061-1/+3
| | | | | | | | | | | BUG=none BRANCH=none TEST=ADL-P-RVP boots to OS Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I398c6d642c0cfac48e647878e9b06f164b17db60 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2804000 Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvpm: add battery configSooraj Govindan2021-03-233-1/+53
| | | | | | | | | | | | BRANCH=none BUG=none TEST=Board booted to OS with battery connected. Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I3f6eca92023aa16a1449b805cdf28964f12bc3c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2755361 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* ADLRVP-NPCX: Enable code for ADL-RVP using NPCX MECCVijay Hiremath2021-03-192-1/+4
| | | | | | | | | | | | | | | | | | | | Using the NPCX MECC following features are tested on ADL-P RVP. 1. Boot to OS 2. Type-C devices 3. Servo functionalities 4. FAN control 5. Battery & Charging 6. Temperature sensors BUG=b:181967246 BRANCH=none TEST=ADL-P-RVP boots to OS Change-Id: I0f5c30067e579c40f532b0df7cabf22e6481f71e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2632805 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: Add support for NPCX EC configsVijay Hiremath2021-03-194-2/+121
| | | | | | | | | | | | | | | Added base code to support NPCX EC on Intel RVP. Respective board files can reference these configs for easier integration. BUG=b:181967246 BRANCH=none TEST=make buildall -j Change-Id: I4bf7570093c267ca4edb45d115585982f62d4623 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2770179 Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: cleanup: Shuffle the codeVijay Hiremath2021-03-196-74/+107
| | | | | | | | | | | | | | | | | | | Shuffled the code to cleanup following 1. Moved the temperature sensor code from CONFIG_FANS to CONFIG_TEMP_SENSOR to avoid build errors when the FAN is disabled. 2. Moved ADC code to respective EC chip code as the ADC structure is not same for all the EC chip variants. 3. Moved PD reset code from EC chip to MECC files so that PD specific code can be added if needed. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I614ce0c011f5080e46cd1095a534884925c13b2c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2762806 Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Select retimer USB MUX config at runtimePoornima Tom2021-03-022-1/+30
| | | | | | | | | | | | | | | | Different SKU of ADL RVP have different retimer USB MUX hence select the retimer USB MUX based on the board SKU at runtime. BUG=none BRANCH=none TEST=Able to detect USB3.0 drive on Port-2 without retimer Change-Id: I34d70749db98ff45ca3c3ed09720ba9ad9df62a4 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2718534 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: cleanup: Move common files to baseboardVijay Hiremath2021-02-224-0/+523
| | | | | | | | | | | | | | | | | Moved the ADLRVP specific common files to baseboard so that the RVP variants with multiple MECC clients can leverage these files without copying them over to board files. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I19739a189aa29c198422f1e2013d59f5da97b02f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706259 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mchp: Add MEC152x SKL RVP boardScott Worley2021-02-104-1/+88
| | | | | | | | | | | | | | | | | | | | Add a MEC152x board based upon SKL-RVP using the intelrvp baseboard. We use the fusb307 USB PD as a placeholder for an actual USB PD. Added MCHP EC module to the intel RVP baseboard. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I4ea2e8ca27efa5b0624e751a06fcec8a1bf65456 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673020 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* docs: Run mdformat on all .md filesTom Hughes2021-01-281-29/+26
| | | | | | | | | | | BRANCH=none BUG=b:178648877 TEST=view in gitiles Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0ac5581ba7bc512234d40dbf34222422afa9c725 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2650551 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: Fix inconsistent VBUS measurement configAbe Levkoy2021-01-221-1/+0
| | | | | | | | | | | | | | | | | | Remove CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT from boards that define CONFIG_USB_PD_VBUS_MEASURE_CHARGER. This change is a no-op, because charge_manager.c is the only place where CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT is checked, and it is only checked if CONFIG_USB_PD_VBUS_MEASURE_CHARGER is not defined. BUG=b:178102402 TEST=make buildall TEST=Build sizes before and after change are the same BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ia3caa57a8531a5cba549b64c9087c337996af9c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2642892 Reviewed-by: Diana Z <dzigterman@chromium.org>
* config: Provide default VCONN Swap delayAbe Levkoy2021-01-221-1/+0
| | | | | | | | | | | | | | | | | Almost every relevant board copy-pastes 5000 us. Make that the default and get rid of the redundant definitions. This is the approximate result of this command: find . -type f -name *.h | xargs sed -i -E \ '/#define CONFIG_USBC_VCONN_SWAP_DELAY_US[[:space:]]+5000[[:space:]]/d' BUG=b:144165680 TEST=make buildall BRANCH=none Change-Id: Ife86f9752971abcd7ab5ad5a5e607eb2ccbde2ba Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* config: Make VCONN Swap delay a documented optionAbe Levkoy2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This is the approximate result of the following command, run from platform/ec: find . -type f -\( -name '*.c' -o -name '*.h' -\) | \ xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g' Fix some latent formatting errors in usb_pd_protocol.c, because they were preventing pre-upload hooks from passing. BUG=b:144165680 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Intelrvp: Enable power configs.Deepti Deshatty2021-01-211-0/+9
| | | | | | | | | | | | | | | Don't allow the system to boot to S0 when the battery is low and unable to communicate on locked systems which haven't PD negotiated. BRANCH=none BUG=none TEST=ADLRVP-P booted to OS with only battery connected. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Change-Id: Ia9855fcd095dabb10051d9f70bfca9f600d68326 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2635876 Reviewed-by: caveh jalali <caveh@chromium.org>
* Move tcpic.h header into include/driverSimon Glass2021-01-073-3/+3
| | | | | | | | | | | | | | | | | | This header cannot currently be accessed by Zephyr since it is in a driver directory, not an include directory. This header has quite a bit of public stuff in it, so it seems reasonable to consider everything public. Move the header file and update all users. BUG=b:175434113 BRANCH=none TEST=make buildall -j30 build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ibba37f47a06783fafb5095f853f2a68d92b6df87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607745
* TCPMv2: Update source-out configsDiana Z2020-12-244-12/+6
| | | | | | | | | | | | | | | | | | | | Now that the DPM will be handling source-out decisions for TCPMv2, remove references to its old configuration options from TCPMv2 boards in order to avoid any confusion as to what code is running now. Also remove the charge manager notifications of sink attach/detach since the policy is being centralized into the DPM. Note that the previous configuration options only ever allocated one 3.0 A port, and so the default number of 3.0 A ports has been set to 1. BRANCH=None BUG=b:168862110,b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie452e3da32b04226503539daa67b6b9f4a58aa58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597431 Reviewed-by: Keith Short <keithshort@chromium.org>
* ADLRVP:Support for 100w typeC power adapterPoornima Tom2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | ADL SOC has a TDP of 45W and the RVP can support up to 200W power.Hence, increased the power support to 100W. BRANCH=None BUG=b:173081793 TEST=use chgsup command and list charger type negotiated values. Tested below on ADL: When Typec Charger connected to Port3: > chgsup port=3, type=0, cur=3000mA, vtg=20000mV, lsm=1 when TBT dock connected to Port1: > chgsup port=1, type=0, cur=4500mA, vtg=20000mV, lsm=1 when AC charger connected: > chgsup port=4, type=3, cur=5263mA, vtg=19000mV, lsm=0 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I0677519a68013dbc593539b692bad5016b52654f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531771 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp:Separate battery configuration into board specific filesAyushee Shah2020-11-253-119/+0
| | | | | | | | | | | | | | | | | | This CL adds the battery configuration from interlrvp baseboard to board specific file for Alderlake, Tigerlake and jasperlake platform so that same manufacturer battery but with different config params can be used on intended platforms. BUG=b:174129818 BRANCH=None TEST=Able to see correct battery configuration in "battery" EC command and can see the battery charging and discharging. Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: I639eb4466c49dbdc01d31feb4ace8844a6b1ac87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557763 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp:Supports boards without DC jackAyushee2020-11-073-1/+21
| | | | | | | | | | | | | | | This commit checks if the dedicated port count is greater than 0 for the charger specific files while keeping the code common for both DC jack supported and non DC jack supported boards. BUG=b:172642304 BRANCH=None TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I138d33802c2df586963e244f18b787ccce60b8f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2523294 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb: Remove references to usb23Caveh Jalali2020-11-061-1/+0
| | | | | | | | | | | | | | | | | The TCSS port mapping is not used by the EC and the higher layers no longer query the EC for this mapping. We can remove this feature and disable CONFIG_INTEL_VIRTUAL_MUX which was added to enable it. BRANCH=none BUG=b:153941950 TEST=buildall passes Change-Id: I2d7f51212f3e64d74827d7f82654eb93534b8db4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427632 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-051-1/+1
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ADLP-RVP: Config to enable TBTPoornima Tom2020-11-031-0/+2
| | | | | | | | | | | | BRANCH=None BUG=b:171409539 TEST=Able to enter TBT mode Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I81fb01ac9e537ded25cfffc8a9691c173ed41a49 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2490900 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: Keep PPC specific code generic in baseboardVijay Hiremath2020-10-312-1/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=PPC interrupt is invoked on ADL-RVP Change-Id: Ib41be079d0d5731627193d15b66bb9949bd2722f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508156 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* adlprvp: add Alderlake RVP supportPoornima Tom2020-10-285-0/+198
| | | | | | | | | | | | | | | | | | | | | | | Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. USB TYPE-C - TCPC over PD AIC 4. H1 Close Case Debug 5. LED 6. Keyboard BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpp_ite -j; sudo util/flash_ec --board=adlrvpp_ite --image=<path> Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: update usb_pd files to indicate MECC version complianceName2020-10-137-108/+130
| | | | | | | | | | | | | | | | | Add new configuration for MECC-0.9 version and update JSL,TGL RVP boards to use this config option. Support for new version of MECC-1.0 will be required for ADL-RVP. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: Ic1118c460a7052ffd0141a45c9153dbdac421d1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435175 Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: Poornima Tom <poornima.tom@intel.com>
* intelrvp: Enable temperature sensor only when SOC is on.Madhu M2020-10-131-0/+1
| | | | | | | | | | | | | | | | | | | | As thermistors are on A-rail need to enable temperature sensor only when SOC is on. BUG=none BRANCH=none TEST=Tested on TGLRVP-Y Temperature sensor reading is disabled when A-rail is off Ambient : Not powered DDR : Not powered Skin : Not powered VR : Not powered Signed-off-by: Madhu M <madhu.m@intel.corp-partner.google.com> Change-Id: If64cd5c3503b4e802c4dc9bebc0475d055e63bc5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2454986 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* it83xx: enable selecting EC's VCCDino Li2020-10-081-0/+1
| | | | | | | | | | | | | | | | | | | The VCC is the power source of EC's GPM0~6, will connect to 1.8v or 3.3v depended on platform design. This change was made to ensure voltage level setting of GPM0~6 matches the corresponded VCC level. So we can enable internal pull-up no matter VCC is connected to 1.8v or 3.3v BUG=b:168783892 BRANCH=none TEST=- buildall. - The level setting is correct on these boards: asurada, drawcia, and reef_it8320 Change-Id: I4eae368e569987381a0437494262d588436bb011 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2397931 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* intelrvp: Move board specific changes to respective board filesName2020-10-078-151/+3
| | | | | | | | | | | | | | | | | Move board specific GPIO definitions and TCPC configuration from baseboard to JSL/TGL boards to accommodate changes in MECC spec 0.9 vs 1.0. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: I53a0545674f22e6cba05f777a4095909c231cfd2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435174 Commit-Queue: Poornima Tom <poornima.tom@intel.com> Tested-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Add battery "Getak SMP-HHP-408"Sooraj Govindan2020-10-072-0/+32
| | | | | | | | | | | | | | BRANCH=none BUG=b:169551130 TEST=make buildall -j Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: Ieabae7bb8e4d0645ad480dd16026e5d8414362b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435173 Commit-Queue: Poornima Tom <poornima.tom@intel.com> Tested-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Enable runtime control over PD debug levelMadhu M2020-09-021-1/+0
| | | | | | | | | | | | | | | | Enable runtime control of the PD debug level on intelrvp boards. This change reduces intelrvp flash space by 1404 bytes. BUG=none BRANCH=none TEST=make buildall TEST=Manually run pd dump 3 and ensure more pd protocol logs Signed-off-by: Madhu M <madhu.m@intel.corp-partner.google.com> Change-Id: I03dddaf9aca8d44236fc015643d14bc18c690380 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2387127 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp: Enable TCPMv2Ayushee2020-08-275-42/+24
| | | | | | | | | | | | | | | | This patch enables support for TCPMv2 for Intelrvp BUG=b:142340399 BRANCH=none TEST=TCPMv2/PD3.0 works properly on tglrvp. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: If15fc23efbcd9716c322ad06bc78a8e16f957d8e Signed-off-by: ravindr1 <ravindra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2299841 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* bb retimer: Use mutex to lock the access to shared NVMVijay Hiremath2020-08-251-2/+0
| | | | | | | | | | | | | | | | | | | If the BB retimer has a shared NVM we need 40ms delay after releasing the RESET line to synchronize, load and initialize both the retimers. On a non-shared NVM we need 20ms delay to load and initialize. In order to synchronize, instead of 40ms delay this CL uses a MUTEX to lock the access of another retimer by not releasing the RESET line until the first retimer completes initialization. BUG=b:165895649 BRANCH=none TEST=Tested on volteer(non shared NVM), tglrvpu_ite (shared NVM) Retimer is able to initialize (DP, USB, TBT, USB4 are detected) Change-Id: I709377c2e6401faa26871289143d71665ee516d1 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2368223 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Remove FORCE_PWR GPIO from EC driverVijay Hiremath2020-08-191-2/+0
| | | | | | | | | | | | | | | | | | FORCE_PWR GPIO is used for keeping the BB retimer in active state during f/w updating. On TGLRVP, control to enable the FORCE_PWR GPIO was given to EC to support the I2C based F/W updating. I2C based f/w updating is deprecated and the LSx interface is POR hence the FORCE_PWR GPIO control is given to AP now. Thus, removing the FORCE_PWR GPIO from EC driver. BUG=b:165214747 BRANCH=none TEST=make buildall -j Change-Id: If9bb7199a68c93f704f698552e5594a58bd68f7c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363334 Reviewed-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: Enable apreset host command needed for CSE LiteVijay Hiremath2020-08-191-0/+2
| | | | | | | | | | | | | | | | | This CL is derived from CL published on Volteer. Change-Id: Iff6fa572c5660b67152f9930b9bad9f82ff6c6ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2360454 BUG=none BRANCH=none TEST='etool apreset' resets the AP Change-Id: Ie2dd1fcd55dfdc42bd75a8c9b6846bce2f149b98 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2361103 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Commit-Queue: Keith Short <keithshort@chromium.org>
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