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* Drop some obsolete boardsJack Rosenthal2021-08-055-728/+0
| | | | | | | | | | | | | | | | | | | | | samus: AUE in M91, M92 pushed to stable already samus_pd: samus pd chip dragonegg: canceled cheza: canceled flapjack_scp: flapjack was canceled atlas_ish: atlas shipped, but ish project canceled sklrvp,glkrvp: these are pretty old intel reference boards and the portage overlays were already deleted ... assume nobody needs the EC firmware anymore either BUG=none BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I794867ac82f37ffa2267e2e59ac02bc381688c57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069716 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* lid_angle: Create a common callback for lid angle changesWai-Hong Tam2021-08-057-74/+5
| | | | | | | | | | | | | | | | | | | | | | Each board defines its own callback lid_angle_peripheral_enable(). The implementation is very similar. Create a common implementation and reduce the duplicated code. This CL removes the board callbacks which are identifical to the common callback. If it is slightly different, keep it and add the __override tag. The check of TEST_BUILD is unnecessary as the board callback is not linked in the test build. BRANCH=None BUG=b:194922043 TEST=Build all the images. Change-Id: I73d381730f35b80eff69399cdfc5fb54f839aee0 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069175 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mtscp-rv32i: align mt8192 and mt8195 ipi handler interfaceYunfei Dong2021-08-043-3/+3
| | | | | | | | | | | | | | | | | For mt8192 and mt8195 can use the same vdec.c/venc.c, change build config to support different platforms. BRANCH=none BUG=b:184793035 TEST=make BOARD=cherry_scp Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.org> Change-Id: Id096d4ddd80caf4dcf39b7a8a747baf386b1b9c1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2913490 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* mtscp-rv32i: enable privilege mode for decoderYunfei Dong2021-08-041-0/+4
| | | | | | | | | | | | | | | | | Decoder hardware need to use privilege mode to read/write register. BRANCH=none BUG=b:184793035 TEST=make BOARD=cherry_scp Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.org> Change-Id: Ifaa1fd5a05f6a19aa7a520461122b75c73a60c9f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2913481 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* COIL: Change host interface option to CONFIG_HOSTCMD_SHIKeith Short2021-08-032-2/+2
| | | | | | | | | | | | | | Update SPI host interface config option for inclusive language. BUG=b:163885307 BRANCH=none TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* flash: Set CBI EEPROM WP immediately if SW WP setAseda Aboagye2021-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | With `CONFIG_EEPROM_CBI_WP`, the EC will set the the CBI EEPROM WP according to `system_is_locked`. The system lock status is also cached. In order to prevent requiring an EC reboot after setting the software write protect status, this commit will set the CBI EEPROM WP status when the SW WP is asserted along with the HW WP. This is the same criteria that `system_is_locked` would use when deciding if the system is locked. BUG=b:181769483 BRANCH=None TEST=Build and flash a reworked lalala, enable HW WP, enable SW WP via `flashrom -p ec --wp-enable` and verify that EC_CBI_WP is asserted immediately without requiring an EC reboot. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I987a5b7652134be11c82855aab9ed4eb1442b57c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058077 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Ezkinil: Add PS8818 for TYPEC C1 secondary MUXSue Chen2021-07-302-0/+21
| | | | | | | | | | | | | | | Use SSFC bits 6-7 to choose which secondary MUX is used. BUG=b:192523667 BRANCH=zork TEST=After setting SSFC to 0x80 on the DUT with PS8818, the typec on DB works fine. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I8a66098d1e9b947acfb26b78f0cec7f835bf4c40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000894 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* adlrvp: enable AP driven mode entryli feng2021-07-291-0/+2
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST= 1. make BOARD=adlrvpp_ite pass 2. on ADL-P RVP, connect USB4 device to port 0, AP requests to enter mode USB4; EC set up USB4 successfully, and enumeration in sysfs is correct. Signed-off-by: li feng <li1.feng@intel.com> Change-Id: Ia6e503c19871928b3b9cc5049079fb40778a6bea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999438 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* zephyr: asurada: cleanup board id/versionDenis Brockus2021-07-291-1/+1
| | | | | | | | | | | | | | | | | Make board_get_version an __override function. Removed unused CONFIG_PLATFORM_EC_BOARD_VERSION_ defines. BUG=b:195037412 BRANCH=none TEST=zmake configure -b $PROJ_HAYATO Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ie8bb565fb5d649c5e0de771e0dfd6fecaee07a53 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061264 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* keeby: Add GPIO_EC_CBI_WPAseda Aboagye2021-07-291-0/+3
| | | | | | | | | | | | | | | | | This commit simply adds the GPIO_EC_CBI_WP pin for the keeby boards and also sets CONFIG_EEPROM_CBI_WP. BUG=b:181769483 BRANCH=None TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I31694cb748d8b8a197b84634fbd9417d274a79d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046413 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* voema: Remove base sensor support kx022David Huang2021-07-291-2/+1
| | | | | | | | | | | | | | | Remove base sensor support kx022 due to kx022 not support gyro and base sensor need gyro. BUG=b:192301309 BRANCH=volteer TEST=make buildall -j succeeded. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I6ff1bf9488d816be680a395334ea3008b9280890 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3029802 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* tomato: enable port 0 bc12 functionTing Shen2021-07-292-2/+10
| | | | | | | | | | | | | | | | Tomoto port 0 bc1.2 solution is changed from PI3USB9201 to MT6360. Update board code to reflect this HW change. BUG=b:192422592 TEST=manually test bc1.2 detection BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I855815b5c8d85c9807455fe658a38bdac59b1399 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3031241 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* cherry: enable usb pdTing Shen2021-07-293-72/+213
| | | | | | | | | | | | | BUG=b:177391887 TEST=verify pd works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ied4516abef3d544b8b4bdf8355f0f9fc305629a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2793783 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* dalboz: not read thermisotr in S5Zick Wei2021-07-281-0/+5
| | | | | | | | | | | | | | | The thermistor: TEMP_SENSOR_SOC powerd by S5 power rail, EC will get abnormal high temperature when DUT get from G3 to S5, we ignore thermistor temperature in S5. BUG=none BRANCH=zork TEST=verify there's no shutdown/prochot message during EC power on. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: Ie755dfab741ce1340c75bbeb5eb53288381b1c0a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045427 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* baseboard kukui: Update kukui_board_id_map for EC IT81202Sue Chen2021-07-281-1/+24
| | | | | | | | | | | | | | | | EC_BOARD_ID is connected with 3300mV while using EC IT81202 that is different from STM32 with 1800mV. Therefore, it need to update kukui_board_id_map for EC IT81202. BUG=b:182772415 BRANCH=icarus TEST="mosys platform version -vvvv" and "ectool boardversion" can read correct Board ID on Cozmo. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I0bd518ec2d612b7ea42e160f55b4061ce459a274 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3054214 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
* keyboard: Use __override for keyboard_scan_configDaisuke Nojiri2021-07-2319-21/+19
| | | | | | | | | | | | | | | | | Currently keyboard_scan_config is defined by each board using CONFIG_KEYBOARD_BOARD_CONFIG. This patch makes it defined as __override hence removes CONFIG_KEYBOARD_BOARD_CONFIG. BUG=None BRANCH=None TEST=buildall Change-Id: I53a356741ba4d00e829ca59b74ee6dc704188728 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044403 Tested-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* zephyr: asurada: enable voltage regulatorDino Li2021-07-231-1/+1
| | | | | | | | | | | | | | | Fixed error of host commands (0x12c~0x130) for controlling voltage regulator. BUG=b:189855648 BRANCH=none TEST=Verified that no error on regulator host commands. (verified on both cros-ec and zephyr fw image) Change-Id: Ib7c5782e80262a38be0517181afbd78160847040 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3007380 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* brya: Remove pd_snk_is_vbus_providedCaveh Jalali2021-07-221-5/+0
| | | | | | | | | | | | | | | | The pd_snk_is_vbus_provided() function is only used when CONFIG_USB_PD_VBUS_DETECT_PPC is enabled. brya uses CONFIG_USB_PD_VBUS_DETECT_TCPC instead. BRANCH=none BUG=none TEST=buildall passses Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: If5a93025d6e870deb46717863c61c3d34be0283a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044413 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* cappy2:initial ECwangganxiang2021-07-221-0/+2
| | | | | | | | | | | | | | | create Cappy2 BUG=b:191718716 BRANCH=Keeby TEST=make BOARD=cappy2 pass Signed-off-by: wangganxiang <wangganxiang@huaqin.corp-partner.google.com> Change-Id: Id374b76eb020d429c5281ed6e9b7d1d7050c62d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3020642 Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Guybrush: Enable CONFIG_BACKLIGHT_LIDDiana Z2021-07-211-0/+5
| | | | | | | | | | | | | | | | | Guybrush has the GPIO set up for backlight disable, but doesn't have the config set and so we're not compiling in the code to actually disable backlight on lid close. BRANCH=None BUG=b:194326578 TEST=on guybrush, open and boot to confirm backlight is on. Close with the system in S0 and confirm it goes off Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If707525d9f4bb98a577f75e7017beae03638726c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044410 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* Guybrush: Add EC_ENTERING_RW signalDiana Z2021-07-212-1/+2
| | | | | | | | | | | | | | | | | Add this signal as it is present on more recent board versions. This should be fine on older board versions since it was a TP pin previously. BRANCH=None BUG=b:194320972 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I839027fecaac8d47992ae262f334c88c8a7311a7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044406 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Commit-Queue: Rob Barnes <robbarnes@google.com> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* guybrush: Use correct index for tmp112 SOCRob Barnes2021-07-212-2/+2
| | | | | | | | | | | | | | | This change fixes a bug where ADC_TEMP_SENSOR_SOC index was used in for the TMP112 SOC instead of TMP112_SOC BUG=b:176994331 BRANCH=None TEST=Check output of temps Change-Id: Ic27e38f5d4dfee3b270fe8490787575cf4cc7568 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3002883 Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* cherry: implement USB-A port power controlTing Shen2021-07-201-0/+10
| | | | | | | | | | | | | BUG=b:193499785 TEST=manually BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I1bda9b40bb8795837d25022f6f71661f7699d1cf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3023017 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* munna: munna board with STM32L431 ecBossen WU2021-07-203-3/+38
| | | | | | | | | | | | | munna board initialization. BRANCH=main BUG=b:188117811 TEST=make BOARD=munna; make buidall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I7de980f61d00f1b050924812265b7068d937a112 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909958 Reviewed-by: Shou-Chieh Hsu <shouchieh@chromium.org>
* herobrine: Support SKU IDPhilip Chen2021-07-191-0/+2
| | | | | | | | | | | | | BRANCH=none BUG=b:186264627, b:193807794 TEST=build herobrine_npcx7 and herobrine_npcx9 Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: If8870e33643f96658f4902d0fe26081712eb6cf7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035787 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* dedede: Make scope of SSFC definition per boardParth Malkan2021-07-193-124/+1
| | | | | | | | | | | | | | | | | | | | | | SSFC bit definition started diverging between coreboot and EC. To avoid conflicts move the definitions of SSFC bits within EC to per board instead of at a baseboard level. Base sensor and Lid sensor components are common across all boards Base Sensor - bits 0-2 Lid Sensor - bits 3-5 In addition, Sasuke uses bits 6-8 for usb superspeed mux Cret board uses bits 9-11 in coreboot for audio codec BRANCH=firmware-dedede-13606.B BUG=b:187694527 TEST=make buildall Signed-off-by: Parth Malkan <parthmalkan@google.com> Change-Id: Ib0f732e5d41668135ff180c545ff4bb6a1cb1427 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021932 Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Marco Chen <marcochen@chromium.org>
* honeybuns: Notify hpd->pd converter of DP_CONFIG messagesScott Collyer2021-07-171-0/+2
| | | | | | | | | | | | | | | | | | | | | This CL is part of a fix to delay sending DP_ATTENTION messages until after at least one DP CONFIG message has been received. Sending DP_ATTENTION messages priot to DP_CONFIG can cauase some port partners to abort alt-dp mode. BRANCH=quiche BUG=b:192051705 TEST=verifed on kasumi (grunt) that the display is extended correctly following usbc hotplug events. Previously, this case was failing 1 out of 3-4 times. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I84a962b2f315df28eda290ebae452e41fd6e0b32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035786 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* guybrush: Fix sensor_id for screen rotation to work on deviceBhanu Prakash Maiya2021-07-171-3/+3
| | | | | | | | | | | | | | | | | | | Looks like the iio:devices are mapped to fixed sensor_id in EC. Aligning sensor_id with other projects in ChromeOS EC. BRANCH=none BUG=b:178400750 TEST=Motion task implementation tested on Guybrush Rotate device and rotation works. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Signed-off-by: Latchiamaran Senram <latchiamaran.senram@bosch.corp-partner.google.com> Change-Id: Id2134c8d31471c8900cd7f6b3397d20dc2e64744 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035799 Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@google.com>
* guybrush: Enable LID ANGLE config on boardBhanu Prakash Maiya2021-07-171-2/+6
| | | | | | | | | | | | | | | | | | This patch implements lid_angle_peripheral_enable function. BRANCH=none BUG=b:178400750 TEST=Accel implementation tested on Guybrush $ ectool motionsense lid_angle Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Signed-off-by: Latchiamaran Senram <latchiamaran.senram@bosch.corp-partner.google.com> Change-Id: I0ece0c23350fd870c5fa696ae77dc221ef60dc4e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3029667 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* guybrush: Move ec task list from basebord to board level.Bhanu Prakash Maiya2021-07-161-25/+0
| | | | | | | | | | | | | | | | | | | | The order of tasks in the tasklist decides the priority of the tasks. Splitting tasks between baseboard and board level puts baseboards task at low priority and board tasks at highest priority. To put motion task at right priority, patch maintains one list at board level. BRANCH=none BUG=b:178400750 TEST=Motion task implementation tested on Guybrush Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Signed-off-by: Latchiamaran Senram <latchiamaran.senram@bosch.corp-partner.google.com> Change-Id: Ib21e296d7c0af13f3439335f12348eb027b63e35 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033337 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* asurada: add baseboard_init into common zephyr/cros-ecDenis Brockus2021-07-151-0/+9
| | | | | | | | | | | | | | | | | | This was added to baseboard.c but does not seem to be there anymore. The GPIOs are needed to enable USB-A after XHCI is completely initialized. BUG=b:187149602 BRANCH=none TEST=verify boot GPIOs enable USB-A VBUS after XHCI_INIT_DONE Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ieb5fb2e77722c308b3675cb54884115e4f88912a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033323 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Guybrush: Sleep the battery fuel gauge before hibernatingDiana Z2021-07-141-0/+4
| | | | | | | | | | | | | | | Before we go into hibernate, try to put the battery fuel gauge into sleep mode. Note we must be in a low current state for the gauge to actually enter this mode. BRANCH=None BUG=b:186774653 TEST=on guybrush, observe power reduction in Z5 Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie02aa3ede1b3a89592bdd5cd8e701887db3c2d9f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2967039 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* herobrine_npcx9: Update I2C busesWai-Hong Tam2021-07-141-0/+1
| | | | | | | | | | | | | Add the I2C bus for the RTC chip. The chip runs at 400KHz. BRANCH=None BUG=b:192253134 TEST=Built the herobrine_npcx9 image successfully. Change-Id: Ibf5eec51a938b7a1ce1d1379ae8c2ede2b2f4b03 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993218 Reviewed-by: Keith Short <keithshort@chromium.org>
* qcom: Move enabling/disabling 3.3V rail to the board levelWai-Hong Tam2021-07-142-0/+23
| | | | | | | | | | | | | | | | | | | | | | In the next generation, the 3.3V rail is not controlled by EC anymore. Move the control logic to the board level. The 3.3V rail should be enabled before the power on sequence, so use the hook chipset pre-init hook. Disable it on the chipset shutdown complete hook. For Trogdor, do it on the baseboard level. For Herobrine, do it on the board level, Herobrine-NPCX7, only. Herobrine-NPCX9 and other future boards don't need it. BRANCH=None BUG=b:187980397, b:192253134 TEST=Tested the Lazor EC-OS and Zephyr images and booted to AP. TEST=Tested the Herobrine-NPCX7 EC-OS and Zephyr images and booted to AP. Change-Id: I7e025123f8997629b9b0db46e30ea9c716bdbf99 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993213 Reviewed-by: Keith Short <keithshort@chromium.org>
* brya: Enable DPTF supportSumeet Pawnikar2021-07-141-0/+1
| | | | | | | | | | | | | | | This enables the handling of DPTF messages from the AP. BUG=b:191442254 BRANCH=None TEST=None Change-Id: Iff7dbb0b713f9b255db71ae9d3d83ca2be24f2ac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3015907 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* adlrvp: Add custom board ID reading functionVijay Hiremath2021-07-143-1/+7
| | | | | | | | | | | | | | | ADLRVP has a I/O expander + EEPROM based board ID reading implementation hence added overridable custom board ID reading function. BUG=none BRANCH=none TEST='ectool version' gives intended result Change-Id: I98e49de710f54683b8fbe9f6e9615b7de0aeb4ed Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3024669 Reviewed-by: AndreX Andraos <andrex.andraos@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* herobrine: Move GPIO alias to the board levelWai-Hong Tam2021-07-131-1/+0
| | | | | | | | | | | | | | Move the GPIO alias of EN_PP5000 from the baseboard level to the board level. The new Herobrine hardware will use a different name. BRANCH=None BUG=b:192253134 TEST=Built the herobrine_npcx7 EC-OS and Zephyr images successfully. Change-Id: I903b2646bfc39ce19713a35cd037402003f82591 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993212 Reviewed-by: Keith Short <keithshort@chromium.org>
* herobrine: Move hibernate config to the board levelWai-Hong Tam2021-07-133-23/+0
| | | | | | | | | | | | | | | Move the config of hibernate wake source and hook from the baseboard level to the board level. The new Herobrine hardware will use different wake sources and have different hook. BRANCH=None BUG=b:192253134 TEST=Built the herobrine_npcx7 EC-OS and Zephyr images successfully. Change-Id: Idbad8f985252fdef0657427d5f8d5883029a641f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993211 Reviewed-by: Keith Short <keithshort@chromium.org>
* guybrush: Configure LID_ACCEL hardware without FIFOBhanu Prakash Maiya2021-07-131-0/+12
| | | | | | | | | | | | | | | | | | | | | | 1. This patch puts LID_ACCEL in forced mode. 2. This patch moves ACCEL_FIFO defines to baseboard BRANCH=none BUG=b:178213305 TEST=1. ectool motionsense Motion sensing active Sensor 0: 0 0 0 Sensor 1: 0 0 0 Sensor 2: -336 -1360 -16288 2. Lid accel data is showing up on ectool. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Change-Id: If0eaa106478777a6266a77af2b47e91e354229ff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021753 Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com> Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Honeybuns: Don't propose Vconn swapsDiana Z2021-07-121-5/+2
| | | | | | | | | | | | | | | | Honeybuns doesn't require any cable information, so avoid proposing Vconn swaps in order to reduce traffic and reduce the liklihood of collisions with PD 2.0 partners. BRANCH=None BUG=b:192051705 TEST=on honeybuns, verify both ports can successfully connect and honeybuns never proposes a Vconn swap Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ic98663af7ee7727456b2c9c3e5200ca3080ec074 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3016408 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* system: Generalize system_get_board_version()Philip Chen2021-07-121-1/+1
| | | | | | | | | | | | | | | | | | Extend system_get_board_version() to support not only AP-sourced SKU ID but also EC-sourced SKU ID, whose getter function can be customized per board. BRANCH=None BUG=b:186264627 TEST=make buildall -j TEST=zmake testall Change-Id: I764868d6472fb66480a43d028e5a79933b10117d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3017602 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* guybrush: Remove CONFIG_SYSTEM_UNLOCKEDRob Barnes2021-07-121-1/+0
| | | | | | | | | | | | | | | We should no longer rely on the system being hard-coded to be unlocked. This should be determined at runtime from the write-protect status of flash. So, remove CONFIG_SYSTEM_UNLOCKED. BRANCH=none BUG=b:191333062 TEST=guybrush boots Change-Id: I57f281a8d2682b94aacabafc8258cf4da634551f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3001393 Reviewed-by: Diana Z <dzigterman@chromium.org>
* guybrush: enable BMI323 sensor on guybrushBhanu Prakash Maiya2021-07-092-0/+2
| | | | | | | | | | | | | | | | | | | Enable BMI323 sensor as BASE ACCEL and BASE GYRO on guybrush board. BRANCH=none BUG=b:178398789 TEST=Accel implementation tested on Guybrush EC commands: > accelinfo > acceldata Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Change-Id: I1bda8d0836dcb62b0d4a33750246a15931c77389 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984744 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* system: Clean up system_get_board_version()Philip Chen2021-07-095-5/+0
| | | | | | | | | | | | | | | | | | | Refactor system_get_board_version() a bit so that we can remove CONFIG_BOARD_VERSION_CUSTOM and CONFIG_BOARD_VERSION from config.h. BRANCH=None BUG=b:186264627 TEST=make buildall -j TEST=zmake testall Cq-Depend: chromium:3015243 Change-Id: Id5ab809493c297b7d330ea13dcd6934ec00042a6 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004112 Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gingerbread: Account for port C1 1.5A current limitScott Collyer2021-07-092-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds an override function for typec_get_default_current_limit_rp() for gingerbread. This allows port C0 to have a 3.0A current limit as desired, and still limit C1 to 1.5A. A new macro BOARD_C1_1A5_LIMIT was added to allow this feature to be used for honeybuns variants. This macro is also used to adjust the USB-PD SRC CAP current limit to 1.5A BUG=b:191793195 BRANCH=quiche TEST=verfied on Gingerbread that Rp = 3.0A is selected for C0 and Rp = 1.5A is selected for port C1. C0: > ucpd info cc1 = Rp cc2 = Open Rp = Rp_3.0 cc1_v = 2 cc2_v = 0 rx_en = 1 pol = 0 C1: > tcpc 1 dump ROLE_CTRL (0x1a) = 0x15 Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2853ddcbc7b1d76320e480bd4c11ad555dd52bad Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980440 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* kukui: disable CONFIG_CMD_FLASHINFO to reduce image sizeKeith Short2021-07-091-0/+1
| | | | | | | | | | | | | | | | | | Disable console command "flashinfo" to reduce image size. "flashinfo" is not used by the FAFT tests so it can safely be disabled. This saves over 500 bytes of RO and RW flash space each for the Kukui family. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2b08c1f1453443cf07b6fde03417817c8387a928 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3018170 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* adlrvp: Fix the change in cbi config nameThejaswani Putta2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | Rename CONFIG_CROS_BOARD_INFO to CONFIG_CBI_EEPROM in adlrvp to allign with other boards and get cbi utility working. BRANCH=none BUG=none TEST=build ec image and flash on adlrvp, cbi set/get works fine. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Change-Id: I787bb5e874daa930787c2010a551c8f9e494de96 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999432 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* Guybrush: Set both FRS signals as GPIODiana Z2021-07-072-0/+17
| | | | | | | | | | | | | | | | Both PPCs require the FRS signal be set as soon as we've enabled FRS swapping. Use the board FRS enable function to set these through the TCPC ioexpander. BRANCH=None BUG=b:183586640 TEST=on guybrush, attach WooHubs to C0 and C1, and ensure FRS can complete successfully Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I486b29c128e1d31f9d35e15df1e12a1eb3f2f3db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993559 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Guybrush: Switch to TCPC sourcing detectionDiana Z2021-07-072-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Both PPC drivers used by guybrush report Vbus sourcing through a set of cached flags. However, with FRS in the picture their flags will no longer accurately reflect whether we're sourcing. The TCPC however will correctly report that we're sourcing in its power control register. This should also be a more reliable source of information when the system is resetting or sysjumping. It no longer seems necessary to confirm that a port is not sourcing before performing a power supply reset, so this has been removed as well. BRANCH=None BUG=b:183586640 TEST=on guybrush with FRS enabled, perform a failed FR swap and see that Type-C ErrorRecovery correctly turns off Vbus. Perform a successful FR swap and ensure we don't have a lingering Vbus supplier in the charge manager. With no battery, boot from both ports with only a charger plugged in. Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I7833f52dc84e2d5b097c4deb6acf7f2c29b8d48a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987597 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* asurada: move regulator code into a separate fileDino Li2021-07-063-39/+47
| | | | | | | | | | | | | | With this CL, cros ec and zephyr are both able to build the code. BUG=none BRANCH=none TEST=boot asurada and there is no error on regulator host commands (0x12c~0x130) Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I2cc34891d5d1118ed90d976d404bab1f7b5ce5e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004126 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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