summaryrefslogtreecommitdiff
path: root/board/adlrvpp_ite
Commit message (Collapse)AuthorAgeFilesLines
* board: Sort header filesJeremy Bettis2022-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | Sort all includes in board with the clang-format rules used by the zephyr project. BRANCH=None BUG=b:247100970 TEST=zmake build -a TEST=./twister --clobber -v -i TEST=make -j72 buildall_only runtests TEST=zmake compare-builds -a Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I6ad72b167cbb768a64c338fa633eb4bf5a401897 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4060360 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
* Update license boilerplate text in source code filesMike Frysinger2022-09-125-5/+5
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: rename HOSTCMD_ESPI_* to HOST_INTERFACE_ESPI_*Michał Barnaś2022-09-091-2/+2
| | | | | | | | | | | | | | | Rename ESPI additional configs to match the name of base config that selects ESPI as HOST_INTERFACE. BUG=b:195416058 BRANCH=main TEST=zmake testall && make buildall Change-Id: I137449a1a58b1ea0d9794ebc0900e1b68413819d Signed-off-by: Michał Barnaś <mb@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3291744 Reviewed-by: Sam Hurst <shurst@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* board/adlrvpp_ite/board.h: Format with clang-formatJack Rosenthal2022-06-281-40/+40
| | | | | | | | | | | BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f203e86a3e3754eaf271cfc9297e4b96f981c8a Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727963 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* adlrvp: Add usb_mux taskDeepti Deshatty2022-04-031-0/+1
| | | | | | | | | | | | | | | Enable usb_mux task for adlrvp as virtual mux sets may take significant time to complete. BRANCH=None BUG=None TEST=on adlrvpn, verified type-c USB, DP functionality Change-Id: I0ff30168cdeff616c6e3ae10d99959b70e1fdff8 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3359114 Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* adlrvp: remove pull up set for EC servo uart linesDeepti Deshatty2022-02-171-1/+1
| | | | | | | | | | | | | | | Removed GPIO_PULL_UP set for the EC servo uart lines. With this change suzy-q EC logs Tx works fine on rvp. BUG=none BRANCH=none TEST=Verified Micro servo and SuzyQ EC logs on ADL-N Rvp Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Change-Id: Id2b6be2e8d30776f42d25d353b5545e294d8f71c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3282978 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvpn: configure charger vsys min registerDeepti Deshatty2022-01-232-3/+18
| | | | | | | | | | | | | | | | | | | | | | | ADL-N uses the similar charger chip as Brya i.e BQ25720 Referring to the b:196184163 charger system voltage register should be set based on the AC or AC+battery conditions. New API set_charger_system_voltage() is implemented for this. API is called when AC/battery is connected/disconnected. Changes helped to solve the PROCHOT assertion by charger chip when no battery is connected to the RVP. BRANCH=none BUG=none TEST=verified change on adlrvp-n board. PROCHOT not asserted when no battery connected to the RVP. Change-Id: Ic21d8008530e08f2b7d26994665ca8cc37cffdfe Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3338099 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* ec: Rename GMR_TABLET_MODE_GPIO_L to GPIO_TABLET_MODE_LAndrew McRae2022-01-201-1/+1
| | | | | | | | | | | | | | Normalise the name of the tablet mode detection GPIO so that everyboard does not need to redefine it. BUG=none TEST=zmake testall; make buildall BRANCH=none Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: Ifb458e755d1e00c0cff66a02c78dfccaba2d070c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3397141 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPIKeith Short2021-11-191-3/+3
| | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842 Tested-by: Michał Barnaś <mb@semihalf.com>
* ADL_RVP: Enable pre-task I2C transactionsVijay Hiremath2021-10-211-0/+22
| | | | | | | | | | | | | | | | | ADL-RVP needs to access IOEX based GPIOs pre-task to configure the SBU lines to CCD or AUX hence enabled pre-task I2C transactions. BUG=none BRANCH=none TEST=Able to configure config SBU lines for CCD pre-task Change-Id: I1512dc4c1837e769f39e1dd595ae2ba1b4cbdf17 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3194986 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* board: Rename RSMRST_L_PGOOD as PG_EC_RSMRST_ODLfirmware-chameleon-14280.B-mainDivya Sasidharan2021-10-121-1/+0
| | | | | | | | | | | | | | | | | GPIO_RSMRST_L_PGOOD is also used as GPIO_PG_EC_RSMRST_ODL creating redundancy. Removing it will help need for redefinitions for zephyr. Remove reference to GPIO_RSMRST_L_PGOOD in zephyr BUG=b:200975143 BRANCH=main TEST=make buildall -j, boot up on brya Change-Id: Iff46595174c54db347b69cff3ad9e266ba9fd535 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180808 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* adlrvpp_ite: enable internal pull-up for GPGOli feng2021-10-021-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | It is observed that PD port 3 has TCPC interrupt storm, the TCPC interrupt pin GPJ3 stays active low even no interrupt coming. The root cause is GPJ3 is configured as voltage comparator by GPG0 after EC power on. Remove GPGO external pull-up resistor to fix this issue. GPGO is PD port 1 TCPC interrupt pin, enable internal pull-up since external pull-up resistor is removed. BUG=b:200265672 BRANCH=none TEST=on ADL-P DDR5 RVP, apply CL:3111455 and CL:3114705 to enable low power mode. Don't see interrupt storm on PD port 3. Connect Gatkex to PD port 1, enter USB4 mode successfully. Connect Gatkex to PD port 3, enter USB4 mode successfully. Signed-off-by: li feng <li1.feng@intel.com> Change-Id: If66011ca86a268556ce69bd06f938c92407217aa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193511 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* adlrvp: Increase EC clock frequencypoornima tom2021-08-181-0/+4
| | | | | | | | | | | | | | | | | With all four PD tasks enabled, ADLRVP board was rebooting with WDT errors. On increasing the frequency from 48MHZ to 96MHZ, the issue got resolved. BUG=b:195406641 BRANCH=None TEST=ADL P RVP booting fine without any WDT errors Signed-off-by: poornima tom <poornima.tom@intel.com> Change-Id: I7f8ea030c2a9837f4468e2bcdd9fc6de00c33eb4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067290 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp_ite: Trigger TCPC interrupts on falling edge onlyVijay Hiremath2021-08-171-7/+7
| | | | | | | | | | | | | | | To avoid unnecessary waking of USBC task changed code to Trigger TCPC interrupts on falling edge only. BUG=none BRANCH=none TEST=Added print statements in ISR and observed, Type-C interrupts are triggered only on falling edge only. Change-Id: I91ea8a23fe9736fbd28ab302b4ccc44447470386 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060258 Reviewed-by: caveh jalali <caveh@chromium.org>
* ADLRVP: Make code robust for validating TCPC vendorsVijay Hiremath2021-04-263-14/+19
| | | | | | | | | | | | | | | | | Intel Reference Validation Platform is designed to test multiple combinations of hardware thus help enable vendors seamlessly. Added task based TCPC code enablement so that TCPC vendors can easily hook their hardware, make the code changes and validate their TCPC. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I989b6a35c6ff3f96150d09de11458886f9642d1f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823167 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Use PCA9675 I/O expander driver structureVijay Hiremath2021-04-232-0/+3
| | | | | | | | | | | | | Updated the code use PCA9675 I/O expander's standard driver structure. BUG=b:169814014 BRANCH=none TEST=ADLRVP can configure retimer & CCD works Change-Id: I61eef08214a64382338321f4a2dae9f7cfd980da Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2845014 Reviewed-by: caveh jalali <caveh@chromium.org>
* genvif: Use VIF overrides by defaultAbe Levkoy2021-03-301-0/+3
| | | | | | | | | | | | | | Use board-specific override files when generating VIFs for boards. BUG=b:172276715 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I197365018ceb8197c22d631cebf4cbce1c0119f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785506 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* adlrvp: cleanup: Move common files to baseboardVijay Hiremath2021-02-224-519/+1
| | | | | | | | | | | | | | | | | Moved the ADLRVP specific common files to baseboard so that the RVP variants with multiple MECC clients can leverage these files without copying them over to board files. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I19739a189aa29c198422f1e2013d59f5da97b02f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706259 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* adlrvp: Modify watchdog timerSooraj Govindan2021-02-111-0/+10
| | | | | | | | | | | | | | | | | Frequent watchdog timer resets are seen, with the increase in number of type-c ports. So increase the timer value to support more type-c ports. BRANCH=none BUG=179760905 TEST=make sure DUT is not rebooting due to EC watchdog reset, after giving 'shutdown -h now' command. Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: Iaa79e80d383336c55cf0d16973f2f1e8321e0679 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2683615 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* config: Provide default VCONN Swap delayAbe Levkoy2021-01-221-1/+0
| | | | | | | | | | | | | | | | | Almost every relevant board copy-pastes 5000 us. Make that the default and get rid of the redundant definitions. This is the approximate result of this command: find . -type f -name *.h | xargs sed -i -E \ '/#define CONFIG_USBC_VCONN_SWAP_DELAY_US[[:space:]]+5000[[:space:]]/d' BUG=b:144165680 TEST=make buildall BRANCH=none Change-Id: Ife86f9752971abcd7ab5ad5a5e607eb2ccbde2ba Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* config: Make VCONN Swap delay a documented optionAbe Levkoy2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This is the approximate result of the following command, run from platform/ec: find . -type f -\( -name '*.c' -o -name '*.h' -\) | \ xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g' Fix some latent formatting errors in usb_pd_protocol.c, because they were preventing pre-upload hooks from passing. BUG=b:144165680 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* adlrvp-p: Enable temperature sensor config - CONFIG_TEMP_SENSOR.Deepti Deshatty2021-01-211-0/+3
| | | | | | | | | | | | BRANCH=none BUG=none TEST=Tested temperatures using "ectool temps" command. Change-Id: Ic93ab1b0c0718781b433966ffd735013a437a6f0 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2639423 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Remove Mutex from bb_retimer_powerhandle()Poornima Tom2021-01-201-13/+4
| | | | | | | | | | | | | | | | The mutex was introduced to lock the retimer SPI access in shared SPI model. With the latest BB retimer driver, I2C retry is introduced to fasten the SPI access hence removed the mutex and additional delay. BRANCH=none BUG=none TEST=Tested on ADLRVP with TBT dock. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I7c965ff2b2d880f22ce0bbd57245bf52a8bf5dd5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2631890 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp: Rename TGL chipset type to ADL chipsetPoornima Tom2021-01-201-1/+1
| | | | | | | | | | | | | | | | Renamed TGL chipset type to ADL chipset type. Just like TGL maps to icelake, ADL chipset type also maps to icelake. BRANCH=none BUG=b:173575131 TEST= Tested on ADL RVP. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: Ia7b23dd1c3fb92807f8e3f7c226fe8a18f0c5b6a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2634890 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* adlrvp:Split the ADLRVP board filesPoornima Tom2021-01-155-425/+479
| | | | | | | | | | | | | | | | | | Common ADL RVP configuration and ITE8xx EC controller specific configuration are placed separately in two different files. This will help in easier porting of board files for different EC vendors who use MECC connector. BRANCH=none BUG=none TEST=ADLRVP-P & ADLRVP-M with ITE EC boot to OS. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I6ec9aa216aeb3d552d355f31d6ec4361345c85ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2626805 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* adlrvpm: add Alderlake-M RVP supportSooraj Govindan2021-01-063-1/+43
| | | | | | | | | | | | | | | | | | | | | | Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. USB TYPE-C - TCPC over PD AIC 4. H1 Close Case Debug 5. LED 6. Keyboard BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpm_ite -j; sudo util/flash_ec --board=adlrvpm_ite --image=<path> Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I3ee12a0875cb6310c3b5767cab90f17f9646e02c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2584553 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* TCPMv2: Update source-out configsDiana Z2020-12-241-6/+0
| | | | | | | | | | | | | | | | | | | | Now that the DPM will be handling source-out decisions for TCPMv2, remove references to its old configuration options from TCPMv2 boards in order to avoid any confusion as to what code is running now. Also remove the charge manager notifications of sink attach/detach since the policy is being centralized into the DPM. Note that the previous configuration options only ever allocated one 3.0 A port, and so the default number of 3.0 A ports has been set to 1. BRANCH=None BUG=b:168862110,b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie452e3da32b04226503539daa67b6b9f4a58aa58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597431 Reviewed-by: Keith Short <keithshort@chromium.org>
* Mux: Program retimer mux mode firstDivya Sasidharan2020-12-101-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Configure BB retimer first and then TCSS mux for the following boards 1. Adlrvpp 2. Boldar 3. Copano 4. Drobit 5. Halvor 6. Lingcod 7. Malefor 8. Terrador 9. Tglrvpu/y 10.Todor 11.Trondo 12.Volteer 13.Voxel BUG=b:166300460 BRANCH=None TEST=Able to configure the BB retimer before the TCSS mux Change-Id: Ife3074e3f45f00d3263eb0c5c2bea713db67541b Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506629 Reviewed-by: Keith Short <keithshort@chromium.org>
* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* adlrvpp: Modify GPIO assignments as per Rev 2 schematicsSooraj Govindan2020-12-031-10/+10
| | | | | | | | | | | | | | | | | Add support for "Revision 2 add-in card" to enable Chrome EC, on AlderLake reference platform. BRANCH=None BUG=b:174290307 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpp_ite -j; sudo util/flash_ec --board=adlrvpp_ite --image=<path> Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I314ed281b12f41c1539afb9716301af6fd7ede26 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2544294 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* ADLRVP: Enable PWM FanPoornima Tom2020-12-031-0/+7
| | | | | | | | | | | | | | BRANCH=None BUG=b:169551130 TEST=PWM fan is able to run Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: Ie042402803e5cd18780951b2efe89eae033126aa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563422 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Tested-by: Sooraj Govindan <sooraj.govindan@intel.com>
* ADLRVP: Remove PP5000 rail configPoornima Tom2020-12-031-1/+0
| | | | | | | | | | | | | | | | | Both 3.3A & 5VA rail come up or go down together by EC_DS4 signal hence removed PP5000 rail config. BRANCH=None BUG=b:169551130 TEST=make build all; Tested on ADLRVP Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I7c3a66b53ada616071998d111bf822a5b7fbcc81 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563425 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Tested-by: Sooraj Govindan <sooraj.govindan@intel.com>
* ADLRVP:Support for 100w typeC power adapterPoornima Tom2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | ADL SOC has a TDP of 45W and the RVP can support up to 200W power.Hence, increased the power support to 100W. BRANCH=None BUG=b:173081793 TEST=use chgsup command and list charger type negotiated values. Tested below on ADL: When Typec Charger connected to Port3: > chgsup port=3, type=0, cur=3000mA, vtg=20000mV, lsm=1 when TBT dock connected to Port1: > chgsup port=1, type=0, cur=4500mA, vtg=20000mV, lsm=1 when AC charger connected: > chgsup port=4, type=3, cur=5263mA, vtg=19000mV, lsm=0 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I0677519a68013dbc593539b692bad5016b52654f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531771 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp:Separate battery configuration into board specific filesAyushee Shah2020-11-253-0/+54
| | | | | | | | | | | | | | | | | | This CL adds the battery configuration from interlrvp baseboard to board specific file for Alderlake, Tigerlake and jasperlake platform so that same manufacturer battery but with different config params can be used on intended platforms. BUG=b:174129818 BRANCH=None TEST=Able to see correct battery configuration in "battery" EC command and can see the battery charging and discharging. Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: I639eb4466c49dbdc01d31feb4ace8844a6b1ac87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557763 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* adlrvpp_ite: Enabling sourcing of 7.5A on type-C portsKeith Short2020-11-121-0/+6
| | | | | | | | | | | | | | | | | To support USB4, source a total of 7.5A on the type-C ports. This ensures that if the first device requests 3A (15W), the chromebook continues to source 3A even after a second device is connected. BUG=none BRANCH=firmware-volteer-13521.B-master TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I14b5412602aaa0e8671e76a45eb0090a4d3e148c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2533490 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* adlprvp: Add support for SYS_PWROK_ECSooraj Govindan2020-11-102-5/+14
| | | | | | | | | | | | | | | | | | Per the power sequencing requirements, SYS_PWROK_EC should be driven based on ALL_SYS_PWRGD deassertion/assertion. BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpp_ite -j; sudo util/flash_ec --board=adlrvpp_ite --image=<path> Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: Ifd6805dc878cbbaa401f43b325a42d1b1431b1ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521550 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* usb: Remove references to usb23Caveh Jalali2020-11-062-26/+0
| | | | | | | | | | | | | | | | | The TCSS port mapping is not used by the EC and the higher layers no longer query the EC for this mapping. We can remove this feature and disable CONFIG_INTEL_VIRTUAL_MUX which was added to enable it. BRANCH=none BUG=b:153941950 TEST=buildall passes Change-Id: I2d7f51212f3e64d74827d7f82654eb93534b8db4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427632 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* ADLP-RVP: Config to enable TBTPoornima Tom2020-11-031-0/+11
| | | | | | | | | | | | BRANCH=None BUG=b:171409539 TEST=Able to enter TBT mode Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I81fb01ac9e537ded25cfffc8a9691c173ed41a49 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2490900 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* intelrvp: Keep PPC specific code generic in baseboardVijay Hiremath2020-10-311-0/+4
| | | | | | | | | | | | BUG=none BRANCH=none TEST=PPC interrupt is invoked on ADL-RVP Change-Id: Ib41be079d0d5731627193d15b66bb9949bd2722f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508156 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* adlprvp: add Alderlake RVP supportPoornima Tom2020-10-285-0/+812
Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. USB TYPE-C - TCPC over PD AIC 4. H1 Close Case Debug 5. LED 6. Keyboard BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpp_ite -j; sudo util/flash_ec --board=adlrvpp_ite --image=<path> Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
View Lorry Controller Status