| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | asurada: enable PPC syv682x on C0/C1stabilize-quickfix-13099.93.B-masterstabilize-13099.94.B-masterstabilize-13099.90.B-masterstabilize-13099.85.B-masterstabilize-13099.73.B-masterstabilize-13099.70.B-masterstabilize-13099.118.B-masterstabilize-13099.110.B-masterstabilize-13099.101.B-masterrelease-R84-13099.B-master | Eric Yilun Lin | 2020-05-15 | 1 | -2/+55 |
| | | | | | | | | | | | | | | | | | Enable PPC on C0 and C1, where C1 port is optional and dependent to the daughter board connected. BUG=b:152562604 TEST=ensure C0/C1 can sink and source power. BRANCH=master Signed-off-by: Ting Shen <phoenixshen@google.com> Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Change-Id: I2fabe59562ffbe63e91b60f36b726d63fefdc83b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195721 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> | ||||
| * | asurada: enable C0/C1 USBPD | Eric Yilun Lin | 2020-05-14 | 1 | -0/+24 |
| This CL enable it81202 on-chip TCPC at C0 and C1 port. The functionality is not completed yet (TODO: PPC). C0: on the main board. C1: on the subboard. BRANCH=master BUG=b:152562604 TEST=ensure C0 and C1 can do PD-comm (SNK and SRC) Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Change-Id: Ia8a2e557fd376a05f422bc1139abfd78be0c2b58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192466 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Ayo Wu <ayowu@google.com> | |||||
 |
index : delta/coreboot/chrome-ec.git | |
| review.coreboot.org: chrome-ec.git |
| summaryrefslogtreecommitdiff |