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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-0520-2195/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* brya: Modify thermal_paramsOwen_Ou2021-09-232-26/+27
| | | | | | | | | | | | | | | | | Modify brya's thermal_params. BUG=b:181271666 BRANCH=none TEST=make -j BOARD=brya and flash brya p2 can boot. Signed-off-by: Owen_Ou <Owen_Ou@compal.corp-partner.google.com> Change-Id: I00c3991e2b27d1ac16489bed43204d388a557ae5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3132312 Tested-by: Owen Ou <owen_ou@compal.corp-partner.google.com> Auto-Submit: Owen Ou <owen_ou@compal.corp-partner.google.com> Commit-Queue: caveh jalali <caveh@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: SamSP Liu <samsp_liu@compal.corp-partner.google.com>
* Revert "DP/TBT/USB4: Retimer WA resolved Brya TBT lane bonding issue in AP mode"madhusudanarao amara2021-09-231-14/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit f0985f8a11585f6a704aa94a8354bd5b934619ac. Reason for revert: Issue is resolved after setting the Force BB Retimer GPIO (GPP_E4) to 0. It is a coreboot change. BUG=b:195375738 BRANCH=None TEST=TBT enumerated no lane bonding issue is observed with above coreboot code change with reverted EC WA. Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.corp-partner.google.com> Change-Id: I09a8a53aec9ba3757189a091606922bc7a133ba7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3162936 Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* board: Do not enable gyroscope by defaultGwendal Grignou2021-09-231-11/+1
| | | | | | | | | | | | | | | | | | | | | Enable gyroscope only when the AP needs it. It is not used by the EC. For lid calculation, set frequency at 10HZ, the drivers will calculate higher frequencies when needed. Modify other boards as well: Use awk '/\.type = MOTIONSENSE_TYPE_GYRO,/ { check_config=1 } \ /\.config = / { if (check_config) { print FILENAME,$0 } } \ /\.type = MOTIONSENSE_TYPE_[^G]/ { check_config=0 }' board/*/sensors.c | \ cut -d ' ' -f 1' to locate the impacted files (board.c as well). BUG=none BRANCH=none TEST=Check rotation is still working on brya Change-Id: I45d82d00c30e35541df80d1b7805f8302b3d98ff Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170174 Reviewed-by: Keith Short <keithshort@chromium.org>
* led_pwm: split color map on a separate structureFabio Baltieri2021-09-211-1/+1
| | | | | | | | | | | | | | | | Currently color map is reusing the same structure as the channel and callback selection, which is a bit wasteful and somewhat confusing. Split it to its own struct with just three uint8_t fields. BRANCH=none BUG=none TEST=build only Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: I56992fa9525db46980e450eb6569ba8291987b9b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168864 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Yuval Peress <peress@google.com>
* brya: Enable PS8815_FORCE_DIDCaveh Jalali2021-09-211-0/+1
| | | | | | | | | | | | | | | This enables a reliable way to determine the ps8815 chip revision even when its firmware is inoperative. BRANCH=none BUG=b:186189039 TEST=verified the brya EC reports the correct device ID when the firmware is corrupted. Change-Id: I60808c0ae3312b11ebaf0848eb77a8134a943b49 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093035 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB Retimer: Add new HPD callback to boardsDiana Z2021-09-161-0/+2
| | | | | | | | | | | | | | | Now that the BB retimer has its own HPD interface, add this interface to every board using the bb_usb_retimer driver. BRANCH=None BUG=b:195773400 TEST=on voxel, pass tast typec.Mode*.manual Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ia70d139431739e8f2c0577359cb3aaa7fb906d0a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163930 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* brya: adjust default ALS calibrationBoris Mittelberg2021-09-111-3/+3
| | | | | | | | | | | | | | | Using non-zero coefficiants for initial ALS array removes the need of manual ALS calibration (ectool motionsense calibrate 3) BRANCH=none BUG=b:195332927 TEST=on brya id 2 the backlight changes depending on ambient light Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I71932c605db0f8f1c42bc62796b5f25c5eb3cacf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155296 Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Commit-Queue: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* brya: enable fan controlBoris Mittelberg2021-09-071-4/+1
| | | | | | | | | | | | | | | Enable fan control for Brya reference BRANCH=none BUG=b:196003718 TEST=Fan stops when system (id 2) is turned off from login screen. Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: If3646b60e1442b55494e4c7f5204624a6fc285a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095013 Reviewed-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Tested-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.corp-partner.google.com>
* brya: Move charger config from baseboard to boardDavid Huang2021-09-022-0/+2
| | | | | | | | | | | | | | | Move charger config from baseboard to board. Change Kano charger to isl9241. BUG=none BRANCH=brya TEST=make buildall -j succeeded. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: Ia97424bbcf0654127e21c47d6834ad6c2c6163ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3132556 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Tune thermal_params, adc_channels for board ID 1Caveh Jalali2021-08-272-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:183452273,b:181271666 TEST=verified tmep sensors report plausible values on board ID 1 and 2: > adc TEMP_DDR_SOC = 1749 mV TEMP_AMBIENT = 1749 mV TEMP_CHARGER = 1556 mV TEMP_WWAN = 1815 mV > > temps DDR and SOC : 304 K = 31 C 0% Ambient : 304 K = 31 C 0% Charger : 310 K = 37 C 0% WWAN : 302 K = 29 C 0% > > thermalget sensor warn high halt fan_off fan_max name 0 0 343 353 308 323 DDR and SOC 1 0 348 353 313 328 Ambient 2 0 348 353 313 328 Charger 3 0 348 353 313 328 WWAN > also, on board ID 1: > adc TEMP_DDR_SOC = 1784 mV TEMP_AMBIENT = 1168 mV TEMP_CHARGER = 1168 mV TEMP_WWAN = 1168 mV > > temps DDR and SOC : 303 K = 30 C 0% Ambient : 322 K = 49 C 60% Charger : 322 K = 49 C 60% WWAN : 322 K = 49 C 60% > > thermalget sensor warn high halt fan_off fan_max name 0 0 343 353 308 323 DDR and SOC 1 0 348 353 313 328 Ambient 2 0 348 353 313 328 Charger 3 0 348 353 313 328 WWAN > We simply see ambient, charger, WWAN report the same sensor. Change-Id: I1d6dd171b09ea2ebb22193d52ae57804920d740c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3116991 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* adc: Update board files to match adc.h refactorCaveh Jalali2021-08-271-1/+1
| | | | | | | | | | | | | | This updates a few board files that were including adc_chip.h instead of adc.h. adc_chip.h should not be included explicitly in most cases. BRANCH=none BUG=b:181271666 TEST=buildall passes Change-Id: I42f8b5b2129ebe18a96d089f0355b581cba1b274 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120316 Reviewed-by: Keith Short <keithshort@chromium.org>
* brya: Support temp sensors on board ID 2Caveh Jalali2021-08-272-11/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Brya board ID 2 has 4 temp sensors. This updates adc_channels, temp_sensors, and thermal_params accordingly. BRANCH=none BUG=b:183452273,b:181271666 TEST=verified tmep sensors report plausible values on board ID 2: > adc TEMP_DDR_SOC = 1749 mV TEMP_AMBIENT = 1749 mV TEMP_CHARGER = 1556 mV TEMP_WWAN = 1815 mV > > temps DDR and SOC : 304 K = 31 C 0% Ambient : 304 K = 31 C 0% Charger : 310 K = 37 C 0% WWAN : 302 K = 29 C 0% > > thermalget sensor warn high halt fan_off fan_max name 0 0 343 353 308 323 DDR and SOC 1 0 348 353 313 328 Ambient 2 0 348 353 313 328 Charger 3 0 348 353 313 328 WWAN > Cq-Depend: chromium:3116991 Change-Id: I5a973f8ad281f11713c64974ac2848a3655eee17 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3116989 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* DP/TBT/USB4: Retimer WA resolved Brya TBT lane bonding issue in AP modemadhusudanarao amara2021-08-061-0/+14
| | | | | | | | | | | | | | | | | In AP Mode DP exit to TBT entry is causing TBT lane bonding issue. Issue is not seen by calling the retimer reset as WA at the time of disconnect mode configuration. Revert this patch after getting the actual fix. BUG=b:193402306 BRANCH=None TEST=Checked TBT enumeration in AP Mode TOREVERT=b:195375738 Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.corp-partner.google.com> Change-Id: Ia22e061a863940b2a13ad5a38f4fe130737c5c20 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058157 Reviewed-by: Keith Short <keithshort@chromium.org>
* brya: Fix fan turn high and low momentary in G3 and DC onlyOwen_Ou2021-08-061-2/+2
| | | | | | | | | | | | | | | | | Base on nuvoton's suggest modify PWM's flags and frequency. BUG=b:194935446 BRANCH=None TEST=Brya fan can keep 33% and can't turn high and low momentary in G3 and DC only. Signed-off-by: Owen_Ou <Owen_Ou@compal.corp-partner.google.com> Change-Id: Ie0321d904d8cd2aa9de7dbc8559521b4cba12b8c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3070808 Auto-Submit: Owen Ou <owen_ou@compal.corp-partner.google.com> Tested-by: Owen Ou <owen_ou@compal.corp-partner.google.com> Commit-Queue: Owen Ou <owen_ou@compal.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* keyboard: Use __override for keyboard_scan_configDaisuke Nojiri2021-07-231-1/+1
| | | | | | | | | | | | | | | | | Currently keyboard_scan_config is defined by each board using CONFIG_KEYBOARD_BOARD_CONFIG. This patch makes it defined as __override hence removes CONFIG_KEYBOARD_BOARD_CONFIG. BUG=None BRANCH=None TEST=buildall Change-Id: I53a356741ba4d00e829ca59b74ee6dc704188728 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044403 Tested-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* brya: Report port TBT capabilityCaveh Jalali2021-07-151-0/+16
| | | | | | | | | | | | | | | | This sets up override functions for brya to correctly report each port's thuderbolt compatibility. BRANCH=none BUG=b:192639464 TEST=buildall passes Change-Id: I5d26a087a51e2a6228fd76f7070d4f29960993af Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3029661 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: disable debug accessory control on port C0Boris Mittelberg2021-07-141-1/+2
| | | | | | | | | | | | | | This will release Burnside Bridge from reset and fix the issue when Servo's USB hub disappears after Servo was reset. BRANCH=none BUG=b:191516281 TEST=running deployment in the lab Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I6a65ffa13903adf96686681d961818ffe0e68fb1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3018683 Reviewed-by: caveh jalali <caveh@chromium.org>
* Brya: fix LSM6DSO drv_data overlappingKo_Ko2021-07-131-2/+4
| | | | | | | | | | | | | | | | | The base g-sensor provides 2 functions: accelerometer and gyro. EC need to assign 2 different addresses to store each calibration data. BRANCH=none BUG=b:184779743 TEST=flash ec onto DUT Signed-off-by: Ko_Ko <Ko_Ko@compal.corp-partner.google.com> Change-Id: I18e3e2d3f8613fe9597ffb92a26390f5c9e72b29 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3016493 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: Ko Ko <ko_ko@compal.corp-partner.google.com> Tested-by: Ko Ko <ko_ko@compal.corp-partner.google.com>
* brya: Remove USB_C1_RT_INT_ODL as interrupt sourceCaveh Jalali2021-06-291-1/+1
| | | | | | | | | | | | | | | This disables interrupts on USB_C1_RT_INT_ODL. We do not use this pin with the current selection of USB DBs. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I423d5c1c3ef6e86f393fc9ce35230f1c6ab62607 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987914 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Config USB_C0_C2_TCPC_RST_ODL as ODRCaveh Jalali2021-06-291-2/+2
| | | | | | | | | | | | | | | This configures USB_C0_C2_TCPC_RST_ODL as ODR_LOW instead of driven low since this signal has a board level pull-up. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: Ib199a88349242489481896cfbe8fcbdb303810b9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977474 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Enable PCH_WAKE GPIO for board ID 2Caveh Jalali2021-06-291-1/+1
| | | | | | | | | | | | | | | We originally intended to eliminate PCH_WAKE on board ID 2, but we will use it after all. So, configure it to ODR_HIGH. BRANCH=none BUG=b:188735747 TEST=boots on board ID 1 Change-Id: Ia0fbd373fd5f9cdc37a6eaa59abf09362d4184e7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993548 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Set retimer interrupt trigger to FALLINGCaveh Jalali2021-06-291-3/+3
| | | | | | | | | | | | | | The EC GPIO review recommends setting the retimer interrupts to trigger on the FALLING edge instead of BOTH. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I33df4babcee5dcbf72920941b40a167e953d7342 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977481 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Set BC12 interrupt trigger to FALLINGCaveh Jalali2021-06-291-3/+3
| | | | | | | | | | | | | | The EC GPIO review recommends setting the BC12 interrupts to trigger on the FALLING edge instead of BOTH. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I70284754d4a72c74f972b352165a172756167056 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977480 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Set PPC interrupt trigger to FALLINGCaveh Jalali2021-06-281-3/+3
| | | | | | | | | | | | | | The EC GPIO review recommends setting the PPC interrupts to trigger on the FALLING edge instead of BOTH. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I8735d122e07fde56e1525cbfd38a2732a30f76ad Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977479 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Set TCPC interrupt trigger to FALLINGCaveh Jalali2021-06-281-2/+2
| | | | | | | | | | | | | | The EC GPIO review recommends setting the TCPC interrupts to trigger on the FALLING edge instead of BOTH. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I89bd144700f35dea952d9fbd0bf874750e1ac40a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977478 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: support board ID 2 IO expander GPIO shuffleCaveh Jalali2021-06-283-13/+60
| | | | | | | | | | | | | | | | | | | | This updates the IO expander GPIO definitions for board ID 2. We also need to support board ID 1, so the legacy definitions are captured in the IOEX table as additional IO expanders. All code that accesses the IO expander table knows which entries are valid for a given board ID and all entries are market DISABLED at compile time, so there are no conflicts. BRANCH=none BUG=b:190867210 TEST=boots on board ID 1, can read BB registers when USB device is plugged in. Change-Id: Ief3a70d08770e77120efa52f214cc1d81e6ebe08 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977477 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Include-what-you-use scrubCaveh Jalali2021-06-2511-7/+33
| | | | | | | | | | | | | | | This updates the list of header files included by brya board files to match what is actually used. BRANCH=none BUG=b:192010784 TEST=buildall passes Change-Id: I18d143882babfd17935fbf0cf92f235842df17c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987159 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* bb_retimer: cleanup: Change the power handler func name & paramsVijay Hiremath2021-06-181-2/+2
| | | | | | | | | | | | | | Changed the power handler function name from bb_retimer_power_handle() to bb_retimer_power_enable() and on_off param to enable. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ifad4c71a5d76b4841ea369a991160e221c051ec5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973375 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* brya: Add 2 ADC Channels for P2 buildKo_Ko2021-06-162-9/+25
| | | | | | | | | | | | | | | | | | | | Add 2 ADC channels SENSOR_3_CHARGER and ADC_TEMP_SENSOR_4_WWAN, and change sensor 2 naming for adc and thermal params. BUG=b:181271666, b:183452273 BRANCH=none TEST=build ec.bin and flash ec after not affect boot. Signed-off-by: Ko_Ko <Ko_Ko@compal.corp-partner.google.com> Change-Id: Ib26c264532c52364dc21eeca59c0611001898a42 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905161 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ko Ko <ko_ko@compal.corp-partner.google.com> Tested-by: Ko Ko <ko_ko@compal.corp-partner.google.com> Tested-by: Owen Ou <owen_ou@compal.corp-partner.google.com> Commit-Queue: Owen Ou <owen_ou@compal.corp-partner.google.com> Auto-Submit: Owen Ou <owen_ou@compal.corp-partner.google.com>
* brya: Check burnside bridge RESET signal statusCaveh Jalali2021-06-121-0/+14
| | | | | | | | | | | | | | | | | | This adds a level check of the burnside bridge reset signal GPIO. The signal is connected to a GPIO on the nct3808 which becomes uncontrollable when a debug accessory is connected and forces the BB into reset. We can check for this case by reading back the level of the GPIO and return an error when the desired signal level has not been achieved. BRANCH=none BUG=b:181743576,b:188826559 TEST=buildall passes, PD still works on brya Change-Id: Ia21cbc699f857542600cc5946868e9c58cfa6cf9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2955608 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* bb_retimer: Return status from bb_retimer_power_handle()Caveh Jalali2021-06-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | This allows the implementation of bb_retimer_power_handle() to return a status value indicating whether the request was successful. The default implementation simply controls a GPIO and is expected to succeed unconditionally. More complex implementations may run into failure cases that leave the BB unreachable. When this happens, device initialization returns an error so the caller can take mitigating action. USB MUX operations tend to be called from timing sensitive code paths in the TCPM, so careful error handling helps avoid cascading problems like PD negotiation failures. BRANCH=none BUG=b:181743576,b:188826559 TEST=buildall passes, PD still works on brya Change-Id: If79078be26e47d758e2cd6cc385ff2b34fecff63 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954198 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Implement board_is_dts_portCaveh Jalali2021-06-111-0/+5
| | | | | | | | | | | | | | | | | Brya only has one DTS (CCD) port. We do not want debug accessory support enabled on non-CCD ports as that can have undesirable side-effects. In particular, with debug accessory support enabled on the nct38xx TCPC, some of its GPIOs revert to their primary function in the presence of a debug accessory resulting in undesirable system behavior. BRANCH=none BUG=b:188851792 TEST=brya only reports "Debug accessory detected" on C0 Change-Id: I1cfaf9b51df8e6783db0215fbc6f3cac9e2dd9f1 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954197 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Enable AP-driven alt mode entryPrashant Malani2021-06-041-0/+1
| | | | | | | | | | | | | | | | Wait for the AP to direc the EC to enter USB Type C alternate modes. BUG=b:189263450 TEST=Manually verify that both Godzilla Creek and Dell WD19TB docks enumerate correctly on brya. BRANCH=main Change-Id: I0ea029769c9c33eb6af8fb7a5163b7c4466b3968 Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2937107 Reviewed-by: Abhijeet Rao <abhijeet.rao@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* brya: LED comments improvementBoris Mittelberg2021-06-021-2/+6
| | | | | | | | | | | | | | Fix typo, add functional description BRANCH=none BUG=b:182329831 TEST=none (changed comments only) Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ie36b39291bd0111412fea3b5d3bf963517cf1da3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932418 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* brya: Limit IMVP9 tuning to board ID 1Caveh Jalali2021-05-271-0/+3
| | | | | | | | | | | | | | | | We introduced tuning values for the IMVP9 PMIC for board ID 1 to improve stability. More recent boards should have the desired values pre-programmed, so we do not need to apply tuning parameters. BRANCH=none BUG=b:188945301,b:185275955 TEST=boots on board ID 1 Change-Id: I9b6967a43f6d5c8b37bc3a7344347c278bdf698a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922002 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Set hibernate wake sources polarityCaveh Jalali2021-05-271-5/+6
| | | | | | | | | | | | | | | | | This sets the wake source polarity on GPIOs we use as wake sources. LID_OPEN and ACOK are active high while the GSC_EC_PWR_BTN_ODL is active low. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1 Change-Id: I13fded03bbe3f40ed9699f6e8c32e7532c87bc41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921292 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* brya: Board ID 1: Handle BATT_PRES reassignmentCaveh Jalali2021-05-272-6/+27
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the battery presence detect GPIO has moved to the previous keyboard backlight enable pin. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1, check battery present status on ID_1_EC_BATT_PRES_ODL. Cq-Depend: chromium:2914207 Change-Id: Ibae2a5e1f43c83360535e0d60c2a343bf9ef2421 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2916413
* brya: Board ID 1: Handle TCPC_RST reassignmentCaveh Jalali2021-05-273-3/+43
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the TCPC C0/C2 reset GPIO has moved to a previously unused pin. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified TCPC C0/C2 can be reset on board ID 1 using ID_1_USB_C0_C2_TCPC_RST_ODL. Change-Id: I52d8044ed10379346ae36d4f5d6cbe7446867182 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914209 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 1: Handle KB_BL_EN reassignmentCaveh Jalali2021-05-272-2/+26
| | | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the keyboard backlight enable GPIO has moved to a previously unused pin and its polarity is inverted. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified keyboard backlight function with "kblight" EC console command Change-Id: I86a1b09c9aaab8f6275a65cd1331f135b152f538 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914208 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 2: Update generated-gpio.inc from spreadsheetCaveh Jalali2021-05-271-6/+6
| | | | | | | | | | | | | | | This updates the byra GPIO definitions to match the board ID 2 schematics. BRANCH=none BUG=b:183452273 TEST=booted on board ID 1 with following patches Change-Id: I55f1f926f7adbd113c8e8a4dcdff9ec2ae667ab6 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914207 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Revert "brya: reduce TCPC debug level to unblock testing"Boris Mittelberg2021-05-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7275ced0eadbf0adfe307f2e3c49f830e488f89a. Reason for revert: PD State names are required for FAFT to work Original change's description: > brya: reduce TCPC debug level to unblock testing > > Important EC log messages are getting overlapped by TCPC/PD messages. The > default level is now set to 0. > > BRANCH=none > BUG=b:186707521 > TEST=running FAFT PD with `pd dump 0` works > > Signed-off-by: Boris Mittelberg <bmbm@google.com> > Change-Id: Ia3415c878e49bae01460f5e2acb6b8ce736b9986 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904553 > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: caveh jalali <caveh@chromium.org> Bug: b:186707521 Change-Id: Ied5f926f87d75917295e36b4f6bd70fd6318d7d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920799 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* brya: Board ID 1: Set GPIO PCHHOT as inputCaveh Jalali2021-05-261-1/+1
| | | | | | | | | | | | | | | This fixes the definition of the PCHHOT GPIO to be an input on the EC side. This signal can be used to monitor the PCH status. Updated the GPIO spreadsheet for board ID 1 and regenerated file. BRANCH=none BUG=b:184811017 TEST=boots on brya board ID 1 Change-Id: Idde5ef2e95c1690833532eb598c257a001499f4d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2918476 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* brya: Skip mp2964 tuning on expected AP global resetCaveh Jalali2021-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | Due to CSE lite boot behavior, the AP goes through an additional global reset. This shows up as a transition back down to S5 on the EC. CHIPSET_SHUTDOWN and CHIPSET_STARTUP hooks are executed when this happens, so we need to remember that we've been here before and only run mp2964 update the first time through. BRANCH=none BUG=b:185424011 TEST=verified mp2964 tuning only runs once using EC console logs Change-Id: I08007dfa62bf842c51e4f6474322302409f4256c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911509 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Boris Mittelberg <bmbm@google.com> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
* brya: board ID 2: Move RT_RST to different pinCaveh Jalali2021-05-222-12/+16
| | | | | | | | | | | | | | | Brya board ID 2 moves the USB_C0_RT_RST_ODL pin from GPIO02 to GPIO07 of the nct3808. BRANCH=none BUG=b:188826559 TEST=still able to read BB registers using EC console Change-Id: I82875230ea7c2ecaedfbd4a1672031b81a4bd022 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912056 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Move battery_hw_present to boardCaveh Jalali2021-05-211-0/+8
| | | | | | | | | | | | | | | | This moves the battery_hw_present() function from the baseboard to the board file. We have a GPIO shuffle in the works for brya that requires board specific knowledge to support multiple revisions of the board. BRANCH=none BUG=b:183452273 TEST=battery works fine on brya ID 1 Change-Id: Ida698911539486cc68f509efd8533325b59e031e Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912055 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Add lid_open interrupt annotationCaveh Jalali2021-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This updates the GPIOD2 (the lid open interrupt) pin alternate mode declaration to include the interrupt declaration. This is done for consistency by the gpio.inc generator; there is no functional change as the GPIO_INT() declaration already sets the interrupt mode. Note: The reason the existing declaration works is because the npcx support code treats interrupt flags as additive w.r.t. the GPIO(...) declaration. Other flags are not additive and must be specified a 2nd time. Best practice is to always specify the complete set of config flags. BRANCH=none BUG=b:185322560 TEST=visual inspection Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I29c5ed44479dfcc732d01d46ccab5ed1ecaa314b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912054 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: reduce TCPC debug level to unblock testingBoris Mittelberg2021-05-191-0/+3
| | | | | | | | | | | | | | | Important EC log messages are getting overlapped by TCPC/PD messages. The default level is now set to 0. BRANCH=none BUG=b:186707521 TEST=running FAFT PD with `pd dump 0` works Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia3415c878e49bae01460f5e2acb6b8ce736b9986 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904553 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* brya: Set I2C4 to 400KHzCaveh Jalali2021-05-131-1/+1
| | | | | | | | | | | | | | | This drops the I2C4 speed to 400KHz as board rev. 1 does not meet I2C timing requirements for 1MHz. BRANCH=none BUG=b:186921875,b:187764571 TEST=PD still works on C1 Change-Id: I333708682f63af3293938b07cbf5a562d7065e4d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2885729 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Set I2C6 to 400KHzCaveh Jalali2021-05-131-1/+1
| | | | | | | | | | | | | | | This drops the I2C6 speed to 400KHz as board rev. 1 does not meet I2C timing requirements for 1MHz. BRANCH=none BUG=b:187549899,b:187764202 TEST=PD still works on C1 Change-Id: I3da75c561350d4f59bbd63f77d291eb40c1c37c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2885728 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
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