summaryrefslogtreecommitdiff
path: root/board/cheza/board.c
Commit message (Collapse)AuthorAgeFilesLines
* Drop some obsolete boardsJack Rosenthal2021-08-051-707/+0
| | | | | | | | | | | | | | | | | | | | | samus: AUE in M91, M92 pushed to stable already samus_pd: samus pd chip dragonegg: canceled cheza: canceled flapjack_scp: flapjack was canceled atlas_ish: atlas shipped, but ish project canceled sklrvp,glkrvp: these are pretty old intel reference boards and the portage overlays were already deleted ... assume nobody needs the EC firmware anymore either BUG=none BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I794867ac82f37ffa2267e2e59ac02bc381688c57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069716 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-141-3/+3
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* TCPM: Add OCP moduleDiana Z2020-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | Currently, the overcurrent protection is tracked in the PPC code. However, as different chips are able to report overcurrent move this code into a generic module. Logic for not sourcing Vbus or Vconn on latched ports moves into the TC layer, and an overridable board overcurrent function is provided for boards which have no special actions to take. BRANCH=None BUG=b:171501161 TEST=make -j buildall; TCPMv2 tested with following drawcia patch Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I75919e345a5b0bce4a0b67432a13515e7716cf6a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2532676 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Charger: Add dynamic charger chip countDiana Z2020-07-111-2/+0
| | | | | | | | | | | | | | | | Different DB options may cause different numbers of charger chips to be present on the system. Remove constant count for charger chips, and instead always call into the overridable function to query the count. BRANCH=None BUG=b:155963446 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0e65b8af351ecabe6f7b823e0e56f1932cc280a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2277833 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Swap system_jumped_to_this_image with system_jumped_latestabilize-quickfix-13310.91.B-masterstabilize-quickfix-13310.76.B-masterstabilize-quickfix-13310.73.B-masterstabilize-13310.99.B-masterstabilize-13310.94.B-masterstabilize-13310.83.B-masterstabilize-13310.74.B-masterstabilize-13310.72.B-masterrelease-R85-13310.B-masterDaisuke Nojiri2020-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | EFS2 boards need to call system_jumped_late in HOOK_INIT to avoid running init code twice per boot. system_jumped_to_this_image and system_jumped_late are functionally equivalent for non EFS2 boards. This patch will prevent system_jumped_to_this_image from being used for EFS2 boards when code is copied from a past project. BUG=chromium:1072743 BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I73fb5cedc5325d1c80825f9346954013046ee1df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2267685 Reviewed-by: Keith Short <keithshort@chromium.org>
* driver: Replace BMI160 to BMI in board configChing-Kang Yen2020-04-231-6/+6
| | | | | | | | | | | | | | | | | Replace some macro of BMI160 to BMI version for common function of BMI series. Make board config include the accelgyro_bmi_common.h instead of accel_gyro_bmi160.h. BRANCH=None BUG=b:146144827 TEST=make buildall -j Change-Id: I043ff8a92f15295ead3fa5c1e292319e2b4fa21a Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2156525 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* usb_mux: retimer: mux as chained mux and retimerDenis Brockus2020-02-281-24/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes retimers appear as generic muxes. By allowing a chain of muxes they can be stacked up to the new configurations that zork requires and will continue to work as they did before on configurations that only have a single mux. The code used to have two different arrays, 1) muxes and 2) retimers. On one of the zork configurations the processor MUX stopped being the primary mux and the retimer took its place. In a different configuration of that same platform it left the primary and secondary alone but the mux_set FLIP operation had to be ignored. Since the same interfaces needed to be available for both it stopped making sense to have two different structures and two different methods of handling them. This consolodates the two into one. The platforms that do not have retimers, this change will not make any difference. For platforms like zork, it will remove the retimers and make them chained muxes. So testing on trembyle makes sense to verify, BUG=b:147593660 BRANCH=none TEST=verify USB still works on trembyle Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Charger: Convert boards to use new driver structureDiana Z2020-02-041-0/+11
| | | | | | | | | | | | | | | This commit removes the temporary common charger chip configuration and instead puts the configuration in each board. BRANCH=none BUG=b:147672225 TEST=builds, runs on waddledoo and octopus Change-Id: If81aef31e48c65999a87e202494f286716114bbb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board: Set Accelerometer range to 4gGwendal Grignou2019-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Required by Android CDD - Section 7.3.1 - Paragraph C.1.4 Modified mechanically with: for i in $(grep -lr "\.default_range" board); do sed -i '/.default_range =/s#\(.*\.default_range = \).* /\ \* g.*#\14, /* g, to meet CDD 7.3.1/C-1-4 reqs */#' $i done Manually reworked to only change the accelerometer that matters to android: The lid accelerometer or the base accelerometer if the base also hosts the gyroscope. This is only for future EC, no need to land the change on branches: mems_setup will take care to set accelerometer ranges at 4g on startup. BUG=b:144004449 BRANCH=none TEST=compile Change-Id: If8c14b2e928c9c70c0ce51451adcfcd674a9e73b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957375 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-011-6/+6
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-6/+6
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-4/+17
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-04-171-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* cheza: Add ALS sensorAlexandru M Stan2019-02-201-0/+27
| | | | | | | | | | | | | | | | Added definitions for the OPT3001 sensor on our board. TEST=In S0, "> accelread 2" should yield an illuminance number on the "Last calib." line. Shine a light near the camera to modify the value. TEST=On the AP console: localhost /sys/bus/iio/devices/iio:device4 # watch -n 0.1 cat in_illuminance_input BUG=b/112658076 BRANCH=master Change-Id: I0c4890c83c889429b4908821d6157f3809308d7f Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1460092 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Fix the port argument of overcurrent eventWai-Hong Tam2019-01-261-1/+1
| | | | | | | | | | | | | | The port should be 1. BRANCH=none BUG=b:120231371 TEST=Made port-1 overcurrent and checked the interrupt triggered and the message showed. Change-Id: Ib66bae7582003df5e2f797ef9eceaa9b0ad530ca Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1437399 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* USB PD: PPC: Add overcurrent handling.Aseda Aboagye2019-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Type-C Power Path Controllers provide overcurrent protection. This commit adds support into the USB PD task for overcurrent events while we are in source role. The USB PD 3.0 spec recommends that ports issue a hard reset when an overcurrent condition occurs on a port. Additionally, we'll allow a source port to overcurrent 3 times before latching off VBUS from the port entirely. The source path will be re-enabled after ~1s after each overcurrent event. BUG=b:69935262,b:114680657 BRANCH=None TEST=Boot to ChromeOS in grabbiter. No overcurrent events reported when the sink is drawing <= 3.20 A. Overcurrent events are reported when the sink is drawing > 3.25 A. After 3 reports, the port is latched off and power delivery is stopped. The port is re-enabled only after the sink is disconnected. Also when the sink is drawing current at 3.24 A, there is one report of overcurrent. The port gets disabled in response to that event. But the port is re-enabled after 1 second since overcurrent event is reported only once. After the port is re-enabled, the sink is able to draw the set current. When the overcurrent event is reported, I can see in the kernel logs that the overcurrent condition is detected by the kernel. EC Logs: [3391.984462 C1: PPC detected Vbus overcurrent!] [3391.984953 C1: overcurrent!] [3392.044935 C1: PPC detected Vbus overcurrent!] [3392.045425 C1: overcurrent!] [3392.061404 C1: PPC detected Vbus overcurrent!] [3392.061894 C1: overcurrent!] [3392.062142 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.077226 C1: PPC detected Vbus overcurrent!] [3392.077532 C1: overcurrent!] [3392.077891 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.092660 C1: PPC detected Vbus overcurrent!] [3392.092966 C1: overcurrent!] [3392.093213 C1: OC event limit reached! Source path disabled until physical disconnect.] Kernel Logs: [ 3356.560456] usb usb2-port1: over-current condition [ 3356.768434] usb usb2-port2: over-current condition [ 3356.976446] usb usb2-port4: over-current condition [ 3357.184441] usb usb2-port5: over-current condition [ 3357.392445] usb usb2-port6: over-current condition Change-Id: Ib070f261e98264cd88725ebce7d10e0798267e3b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1286300 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/807633 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cheza: Add the interrupt of port-1 overcurrentWai-Hong Tam2019-01-111-3/+19
| | | | | | | | | | | | | | | | Add the interrupt of port-1 overcurrent. It just calls the common board-specific overcurrent event handler. The implementation of the handler is still a TODO. BRANCH=none BUG=b:120231371 TEST=Checked the interrupt triggered on over-current. Change-Id: I5cfc3b57bedb9e80711eb75a5039e01e6e83799b Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1361682 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Disable pull-up on USB_C1_OC_ODL in S5Wai-Hong Tam2018-12-121-0/+17
| | | | | | | | | | | | | | | In S5, we disable the 5V, so the overcurrent detection is not needed. Disabling its pull-up prevents any current leak. BRANCH=none BUG=b:118342484 TEST=Checked the GPIO flag in S0 and S5. Can't verify on real hardware due to the wrong GPIO pin. Change-Id: Ib9a0c7abdc7bae820cbfa92f9c7a7e704079e077 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1370891 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Make chipset_reset do a warm resetWai-Hong Tam2018-12-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the chipset_reset function do a warm reset to match the expectation of what AP-initiated reset does, which is also a warm reset but triggered by PS_HOLD. The warm reset is done by sending a low pulse to the PMIC RESIN_L pin, which requires PMIC registers being reprogrammed that makes it as a warm reset trigger. If the PMIC registers not reprogrammed properly, it falls back to do a cold reset power sequence. It is done by EC monitoring the AP_RST_L signal, which is already one of the power signals. BRANCH=none BUG=b:117941911 TEST=Typed "apreset" just after "reboot" (PMIC registers not programmed), checked the transition S0 -> S5 -> S0. TEST=Typed "apreset" when AP booted into userspace (PMIC registers programmed), checked a warm reset happened, AP_RST_L toggled. Change-Id: Ia1c5c7a8fd56a9e4867d4dd4c8bf2333c083c616 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1330117 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Make USB mux handled by TCPC chips and HPD handled by APWai-Hong Tam2018-11-071-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Cheza design, the USB mux (switching USB lanes to DP and/or USB SS) is handled by TCPC chips and the HPD is handled by AP (DP PHY). The CL adds some custom drivers to override the get() function (Linux extcon driver uses it to check the USB mux and HPD IRQ) by checking the virtual driver and redirect the other functions to the TCPC drivers. BRANCH=none BUG=b:118898133 TEST=Manually added a new console command to issue a HPD IRQ. +static int command_hpd_irq(int argc, char **argv) +{ + char *e; + int port; + const struct usb_mux *mux; + + if (argc != 2) + return EC_ERROR_PARAM_COUNT; + + port = strtoi(argv[1], &e, 10); + if (*e || port >= CONFIG_USB_PD_PORT_COUNT) + return EC_ERROR_PARAM1; + + mux = &usb_muxes[port]; + mux->hpd_update(port, 0, 1); + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(hpd_irq, command_hpd_irq, + "[port]", + "Issue a HPD IRQ"); In EC console, typed "hpd_irq 0" and checked the result on AP: localhost ~ # ectool usbpdmuxinfo 0 Port 0: USB DP HPD_IRQ Port 1: USB INV Checked it again and HPD_IRQ should be cleared. localhost ~ # ectool usbpdmuxinfo 0 Port 0: USB DP Port 1: USB INV Change-Id: I4ddc274a637393391dd654c9ee75de7646746ad5 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1316370 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Correct the PSYS ADC multiplierWai-Hong Tam2018-11-021-3/+3
| | | | | | | | | | | | | | | | | | | The resistor on the PSYS output is actually 5.6K Ohm, instead of 12.4K Ohm. Correct the ADC multiplier to reflect the impedance value. The worst-case anaylsis: ADC multipler: 2816 * 124000 * 2 / (1023 + 1) = 682000 max ADC register value: 1023 (10-bit) upper bound: 1023 * 682000 < 2^30 BRANCH=none BUG=b:118343126 TEST=Checked the "adc" console command. Change-Id: I6c96c60f08c6f50b53fd69d3aa0ee8f86c069545 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1309049 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Monitor the WARM_RESET_L signal to hold APWai-Hong Tam2018-10-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is a backup solution if JTAG_SRST gets fused out. The WARM_RESET_L signal is wired to JTAG_SRST, such that we can hold AP when servo/H1 programs the AP SPI flash. But when JTAG_SRST gets fused out (just in case it happens), still have a way to hold AP, i.e. overdriving the AP_RST_L and PS_HOLD signals. The WARM_RESET_L signal is pulled by a rail from PMIC, the same as POWER_GOOD. The drop of WARM_RESET_L may be caused by either servo/ cr50 holds the signal or its pull-up rail drops. We should handle both cases. Also add WARM_RESET_L as one of the power signals for debug purpose. BRANCH=none BUG=b:78194018, b:112723105, b:112564635 TEST=Ran "dut-control warm_reset:on" and "dut-control warm_reset:off". Scoped the signal of AP_RST_L and PS_HOLD to verify the correctness. Verified AP hold and back booting up. TEST=Changed to the gpio.inc to swap LID_OPEN and WARM_RESET_L and ran "dut-control lid_open:no" and "dut-control lid_open:yes" to emualte the case JTAG_SRST gets fused out. Scoped the signal correctness. Verified AP hold and back booting up. Ran flashrom to program AP SPI flash through servo. Change-Id: I71ebd920171da9994192f7742675feb7cb39ce2f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1234743
* cheza: start using higher priority taskJett Rink2018-10-171-4/+14
| | | | | | | | | | | | | | | The last step to convert cheze over to using a higher priority USB-PD interrupt is to update the interrupt handler BRANCH=none BUG=b:117498337 TEST=verified that HARD RST goes away after Source_Cap Change-Id: Ibb4afec382845e6505425778473c795909a3c9b1 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1283240 Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Reenable EC hibernateWai-Hong Tam2018-10-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | This CL requires hardware rework or a new hardware revision, which * blocks the current drop to VCC1_RST pin; * makes the lid open and power button signals pulled-up by the EC standby rail. BRANCH=none BUG=b:79348203 TEST=Typed "hibernate" command on EC console and checked waking EC up using the 4 wake sources: * dut-control lid_open:no sleep:0.2 lid_open:yes * Unplug and plug the AC charger * dut-control pwr_button:press sleep:0.2 pwr_button:release * dut-control cold_reset:on sleep:0.2 cold_reset:off Change-Id: Iccc33e3df621da319d422942eda1ec9f01a4fd67 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123157 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-2/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* type: Rename matrix_3x3_t to mat33_fp_tYilun Lin2018-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming of many vector types and matrix types are not clear enough. For example, we have: vector_3_t, which is a vector of three int. vec3_t, which is a vector of three float. size4_t, which is a vector of four size_t. mat33_t, which is a 3x3 matrix of float. matrix_3x3_t, which is a 3x3 matrix of fixed point. Besides, we have types like int8_t, uint16_t types. To clearly distinguished types, the CL propose to, For vector types, naming should be `$type + 'v' + $num + '_t'`: vector_3_t becomes intv3_t vec3_t becomes floatv3_t vector 4 of uint16_t becomes uint16v4_t (which doesn't exist yet) For matrix types, naming should be `mat$N$N_` + $type + '_t', where $N is the matrix size: matrix_3x3_t becomes mat33_fp_t # fp: fixed point mat33_t becomes mat33_float_t TEST=make buildall -j BUG=b:114662791 Change-Id: I51d88d44252184e4b7b3564236833b0b892edc39 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1215449 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Measure VBUS by ADCstabilize-atlas-11022.BPhilip Chen2018-08-311-0/+8
| | | | | | | | | | | | | | | | BRANCH=none BUG=b:112441618 TEST=manually test adc command on a reworked rev2 board: (1)When a Type-C charger is plugged, VBUS is measured ~5000mV. (2)When a 15V PD charger is plugged, VBUS is measured ~15000mV. (3)When no charger is plgged, VBUS drops to ~0mV. Change-Id: I0340d1e4428260e6898eccdac930a9d96d9836bd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1196847 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Disable interrupts which are floating when switchcap offWai-Hong Tam2018-08-311-4/+12
| | | | | | | | | | | | | | | | The power signals, AP_RST_L and PMIC_FAULT_L, are floating when switchcap off. Disable their interrupts. The PS_HOLD and POWER_GOOD should be OK as they have pull-down. BRANCH=none BUG=b:78455067 TEST=Checked "power on", "power off", "apshutdown", and "apreset". Change-Id: I17e4c7e8f82e950b52d750961f4b5efc01c18ccf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180066 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Use POWER_GOOD signal instead of AP_RST_LWai-Hong Tam2018-08-311-14/+0
| | | | | | | | | | | | | | | | | | | | | | | The AP_RST_L is not a good signal to indicate power good. For an AP initiated warm reset (the Qualcomm way), AP pulls down PS_HOLD for a short pulse, and then PMIC pulls down AP_RST_L for another short pulse. This short pulse confuses EC from a power-lost. We use a confirmation logic to differentiate this case as a workaround. This CL uses another signal POWER_GOOD, which is SRC_PP1800_S4A from PMIC, as an indicator. CQ-DEPEND=CL:1169952 BRANCH=none BUG=b:78455067 TEST=Checked "power on", "power off", "apshutdown", and "apreset". Verifed the power-off sequence: * if the PMIC registers not programmed, it forces off switchcap. * if the PMIC registers programmed, it does graceful PMIC shutdown. Change-Id: I847eef5d4202485b70354b3f65ce24cd1ccb7ece Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1169953 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Add more power signals for informative purposeWai-Hong Tam2018-08-291-1/+8
| | | | | | | | | | | | | | | | | | | | | | | No power sequence logic is chanaged. Add PS_HOLD, PMIC_FAULT_L, and POWER_GOOD (the real one, not AP_RST_L) as power signals. If their states change, the EC console will show it and the timestamp. BRANCH=none BUG=b:78455067 TEST=Ran "gpioset SWITCHCAP_ON_L 0" and showed the signals changed: 7 signal changes: 750.164712 +0.000000 AP_RST_L => 0 750.164810 +0.000098 PMIC_FAULT_L => 0 750.165312 +0.000502 PS_HOLD => 0 750.166565 +0.001253 POWER_GOOD => 0 750.206345 +0.039780 PMIC_FAULT_L => 1 751.190869 +0.984524 PMIC_FAULT_L => 0 751.233388 +0.042519 PMIC_FAULT_L => 1 Change-Id: I1237f4fff20e2256f504d3c9d11ed26da5224ecd Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1169951 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Configure ANX3429 interrupt as open-drainWai-Hong Tam2018-08-231-1/+1
| | | | | | | | | | | | | | | | | This interrupt pin by default is a push-pull. It causes leak to EC VSPI power during EC watchdog reset. As in our design, we use this interrupt pin as open-drain. Should configure the register to make it open-drain. BRANCH=none BUG=b:112906111 TEST=Flashed the EC image to Cheza rev-2 board. Typed "reboot" command and then EC reset properly. Change-Id: Iee5db3cb5b5291778d97dee4fc70369d34344ce7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1185871 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Don't need to set the switchcap register on initWai-Hong Tam2018-08-171-10/+0
| | | | | | | | | | | | | | The switchcap register should be OTP'ed. BRANCH=none BUG=b:77957956 TEST=On the rev-2 board, power cycle the board, check the switchcap register having a proper value. Change-Id: I558301772404618a1d189a567ea61e743f403e84 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179975 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Don't report TCPC alert status if TCPC chip in resetWai-Hong Tam2018-08-101-2/+4
| | | | | | | | | | | | | | | | | | | | | The PD host command task regularly checks the TCPC chip to see any alert status. If it happens, EC will talk to the TCPC chip. But if the TCPC chip in reset, like during boot-up init hook or in low power mode (for the port-0 TCPC chip), should not report the alert status. Some other CrOS devices do the same thing. BRANCH=none BUG=b:111403605 TEST=Unplugged the charger and powered only by batter, plugged some USB device to port-0, cold reset the board, didn't see the repeated messages of [TCPC p0 Low Power Mode]. Change-Id: Idcc57baef692be34852e665cdad0bc2051cd9e5e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1167985 Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Enable display backlight controlWai-Hong Tam2018-08-061-0/+17
| | | | | | | | | | | | | | | | | | The display backlight is turned OFF in S3 and ON in S0. The display backlight state also depends on the lid state, i.e. closing lid will trigger display backlight OFF. BRANCH=none BUG=b:74395451 TEST=Run "dut-control lid_open:no" trigger backlight OFF. Run "dut-control lid_open:yes" to trigger backlight ON. Power off the AP to trigger backlight OFF. Change-Id: I23d72a80d74ae5fc29612010be165e7e99c58649 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1161016 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Fix triggering PPC interruptWai-Hong Tam2018-08-031-3/+2
| | | | | | | | | | | | | Cheza only has PPC on port-0. Passing only 0 to the interrupt handler. BRANCH=none BUG=b:74395451 TEST=Plug a charger to port-0; it charges. Change-Id: I2d8e33ade5e34cf6da901582fdb08181115cbc28 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1161214 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* cheza: Remove the switchcap hackWai-Hong Tam2018-07-261-10/+0
| | | | | | | | | | | | | Don't need it as the switchcap has been OTP'ed. BRANCH=none BUG=b:77957956 TEST=On the rev-1 board, power-on and power-off work. Change-Id: I318e658b34d2ebdd8cd169bc5690aa1edd669008 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1080998 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Enable PWM for display backlightWai-Hong Tam2018-07-261-0/+9
| | | | | | | | | | | BRANCH=none BUG=b:79548010, b:78599945 TEST=On the rev-1 board, connects as a panel, the display works. Change-Id: If5a85e0a173bc51d63b32d92cf734ac40e57cbfc Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1080997 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Change the I2C buses of BC 1.2 chipsWai-Hong Tam2018-07-261-3/+4
| | | | | | | | | | | | | | | Reflect the rev-1 hardware. Speed-up the TCPC port-1 I2C bus to 1M Hz. The TCPC port-0 I2C bus keeps as 400k Hz initially. BRANCH=none BUG=b:78304996 TEST=Verified on the rev-1 board, i2cscan shows the BC 1.2 chips, plugging charger to port-1 work as expected. Change-Id: I9c26df5eb6a914477a41ff1b3ee72efce5ead2dd Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1080996 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Enable ADC channelsWai-Hong Tam2018-07-261-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Enable the ADC channel 0 (base detection), channel 2 AMON/BMON, and channel 3 PSYS. BRANCH=none BUG=b:79548010 TEST=Checked the following EC commands: > adc BASE_DET = 2813 AMON_BMON = 152 PSYS = 1546875 > amonbmon AMON(Charging): 2902 uV, 145 mA AMON(Discharging): 152 uV, 7 mA BMON(Charging): 458 uV, 22 mA BMON(Discharging): 152 uV, 15 mA > psys PSYS = 1701562 uW Change-Id: Ib4c198865a2b01e0e0d71027c3296c56cf49d88e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1150816 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Don't defer the VBUS detection interrupt handlerWai-Hong Tam2018-06-211-14/+2
| | | | | | | | | | | | | | | | | | | The VBUS detection interrupt handler was moved to the deferred context because some check requires I2C communication. Now the check result is cached locally and doesn't need any I2C communication, per the fix: https://chromium-review.googlesource.com/1086115 So the interrupt handler should not be deferred. BRANCH=none BUG=b:74395451 TEST=Plug charger to P0 and/or P1, check the state change correctly. TEST=Plug device to P0 and/or P1, check sourcing VBUS correctly. Change-Id: I3ee762b5f1c9a00037da510df83b593c45a4e95a Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1108740 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cheza: Support accel/gyroPhilip Chen2018-06-151-0/+61
| | | | | | | | | | | | | | BUG=b:110006188 BRANCH=none TEST=Move/rotate cheza rev1 board, and 'accelread' shows different readings Change-Id: Iec89e800df9722f5bb53d91c3178dd99d30e5d4c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1090693 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* Cheza: Support host command over SPIWai-Hong Tam2018-05-261-0/+1
| | | | | | | | | | | | | BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran "ectool version" in userspace. Change-Id: Iee6816c669a18d1203b9f8f88857418185645503 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1005554 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Add stubs and ifdefs to fix testsNicolas Boichat2018-05-261-0/+2
| | | | | | | | | | | | BRANCH=none BUG=none TEST=make BOARD=cheza tests -j Change-Id: Ifec4653bf71b870b616669f0a32ba528c1e38787 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072217 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ppc: making driver non-constJett Rink2018-05-241-2/+2
| | | | | | | | | | | | | | | We need to update the driver based on the runtime board id, so we need to remove the const attribute. BRANCH=none BUG=b:78896495,b:78021059 TEST=build all -j Change-Id: I5f751c33cf4ec68a38aeb8644170df4987c87d7b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068030 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cheza: Check power enough and enable PP5000 when power-on APWai-Hong Tam2018-05-221-8/+0
| | | | | | | | | | | | | | | | | | | | | | | Remove the previous hack of force increasing the adapter current. The PP5000 rail is now turned on/off during power-on/off AP. Add a check to ensure it has enough power to enable the 5V rail and boot AP. If the battery is in low level or unplugged and the charger adapter doesn't supply enough power, don't boot AP and transition back to S5. The check may wait a while for PD negoiation. BRANCH=none BUG=b:79353631 TEST=On battery plugged and unplugged cases, checked the device can source VBUS to USB port-0 and port-1. TEST=Unplug battery and use a low-power adapter, can't boot up AP. See the "Not enough power to boot" message and transition to S5. Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050607
* cheza: Disable EC hibernate temporarilyWai-Hong Tam2018-05-141-8/+0
| | | | | | | | | | | | | | EC can't be waked up once it enters hibernate. Need to figure out the cause. Disable it temporarily in order not to block others. BRANCH=none BUG=b:79348203 TEST=Ran "help" on console and not "hibernate" command. Change-Id: Ifba2b95df26b03e4389616ebb3fc217bb5a24d54 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050748 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Remove BC1.2 switch hackTom Wai-Hong Tam2018-05-091-14/+0
| | | | | | | | | | | | | | | | | | | | | | PD is enabled so don't need it. BRANCH=none BUG=b:74395451 TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests: * Verified USB boot * Plugged adapter to port-0/port-1/both and saw charging * Plugged USB device to port-0/port-1/both and saw sourcing VBUS * Plugged adapter to one port and USB device to another port * Plugged USB disk to port-0 and booted into kernel * When AP off, not sourcing VBUS to USB device * Rebooting AP still works Change-Id: Ib878960fb302d85549735a395f75cc8d045d45f2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1042621 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Support PD and chargingTom Wai-Hong Tam2018-05-091-0/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port 0: TCPC: ANX3429 PPC: SN5S330 BC1.2: PI3USB9281 Port 1: TCPC: PS8751 Power switch (sink): NX5P3290 Power switch (source): NX20P5090 BC1.2: PI3USB9281 Charger: ISL9238 BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests: * Plugged adapter to port-0/port-1/both and saw charging * Plugged USB device to port-0/port-1/both and saw sourcing VBUS * Plugged adapter to one port and USB device to another port * Plugged USB disk to port-0 and booted into kernel * When AP off, not sourcing VBUS to USB device * Rebooting AP still works Change-Id: Icde5e24c2cda3d0f2046486528a210af84befcca Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/969701 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
View Lorry Controller Status