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* cheza: Enable MKBP keyboard protocolWai-Hong Tam2018-07-171-0/+1
| | | | | | | | | | | | | | This is used for passing button information from EC to AP. BRANCH=None BUG=b:74395451 TEST=make buildall -j Change-Id: I8a4ee99fb699f484dcc71fe4c0c6a7fd05a94ffb Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1138731 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* cheza: Don't defer the VBUS detection interrupt handlerWai-Hong Tam2018-06-211-14/+2
| | | | | | | | | | | | | | | | | | | The VBUS detection interrupt handler was moved to the deferred context because some check requires I2C communication. Now the check result is cached locally and doesn't need any I2C communication, per the fix: https://chromium-review.googlesource.com/1086115 So the interrupt handler should not be deferred. BRANCH=none BUG=b:74395451 TEST=Plug charger to P0 and/or P1, check the state change correctly. TEST=Plug device to P0 and/or P1, check sourcing VBUS correctly. Change-Id: I3ee762b5f1c9a00037da510df83b593c45a4e95a Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1108740 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cheza: Fix USB peripheral mode when using a Type-C to std-A male cableWai-Hong Tam2018-06-181-1/+0
| | | | | | | | | | | | | | | | | | | | In the PD state machine, the decision is that if the data is DFP, then connect the mux, but if the data role is UFP, then disconnect the mux. To make the Type-C to std-A male cable work, the UFP should also connect, need to disable the CONFIG_USBC_SS_MUX_DFP_ONLY. BRANCH=none BUG=b:110265762 TEST=Used an image enabling USB peripheral mode and USB gadget zero, typed EC command to mux the port-1 HS to AP, plugged a Type-C to std-A male cable, the host side can enumerate the gadget zero device and the dmesg log shows the detection too. Change-Id: I532e53bd0832c50a86a91d1c8d84fd55af543eca Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1102985 Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Support accel/gyroPhilip Chen2018-06-154-1/+79
| | | | | | | | | | | | | | BUG=b:110006188 BRANCH=none TEST=Move/rotate cheza rev1 board, and 'accelread' shows different readings Change-Id: Iec89e800df9722f5bb53d91c3178dd99d30e5d4c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1090693 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Read board version from GPIO pinsPhilip Chen2018-06-071-1/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST='version' command on ec console shows correct board version Change-Id: If52b3424f754cf470042909767eaff48a9b5483a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1090370 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Switch USB port-0 HS to the hubWai-Hong Tam2018-06-011-2/+2
| | | | | | | | | | | | | | It matches the SS path, in which both port-0 and port-1 connect to the hub. BRANCH=none BUG=b:74395451 TEST=Tried plugging USB 2.0 disk to port-0 and port-1, both bootable. Change-Id: Ic0264657fbe126242a419ef33ce07bc2599375ee Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1082981 Reviewed-by: Douglas Anderson <dianders@chromium.org>
* Cheza: Support host command over SPIWai-Hong Tam2018-05-263-1/+8
| | | | | | | | | | | | | BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran "ectool version" in userspace. Change-Id: Iee6816c669a18d1203b9f8f88857418185645503 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1005554 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Add stubs and ifdefs to fix testsNicolas Boichat2018-05-261-0/+2
| | | | | | | | | | | | BRANCH=none BUG=none TEST=make BOARD=cheza tests -j Change-Id: Ifec4653bf71b870b616669f0a32ba528c1e38787 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072217 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ppc: making driver non-constJett Rink2018-05-241-2/+2
| | | | | | | | | | | | | | | We need to update the driver based on the runtime board id, so we need to remove the const attribute. BRANCH=none BUG=b:78896495,b:78021059 TEST=build all -j Change-Id: I5f751c33cf4ec68a38aeb8644170df4987c87d7b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068030 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cheza: Enable LED supportWai-Hong Tam2018-05-223-1/+165
| | | | | | | | | | | | | | | | It is copied from the Lux board, as the rev-0 hardware uses the same design as Lux. The LED doesn't work if AP is in G5, as the LED power source PP5000 is disabled in G5. Will fix it later. BRANCH=none BUG=b:74395451 TEST=Tested several scenarios: charge, low-level battery, charge but no battery. Change-Id: I3803b917c6c4cba35176b75cb316b2c8ef9eb13a Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1060582 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Check power enough and enable PP5000 when power-on APWai-Hong Tam2018-05-223-15/+3
| | | | | | | | | | | | | | | | | | | | | | | Remove the previous hack of force increasing the adapter current. The PP5000 rail is now turned on/off during power-on/off AP. Add a check to ensure it has enough power to enable the 5V rail and boot AP. If the battery is in low level or unplugged and the charger adapter doesn't supply enough power, don't boot AP and transition back to S5. The check may wait a while for PD negoiation. BRANCH=none BUG=b:79353631 TEST=On battery plugged and unplugged cases, checked the device can source VBUS to USB port-0 and port-1. TEST=Unplug battery and use a low-power adapter, can't boot up AP. See the "Not enough power to boot" message and transition to S5. Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050607
* cheza: Disable EC hibernate temporarilyWai-Hong Tam2018-05-142-10/+2
| | | | | | | | | | | | | | EC can't be waked up once it enters hibernate. Need to figure out the cause. Disable it temporarily in order not to block others. BRANCH=none BUG=b:79348203 TEST=Ran "help" on console and not "hibernate" command. Change-Id: Ifba2b95df26b03e4389616ebb3fc217bb5a24d54 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050748 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Remove BC1.2 switch hackTom Wai-Hong Tam2018-05-091-14/+0
| | | | | | | | | | | | | | | | | | | | | | PD is enabled so don't need it. BRANCH=none BUG=b:74395451 TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests: * Verified USB boot * Plugged adapter to port-0/port-1/both and saw charging * Plugged USB device to port-0/port-1/both and saw sourcing VBUS * Plugged adapter to one port and USB device to another port * Plugged USB disk to port-0 and booted into kernel * When AP off, not sourcing VBUS to USB device * Rebooting AP still works Change-Id: Ib878960fb302d85549735a395f75cc8d045d45f2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1042621 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Support PD and chargingTom Wai-Hong Tam2018-05-097-12/+876
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port 0: TCPC: ANX3429 PPC: SN5S330 BC1.2: PI3USB9281 Port 1: TCPC: PS8751 Power switch (sink): NX5P3290 Power switch (source): NX20P5090 BC1.2: PI3USB9281 Charger: ISL9238 BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests: * Plugged adapter to port-0/port-1/both and saw charging * Plugged USB device to port-0/port-1/both and saw sourcing VBUS * Plugged adapter to one port and USB device to another port * Plugged USB disk to port-0 and booted into kernel * When AP off, not sourcing VBUS to USB device * Rebooting AP still works Change-Id: Icde5e24c2cda3d0f2046486528a210af84befcca Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/969701 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Change ACOK_OD pin to EC inputTom Wai-Hong Tam2018-05-081-5/+5
| | | | | | | | | | | | | | | | | | | | The ACOK_OD is a required signal of the charging state machine. EC can't always hold it low; however, it breaks the charging state. Make it back to EC input. There are some side-efforts, mentioned in the bug. BRANCH=none BUG=b:78035750 TEST=Plugged/unplugged AC when AP is on/off. TEST=Verified the power sequence still works. Change-Id: I039af9cdb86cfb509f2580e6f57d82309825dac1 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1042620 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Lower the I2C bus speed of smart batteryTom Wai-Hong Tam2018-05-081-1/+1
| | | | | | | | | | | | | | | The I2C speed of the smart battery is 100KHz. Lower the bus speed. BRANCH=none BUG=b:74395451 TEST=Used console command "i2cscan" to check the smart battery. Change-Id: I3f5f1e7ac1707ba416036214afa2ff46dad7f174 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1040874 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Remove internal pull-up for the BATT_PRES_ODL pinTom Wai-Hong Tam2018-05-081-1/+1
| | | | | | | | | | | | | | | There is an external pull-up for the BATT_PRES_ODL signal. BRANCH=none BUG=b:74395451 TEST=Verified the BATT_PRES_ODL value when battery plugged or not. Change-Id: Ief10820290c204cd0a965081165df9f64ce1bb34 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1035450 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Support confirmation of power lostTom Wai-Hong Tam2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | Keep the timestamp of the latest power lost. Add a handler to wake the chipset task to check if power lost stays low for a while (the time between now and the latest power lost is longer than a period). BRANCH=none BUG=b:78455067 TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset sequence and verified AP reset but not a transition S0 -> S5. TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse (see power_off function) to execute PMIC shutdown sequence and verified a power-lost transition S0 -> S5. Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028831 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Enable AP_RST_REQ as a request from AP to reset itselfWai-Hong Tam2018-05-082-1/+2
| | | | | | | | | | | | | | | | | | | | | | | This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising edge interrupts to trigger a hook to call chipset_reset(). As the hook task will be preempted by the chipset task, it adds a flag bypass_power_lost_trigger to avoid triggering to S5 as the chipset state machines sees power lost during the reset. So far the chipset_reset() implementation is to do a cold reset; will be revised to a warm reset after the PMIC registers are reprogrammed. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran 'reboot' on AP console which toggles the GPIO. Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1023986 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Make sure switchcap is configured rightAlexandru M Stan2018-05-042-0/+12
| | | | | | | | | | | | | | | | | | Configure switchcap every time we're about to change the signal, just in case it forgot. Feel free to revert this after b/77957956 is fixed. BRANCH=none BUG=b:77957956 TEST="i2cxfer r 0 0xd0 0x2" never shows 0x70, even after a bad brownout (like "gpioset EN_PP5000_A 1" on an unreworked board) Change-Id: I8994cd402ce96d8bf4e436dadfc0e572e7f77a85 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024501 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Add SDM845 power sequence for rev-0 boardWai-Hong Tam2018-05-044-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the power sequence for rev-0 board. Confirmed the behavior of reprogramming the PMIC registers to enable the instant reset and shutdown. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control pwr_button:press sleep:0.2 pwr_button:release Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0 * Console command: power off Result: S0 -> S5 -> G3 * Console command: power on Result: G3 -> S0 * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969702
* npcx: change chip variants of npcx7 series for better clarification.Mulin Chao2018-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w to npcx7m7wb for better clafiication since it introduced new parameter "b" for chip generation in the same family series. In new npcx7 series naming rule, it follows: Format: NPCX7(M)(N)(G/K/F)(B/C) param M: 8: 128-pins package, 9: 144-pins package param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size param G/K/F/W: Google EC depends on specific features. param B/C: Chip generation in npcx7. (Generation A is ignored. It follows nameing rule in npcx5.) The all chip variants of npcx7 used in boards are also listed below: npcx7m6g - for npcx7 ec without internal flash on npcx_evb. npcx7m6f - for npcx7 ec with internal flash. npcx7m6fb - for npcx7 ec with internal flash, enhanced features. npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV. BRANCH=none BUG=none TEST=No build errors for npcx7 series. Change-Id: I896ee33209efa5d7157c90515005db5f36318c76 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1025471 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Increase charger current to maxAlexandru M Stan2018-04-261-0/+7
| | | | | | | | | | | | | | | | 1.5A is really too low for our bringup tests, increase it to max until we have a battery driver. BRANCH=none BUG=b/74395451 TEST="gpioset EN_PP5000_A 1" should not brownout the system TEST=Backlight can turn on TEST=Kernel boots and is stable for swboyd Change-Id: I789b18304c36f6f68296796c076699af722cb5d6 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024502 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Lower the I2C speeds on TCPC buses to 400kHzWai-Hong Tam2018-04-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial I2C operating speed of the port-0 TCPC chip is 400kHz. It requires changing a register addr:0x48 to a value 0x03 to increase its speed to 1MHz. The BC1.2 chips on port-0 and port-1 also operate at 400kHz, according to the datasheet. So lower the I2C speeds on two TCPC buses to 400kHz. BRANCH=none BUG=b:78142256 TEST=Use console to enable TPCP power and check I2C communication: > gpioset EN_USB_C0_TCPC_PWR 1 > gpioset USB_C0_PD_RST_R_L 1 > i2cscan 1 Scanning 1 tcpc0...................................... 0x4a... 0x50........................ 0x80............................................................... > i2cxfer r 1 0x50 0x00 0xaa [170] Change-Id: I665136d738de50db8beeed338e3102fb5ca6fc84 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1015763 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Add initial support for ChezaWai-Hong Tam2018-04-175-0/+311
Add initial support, like UART, GPIO, I2C, buttons, etc. Add some hacks for early bring-up. BRANCH=none BUG=b:74395451 TEST=BOARD=cheza make TEST=Flashed the EC image to cheza. Verified AP power-on, booting coreboot/depthcharge with UART, and then booting kernel from USB. Change-Id: Id057abb491553bbffd3c57a6f48187ac2f2ff9a6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/969420 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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