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* gpio: change A1 pinmux flag to DIO_INPUT instead of GPIO_INPUTMary Ruthven2022-03-011-1/+1
| | | | | | | | | | | | | | | | | The DIOA1 PINMUX definition uses a GPIO flag instead of a DIO flag. It doesn't matter that much, because GPIO_INPUT maps to DIO_DIRECT_INPUT which is a noop. i2cp_set_pinmux configures the DIOA1 input in existing images. This change just modifies the flag for correctness. BUG=b:221090807 TEST=check pinmux output on spi and i2c boards. Verify it doesn't change. Change-Id: I227156e5799d872da32a87a7bcab4ae638c18c08 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3495872 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: return the time since user_pres was assertedMary Ruthven2022-03-011-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a vendor command that returns the time since user_pres_l was asserted. This is only used for testing. Tracking user_pres_l needs to be enabled with a vendor command since DIOM4 may not be pulled up and may be pulled down on old boards. Enabling the vendor command survives deep sleep reset. It gets cleared after cr50 reset. Cr50 clears the user_pres_l status if tracking is disabled. BUG=b:219981194,b:208504127 TEST=manual # Verify it survives deep sleep sudo gsctool -y enable sudo gsctool -y ... user pres enabled # enter deep sleep sudo gsctool -y ... user pres enabled # Verify it doesn't survive cr50 reboot sudo gsctool -y enable sudo gsctool -y ... user pres enabled cr50 > reboot sudo gsctool -y ... user pres disabled # Check gsctool output after triggering DIOM4 pulse sudo gsctool -y enable # Trigger pulse and wait 5 seconds sudo gsctool -y ... user pres enabled last press: 5064331 Change-Id: Ib37980a5cd8d3378bf718e8e32a7d4152435a816 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3495863 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* coil: cleanup commentsstabilize-rust-13720.B-cr50_stabMary Ruthven2021-01-111-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: Icbd143b072fdd5df3b67d7e5a09ee6c01a77f6b9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622889 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: rename spi_master to spi_controllerMary Ruthven2021-01-101-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: If7b5829294a3d4d8a68042f1a8d449e8e6ef158e Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615124 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: CONFIG_SPI_MASTER->CONFIG_SPI_CONTROLLERMary Ruthven2021-01-101-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I244ca864dad04f2b4f02bb1be2b482921da2fc88 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615123 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: sps->sppMary Ruthven2021-01-101-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: Ia34cccffdd6a82c25b479bb8d2e6370bbf00baf0 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615121 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: CONFIG_SPS->CONFIG_SPPMary Ruthven2021-01-101-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I79a65f8475e2a764720a1f37a147c3723d34b046 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615120 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: cleanup i2c commentsMary Ruthven2021-01-081-7/+7
| | | | | | | | | | | | Remove coil terms from i2c comments BUG=b:175244613 TEST=make buildall -j Change-Id: If056c099304e1fa676991e22ddaa9cb91ccfdeb3 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613509 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: i2cm->i2ccMary Ruthven2021-01-071-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I5318e7845c7b87a21b1fa9f5e99629513b7fbb80 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613504 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: rename I2CS gpiosMary Ruthven2021-01-071-12/+12
| | | | | | | | | | | | | We can't change the register names at this point. We can only change the gpios. This changes the gpio names. BUG=b:175244613 TEST=make buildall -j Change-Id: I0dadd84bbb3d19011e86428b79d0cb08321c35e3 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611762 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: i2cs -> i2cpMary Ruthven2021-01-071-2/+2
| | | | | | | | | | | | | | | | | Rename i2cs functionas and variables to i2cp. Change some basic comments. I will rework the i2cp comments to stop using controller when referring to the i2cp, because it's kind of confusing now that master has been renamed to controller. BUG=b:175244613 TEST=make buildall -j Change-Id: I9574e77ab42427ca90d5b8a6421793f52e519f67 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611761 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* apply INT_AP_L extension on I2CS interfaceNamyoon Woo2020-05-291-6/+9
| | | | | | | | | | | | | | | | This patch applies INT_AP_L extension on I2CS. It uses GPIO_MONITOR_I2CS_SDA to detect a transaction start during INT_AP_L assertion and to deassert INT_AP_L. BUG=b:148691139 TEST=None Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iedd59b488dfdfaaf71dd71eda6437f1a9402d3c4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2150517 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* cr50: Provision DIOM4 as inputVadim Bendebury2020-02-271-0/+10
| | | | | | | | | | | | | | | | | This will allow using this pin a physical presence indicator on certain platforms. BRANCH=cr50,cr50-mp BUG=b:144455668 TEST=tried the new image on the red board, observed DIOM4 level changing when shorting it to ground. Change-Id: I7c20b094d73d49321921c5afa67e0db9825ea82f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076499 Reviewed-by: Yicheng Li <yichengli@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* make DIOB3 interruptible and wakable for EC-EFS2Namyoon Woo2020-02-081-0/+11
| | | | | | | | | | | | | | | | | | | | | If the board supports EC-CR50 communication, Cr50 enables both rising/falling-edge triggered interrupt on DIOB3 pin and makes it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4. If the board does not support EC-CR50 communication, Cr50 connects GPIO_AP_FLASH_SELECT to DIOB3. If EC puts high on DIOB3 to activate EC-CR50 communication, CR50 enables UART_EC RX and TX. BUG=chromium:1035706 BRANCH=cr50 TEST=none Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add support for using a strap pin as a ccd gpioMary Ruthven2020-01-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a mechanism which allows to use one of board strap pins as the CCD gpio and makes DIOA9 the CCD pin on boards with strap os 0xE. This change uses 2 bits from the board properties to determine which pin is used as the ccd gpio. 0 - no ccd gpio 1 - DIOA1 2 - DIOA9 3 - DIOA12 DIOA6 is another strap pin, but there's only one valid strap with a 5kPU left, so I decided not to use another board property bit to support it as a possible ccd gpio. I want to save the board property bit, since we're running out of them and there are so many other I2C straps boards can use. We can add it later if we need to. BUG=b:147812066 BRANCH=cr50 TEST=manual. Use pinmux and gpiocfg to verify the output is only enabled when the gpio is asserted. no added brdproperties - nothing is different with pinmux run on Puff gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button pressed gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button released add BOARD_CCD_REC_LID_PIN_DIOA1 to SPI board pinmux output adds DIOA1 27 IN GPIO1_GPIO10 GPIO1_GPIO10 24 DIOA1 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA9 to SPI board pinmux output adds DIOA9 27 IN GPIO1_GPIO10 GPIO1_GPIO10 16 DIOA9 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA12 to I2C board pinmux output adds DIOA12 27 IN GPIO1_GPIO10 GPIO1_GPIO10 13 DIOA12 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output Change-Id: If74385135a572e7e5d0763fad9f5368fdec8d7a0 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006210 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* add BOARD_EC_CR50_COMM_SUPPORT to board propertiesNamyoon Woo2020-01-141-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL add a board property indicating EC-CR50 communication support. The target boards are Volteer,Dedede,Puff, and Zork. It shall be detected if the H1 strap configuration value is either 0x0E or 0xE0. BUG=b:146567516, chromium:1027660 BRANCH=cr50 TEST=Flashed AP firmware through CCD on Grunt, Octopus, Scarlet and Atlas. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:2 a6:0 a12:0 [0.005886 Valid strap: 0xa properties: 0x41] > brdprop properties = 0x1141 > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600b8: DIOB3 3 IN GPIO0_GPIO2 400600c0: DIOB4 0 IN PD ... 40060100: GPIO0_GPIO2 7 DIOB3 ... 40060120: GPIO0_GPIO10 6 DIOB4 Flashed AP firmware on a reworked board with 1M ohm on DIOA1 and 5k ohm on DIOA9. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005886 Valid strap: 0xe properties: 0x200041] > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600c0: DIOB4 3 IN PD GPIO0_GPIO2 ... 40060100: GPIO0_GPIO2 6 DIOB4 ... 40060120: GPIO0_GPIO10 6 DIOB4 Change-Id: If60765190a385a0e728177911b1ec738c6a00d99 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979612 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: correct the comment on ENTERING_RW in gpio.incNamyoon Woo2019-10-071-2/+5
| | | | | | | | | | | | | | | | The previous comments were not correct. ENTERING_RW is not a GPIO at H1. The reason of marking it unimplemented in gpio.inc is to avoid the compile error from cros FW common module. BUG=None BRANCH=cr50 TEST=make buildall. Change-Id: Ieecbc9128e4071accbe4408d41ec51cefb68cffc Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1842031 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* g: allow I2CS operate without hardware resetsVadim Bendebury2019-09-051-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not always possible to rely on PMU for resetting the I2CS controller. Most of the AP firmware versions deploy the 'I2C unwedge' cycle when coming out of reset, but not all of them, this is why Cr50 needs to be able to recover on its own in case there was a crash and the I2C bus was left mid transaction with the H1 holding down the SDA line. A GPIO is dedicated to monitor the I2CS_SDA line during reset. If the line is kept low, it could be a sign of a 'wedged' controller. The g I2CS FSM will reset any time the I2C 'stop' condition is detected. The create the 'stop' condition the I2C_SCL input is disconnected from the bus and connected to an internal GPIO, then I2C_SCL level is set to 'high' and register inverting the I2C_SDA value is toggled, which looks like a transition from zero to one to the controller. thus creating the 'stop' condition. BRANCH=cr50, cr50-mp BUG=b:135772657 TEST=the test was ran on a Pyro device, which uses I2C for communication with H1 and which AP firmware does not deploy the 'I2C unwedge' cycle. Test instrumentation involved setting a Chrome OS startup file such that once booted, the AP starts continuously polling TPM for value of an NVMEM index, creating I2C traffic. The host workstation sends the 'apreset cold' command to the EC within a few seconds of Chrome OS coming up. First run a special Cr50 image which is not resetting I2CS using PMU on TPM restarts, is was not trying to unwedge the stuck I2C bus. On five experiments, it takes on average 32 reboots for until I2C bus is locked up and the DUT falls into recovery. Then loaded the Cr50 image with this patch and ran the test again, it survived for 150 cycles without a problem. Change-Id: Iffec33f97557e3acfd1cd5fb76ba158f8c23b608 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730143 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add gpio assignments descriptionVadim Bendebury2019-08-021-0/+29
| | | | | | | | | | | | | | | | | This is a documentation only change which adds a table showing how internal GPIOs of the g chip are used on Cr50. Adding this table will make it easier to keep track of the GPIOs when adding new use cases. BRANCH=cr50, cr50-mp BUG=none TEST=make buildall Change-Id: I1e573bdc4b9628aae17c7ba976ba1554ee1050e6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730142 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: make sys_rst_l_out pseudo open drainMary Ruthven2019-04-051-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | The existing SYS_RST_L implementation enables the output on SYS_RST_L before setting the level to 0, which results in cr50 briefly driving SYS_RST_L high when SYS_RST_L is asserted. This patch switches SYS_RST_L to a pseudo open drain mode, which eliminates the pulse. The internal pull up on SYS_RST_L is not being removed, so the H1 will still pull this line up when SYS_RST_L output is set to 1. Removing the pull up will require careful analysis of existing designs, and if safe will be done in a different patch. BUG=b:117676461 BRANCH=cr50 TEST=assert/deassert sys_rst_l and check that 'sysrst' shows the correct state. Verify this works on cheza which only pulls SYS_RST_L up to 1.8V even though VDDIOM is 3.3V. Change-Id: I50c9569e70c97cec434df3095f1b109f3248076b Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1282020 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: make ccd_mode_l pseudo open drainMary Ruthven2019-04-041-8/+3
| | | | | | | | | | | | | | | | | | gpio.c has support for making pins open drain. This implementation will prevent the signals from being driven high. Use the gpio.c support instead of the hack we were using before. BUG=none BRANCH=cr50 TEST=the EC can assert CCD_MODE_L when cr50 has it deasserted. Verify this on a ARM and x86 device in the lab. Change-Id: I7f2a465782f2c60a850c25153fb65eb96fff0712 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1282019 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use interrupts for ap_stateMary Ruthven2019-03-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ap_state machine as is is pretty hard to modify as it's implemented now. The state machine has to have certain states set at certain points to handle AP detection properly and it is very slow to detect AP off. It takes a second and it will only detect AP off if TPM_RST_L stays asserted for 1 second. This change modifies ap_state.c to use interrupts instead of polling, so it can detect when the AP is off immediately and wont miss any resets. This is required for the new closed loop reset feature. Cr50 has to be able to detect all AP resets and it can't take 1 second for cr50 to determine the AP is off. We used polling because we had to use APTX_CR50RX to detect AP state for a while. The UART level changes a lot. Processing all of the interrupts really impacted CCD uart, so we couldn't use interrupts to detect the state. We had to poll. AP UART isn't used to detect AP state anymore on any platforms, so it's ok to switch to interrupts now. APTX_CR50RX is still used for ap uart detection in ap_uart_state.c. This change doesn't modify that at all. BUG=b:123544145 BRANCH=cr50 TEST=Make sure suspend and reboot stress tests still work on a bob and a soraka. Check that Cr50 detects the AP state correctly. Change-Id: I80eb97aecffe460b7857e66e7204a55b72c9dd47 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1446999 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: rename ap and ec detect gpiosMary Ruthven2019-02-011-4/+4
| | | | | | | | | | | | | | | | | These gpios are detecting ap and ec uart. Rename them to reflect that. We are adding another interrupt for ap state detection. Rename the uart gpios, so it is a little less confusing. BUG=none BRANCH=cr50 TEST=none Change-Id: I11c8c4465845540e9cda603ddb98c91a8022912b Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1446998 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: change EC_TX_CR50_RX gpioMary Ruthven2019-02-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | The interrupt gpios are all grouped at the top of gpio.inc. They start using PIN(1, 0) and use the next pin as interrupts are added. EC_TX_CR50_RX used to be a standard interrupt, but we stopped using the interrupt handler in chip/g/gpio.c and started using a dedicated interrupt for this signal, so we could do uart bitbang faster. This change moves EC_TX_CR50_RX, so we can keep the standard we were using for interrupt definitions. It moves EC_TX_CR50_RX to PIN(1, 11,) because that's the highest unused pin. We should be able to continue counting up for interrupt definitions and counting down for other gpio definitions. BUG=none BRANCH=cr50 TEST=use uart bitbang to program nocturne. Change-Id: I46c1b296db57d774203ba097cc82722f31388d0b Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1443870 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add more obvious sections in gpio.incMary Ruthven2019-01-311-1/+11
| | | | | | | | | | | | | | | | Change the comments so it's more obvious what the sections are in gpio.inc BUG=none BRANCH=none TEST=none Change-Id: I11566aa1748519df8cdc3cf9269e2a0c90c2dad9 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1443869 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Changes to support closed source EC factory modeKeith Short2019-01-081-0/+12
| | | | | | | | | | | | | | | Drives OEM specific GPIOs to enable and disable factory mode to a closed source EC. BUG=b:118683718 BRANCH=none TEST=make buildall. Verified GPIO states with scope in both factory mode enable and disable conditions. Verified GPIO states are reapplied correctly after reboot, deep sleep, and power cycle. Change-Id: I9bc547504478fded5f95c515027e1da0f245d524 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1358733 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: speed up bit bang EC programmingVadim Bendebury2018-08-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original bit bang programming implementation attempted to provide a fully functional alternative UART interface for the case when EC programming is required, so that proper UART parity can be ensured. Come to think of it, this is not really necessary: - EC programming over UART does not require full duplex. - when EC is being programmed, the AP is held in reset, there is no need to support AP console or TPM at that time, as a result interrupts could be disabled for somewhat longer intervals. This patch introduces the following modifications: - remove uartn interface redirections - when bitbang mode is enabled regular EC console is not available. - instead of waiting for fixed amount of cycles on every bit, wait for the deadline calculated when character transmission started on tx side or when the original start bit was detected on rx side and recalculated after each clock. - when finishing receiving a character do not exit ISR right away, spin for a duration of a character polling the rx line, in case the EC keeps transmitting. The rx buffer is allocated on the ISR stack and is limited to 20 bytes, which would probably cause an overrun if this interface were used for reading flash contents from the EC. - connect USB EC console flow directly to the bit bang driver when bit bang mode is enabled and disable interrupts from the EC UART. - do not use the GPIO wrappers for bit bang interrupt processing - it takes too long. - when starting a bit bang session set the clock timer value to zero, this allows not to worry about wraparound, which will happen in almost 3 minutes, programming session should not take this long. - for the duration of 'bit bang enabled' state servo detection interrupt is disabled, it gets re-enabled after bit bang mode is disabled and servo_detect() gets to run on 1s hook. - it is not enough to check the DIOB5 pinmux state to tell if EC UART is connected or not, as this pin could be connected in bit bang mode as well; always report EC TX UART as disconnected when bit bang mode is enabled. - for the duration of bit bang programming session suppress 'aggregate' GPIO interrupts, triggered per port when GPIO interrupt is asserted. Additional speed up could be achieved if gpio driver wrappers were replaced with direct register accesses, but even as presented this patch allows to reliably program the STM32 on Scarlet at 57600 baud, which is 6 times faster than the current state. BRANCH=cr50, cr50-mp BUG=b:62539385 TEST=with some flash_ec modifications which make sure that bit bang mode is enabled properly (fixing timing of setting boot0 and resetting the EC), Scarlet device EC can be reprogrammed at 57600 baud 100 times in a row with and without logic analyzer connected to the EC UART pins. Change-Id: I2e3520f158943323cb015fa18650a7e177f03cc3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1171221 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50:usb_spi: add Cheza EC supportMary Ruthven2018-04-101-4/+11
| | | | | | | | | | | | | | | | | | | The Cheza EC requires EC_RX_H1_TX be held low while the EC is being reset to enter gang mode. This change adds another programming mode to ec usb spi programming to do that. BUG=b:74388083 BRANCH=cr50 TEST=The cheza boards aren't in, so I just tested EC_TX_CR50_RX_OUT gpioset EC_TX_OUT 0 and 1 setup EC_TX_CR50_RX_OUT correctly as an output when asserted and an input when deasserted. Change-Id: I7fc9cba954f2af5a841f00ce5bf8a27251b33bbe Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1003529 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: create ap_uart state machineMary Ruthven2018-02-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This change creates a state machine to handle ap uart detection. It removes all of the ap_uart stuff from ap_state.c and moves it to ap_uart_state.c. All boards will now use ap_uart to enable/disable ap uart and tpm_rst_l to detect the ap state. Separate ap uart detection from ap detection, so we can disable the ap uart without enabling deep sleep. If the ap is in S3 on ARM devices, Cr50 wont be in deep sleep, but the AP UART RX signal wont be pulled up. In this case we need cr50 ap rx to be disabled and deep sleep to be disabled. BUG=b:35647982 BRANCH=cr50 TEST=run firmware_Cr50DeviceState on scalet and electro Change-Id: I81336a9e232df8d44b325eef59327a1c06a80cba Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/884307 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Split servo state machine into its own fileRandall Spangler2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the last state machine which used common/device_state.c. But servo is more complex than that, because it needs to differentiate state-isn't-known (debouncing) from state-isn't-knowable (Cr50 driving EC TX), so it's cleaner to split it out the way we did AP and EC state machines in previous CLs. BUG=b:35587387 BRANCH=cr50 TEST=manual with CR50_DEV=1 build // Test detect at boot, even with CCD connected Pull CCD_MODE_L low Pull DETECT_SERVO high Pull DETECT_EC high reboot -> 'Servo connect' // CCD is not driving EC UART TX ccd -> EC on, Servo connected, CCD enabled, EC UART RX // When servo disconnects CCD can drive EC TX Pull DETECT_SERVO low --> 'Servo disconnect' ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX // Can't detect servo reconnecting if we're driving EC TX Pull DETECT_SERVO high --> (no change) ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX // When we stop driving EC TX, can redetect servo Pull EC_DETECT low --> See 'EC off', 'Servo connected' ccd -> EC off, Servo connected, CCD enabled, EC UART disabled // Test debouncing at boot Pull DETECT_EC high Pull DETECT_SERVO low Pull CCD_MODE_L high reboot Within 1 sec, pull DETECT_SERVO high --> 'Servo connected' // Test debouncing after boot Pull DETECT_SERVO low then high < 1 sec --> (no message) Change-Id: I964bd36c35f52c8ef7b3ea3793b6e0764e93587c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/636047 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Split AP state machine into its own fileRandall Spangler2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the AP state machine out, the way we split out the EC state machine in the previous CL. BUG=b:35587387 BRANCH=cr50 TEST=manual, with Cr50 strapped (or hard-coded) not to use platform reset and not to use TPM reset to detect the AP: Pull CCD_MODE_L low, so Cr50 detects/enables CCD Pull AP_DETECT high. Pull INT_AP_L low (with resistor). Pull AP_DETECT low --> See 'AP off' message gpioget --> INT_AP_L=0 ccd --> AP UART disabled Pull AP_DETECT high --> See 'AP on' message gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Pull AP_DETECT low for <1 sec then back high (don't see AP off/on message) gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Reboot with AP_DETECT still low -> AP off at 1 second Reboot with AP_DETECT still low and then assert AP_DETECT within a second -> AP on immediately Repeat with Cr50 strapped/hard coded to use platform reset, but using TPM_RST_L instead of AP_DETECT. Note that this will also show TPM reset debugging output when TPM_RST_L is asserted. Change-Id: Ief9e4e5f2585ff925de1595cc8fbd5306c94a806 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/634248 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Split EC state machine into its own fileRandall Spangler2017-08-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the EC state machine out, the way we split out BattPrsnt and CCD_MODE. BUG=b:35587387 BRANCH=cr50 TEST=manual Pull CCD_MODE_L high, so Cr50 detects/enables CCD Pull EC_DETECT high. reboot -> 'EC RX only', then 'EC on' at 1 second Pull EC_DETECT low --> See 'EC off' message ccd --> EC UART disabled Pull EC_DETECT high --> See 'EC on' message ccd --> EC UART RX+TX Pull EC_DETECT low for <1 sec then back high (don't see EC off/on messages) ccd --> EC UART RX+TX Reboot with EC_DETECT still low -> EC off at 1 second Reboot with EC_DETECT still low and then assert EC_DETECT within a second -> EC RX only, then EC connect at 1 second. Change-Id: I71687e651d625cadd656934f4cb2bbadc0b58816 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619750 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Refactor Rdd state machineRandall Spangler2017-08-231-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to mirror Rdd detect into CCD_MODE_L and handle keepalive is now inside chip/g/rdd.c It uses a HOOK_SECOND state machine similar to what's coming for EC/AP/Servo. This also removes the explicit 'ccd enable' / 'ccd disable' commands, since they'd be overridden by the HOOK_SECOND handler. If you need to force CCD enabled, use 'ccd keepalive enable'. BUG=b:64799106 BRANCH=cr50 TEST=With a CR50_DEV=1 images: Disconnect CCD cable (pull RDCC1 and RDCC2 outside 0.2-2.0V) gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Connect CCD cable --> see 'Debug accessory connected' gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Briefly disconnect and reconnect CCD cable --> No debug output gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Disconnect CCD cable and wait a second --> 'disconnected' gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Force CCD_MODE_L = 0 externally, wait a second gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Stop forcing CCD_MODE_L externally, wait a second gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled ccd keepalive enable gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled ccd keepalive disable gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Change-Id: I65110b45e76f60390828e0fbbac8f36fc2cc9b37 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619393 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add 'recover hosed slave' i2cs capabilityVadim Bendebury2017-08-171-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A common failure condition on the i2c bus is when the master unexpectedly stops clocking the bus while the slave is driving the SDA line low. In this case the master is not able to issue Stop or Start sequences, which makes the bus unusable. Good slave controllers are able to detect this condition and recover from it by removing the pull down from the SDA line. This patch adds this capability to the g chip i2c slave controller. A new timer function is created which samples the SDA line twice a second. If it detects that SDA is low in two consecutive invocations and the number of i2cs read interrupts has not advanced, it decides that the "hosed slave" condition is happening and reinitializes the i2c driver, which removes the hold from the SDA line. Even though the state of the SDA line is supposed to be accessible through the I2CS_READVAL register, it in fact is not, reads always return zero in the SDA bit. To work around this a GPIO (port 0, bit 14) is being allocated to allow to monitor the state of the line, it is multiplexed to the same pin the SDA line uses. When the AP is in low power modes the SDA line is held low, this state should not trigger i2c reinitializations. CQ-DEPEND=CL:616300 BRANCH=none BUG=b:35648537 TEST=connected H1 on the test board to an I2c master capable of stopping clocking mid byte. Observed that the existing code would just sit in the "hosed" state indefinitely. The code with the fix recovers from the condition (drives the SDA line high) 500ms to 1s after the failure condition is created. Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/614391 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: add a pulldown to spi mosi and clkMary Ruthven2017-08-011-2/+2
| | | | | | | | | | | | | | | | Add a pulldown to spi mosi and clk pins. The floating signals are causing power issues with the spi buffer. This change adds pulldowns to prevent the issues. BUG=b:38509318 BRANCH=cr50 TEST=eve power drops to 2mW and reef power numbers are unchanged. Flash the EC and AP on both boards using ccd. Change-Id: I595920f461a67effcbdb52a4334683b6eca2b3b2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/595213 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: introduce means of detecting chip running in factory modeVadim Bendebury2017-07-301-0/+7
| | | | | | | | | | | | | | | | | | When installed in the factory test rig, the DIOB4 pin is set to high by the moment the RW section starts. Software behavior needs to change to comply with the factory test rig requirements. Define the GPIO and add a function to report the factory mode state. BRANCH=cr50 BUG=b:63686091 TEST=tested along with the rest of the stack of patches. Change-Id: I8c4158fc75138d717fc009496365c8e61b42a890 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579584 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cr50: Enable EC UART bit banging.Aseda Aboagye2017-06-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Cr50 needs to be able to bit bang the EC UART in order to flash certain ECs such as the STM32 family. This is because the UART block on the chip has no provision to change the parity which is necessary for the STM32 bootloader protocol. This commit adds a configuration to bit bang the EC UART. It's been tested at 9600 baud. BUG=b:35648297 BRANCH=cr50 TEST=With a logic analyzer, verify that TX to the EC can be bit banged with no issues at 9600. TEST=With some other changes, verify that cr50 is able to flash an EC image to an STM32 EC. Change-Id: Ice72aff133f268b5b7f0868aeec590a21404d1af Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/503474 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Only drive CCD_MODE_L when in CCD mode.Aseda Aboagye2017-03-071-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the behaviour of handling the CCD_MODE_L pin. When Cr50 is not in CCD mode, it will stop driving the pin and turn it into an input. This allows the pin to be driven by the EC. Cr50 will then poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD mode. Once the pin is deasserted, CCD mode is disabled. However, when Cr50 itself makes the decision to enter CCD mode, it changes the pin from an input to an output and drives the pin low. NOTE: The rdd interrupt does not directly trigger CCD mode, but now drives the pin low. A side-effect of the pin going low is that CCD is enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the pin to be setup as an input again. CQ-DEPEND=CL:448988 BUG=b:35804738 BRANCH=cr50 TEST=Flash dev board, use `ccd` console command to both enable and disable CCD. Verify that when CCD is enabled, the state of DIOM1 does not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low enables CCD. Letting it float disables CCD. TEST=Verify that CCD mode is reflected in the device state. Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/448161 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: rework sleep state and tpm reset triggersVadim Bendebury2017-02-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cr50 needs to be aware of the power state of the system and of the moment when the AP is reset, because this is when the TPM needs to be reset too. Arm and x86 platforms provide different hints in these cases. In case of x86 there is a single signal cr50 can rely on: PLT_RST_L. This active low signal is asserted when the system is going into any power state deeper than s0ix. The cr50 can fall into deep sleep when PLT_RST_L is asserted, and has to wake up and reset the TPM when this signal is deasserted. There could be other wake triggers, but the tpm should not be reset unless PLT_RST_L is inactive. It is also important not to fall into deep sleep when PLT_RST_L is pulsed to reboot the system. In case of ARM there are two separate signals. Deasserting SYS_RST_L signal is the trigger to reset the TPM, The GPIO_DETECT_AP going low for a duration of time is the indication of the AP going into some kind of sleep mode. The ARM case requires more clarification. This adds run time configuration of the the sleep state control input. Once the input turns low, the CHIPSET_SHUTDOWN signal is sent and deep sleep mode is enabled. Again, this will require adjustment for ARM platforms. The wake from deep sleep state is controlled by the wake pins as before, but by level instead of edge. This makes sure that in case the trigger for deep sleep goes away while deep sleep preparation is under way, the device resumes immediately instead of getting stuck missing the edge. The TPM_RST_ input is now triggering interrupts on deassertion - this is the moment when the TPM needs to be reset. The ISR is being renamed accordingly. The processing previously happening inside the ISR is being moved into a deferred function running on the hooks task context. There is no need to invoke TPM reset related functions from the PMU wake up ISR anymore. BRANCH=none BUG=chrome-os-partner:59007 TEST=as follows: 1. make buildall -j succeeds 2. started on Reef, still in progress after 100 iterations, early to call suspend_stress_test --suspend_min 40 --suspend_max 45 \ --wake_max 15 wake_min 10 (note that reef does not fall into s3 any more, so the test does not verify H1 deep sleep) 3. modified the target to fall into s3 during the test and successfully repeated it for 100 iterations 4. tried battery disconnect a few times and observe successful boot. Change-Id: Ica06ec0d363b53eede3be327404ff5807fa3a610 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/436865 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Implement reading all strapping pins for board configScott2017-01-241-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously only 1 pin DI0A1 was being read to distinguish between SPI/I2C configurations. This change adds code to support reading 4 strapping pins DIOA9|DIOA1 and DIOA12|DIOA6 and enabling the internal pullup/pulldown reistors to differentiate between weak and strong external pull up/dn restistors. An 8 bit strap config id is produced and then a config table is searched to match the config id with known configuraitons. The board properties to be used are read from the config table. BRANCH=none BUG=chrome-os-partner:59833 TEST=manual Modified the Cr50 dev board with 1M and 5k pullup/pulldown resistors and connected them to 4 GPIOs (defined as strapping pins). Tested the 12 possible external pullup/pulldown configurations and verified that the correct 5 bit value was produced for each configuration. Tested with both Reef and Gru. On Reef the strap config = 0x12 and on Gru it reads 0x2 as expected. Verfifed TPM was functional on both systems. Change-Id: I18c625a2b6b904bf4bcdaf2665ed9c3cbdafeb54 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421580 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: describe GPIO assignmentVadim Bendebury2017-01-191-0/+37
| | | | | | | | | | | | | | Just a clean up patch attempting to make it easier to new users to come up to speed with cr50 use of H1 GPIO subsystem. BRANCH=none BUG=none TEST=none Change-Id: I539e7629ee94ddef26ae1616dc6eb5c151e9d97e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/412412 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: use the correct reset signal for gru and reefMary Ruthven2017-01-181-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boards that have plt_rst_l had sys_rst_l currently use the two signals to detect resets and reset the TPM. That meant that the TPM could reset twice depending on the timing of those signals. On boards with plt_rst_l, we should really just use that to detect system resets and not sys_rst_l. On boards with plt_rst_l, sys_rst_l should only be used as an output to trigger warm resets. This change makes both boards use the gpio tpm_rst_l_in to detect AP resets. That gpio will be connected to a different pin depending on which board we are using. On Gru the gpio will be connected to diom0 which is sys_rst_l, and reef will use diom3 which is plt_rst_l. BUG=chrome-os-partner:61789 BRANCH=none TEST=manual Use cr50 servo to verify the contents of /var/cache survive reset after 'dut-control warm_reset:on sleep:0.5000 warm_reset:off' test on gru and reef verify that the system can boot to kernel run 'sysrst pulse' and check that you only see one system reset use 'pinmux' to verify the pins for the two types of boards are setup properly on reef diom0 is an input, diom3 is an input with wake_falling, and gpio1_gpio1 uses diom3 on gru check that diom0 is an input with wake_falling, diom3 is not configured, and gpio1_gpio1 uses diom0 Change-Id: I1f6e8bfa525ffa5585a18282b78014f36f0cfee6 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/428130 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: change uart rx to wake_lowMary Ruthven2016-12-081-1/+1
| | | | | | | | | | | | | | | | Having cr50 resume on the falling edge of its uart rx signal is causing some issues, and wake on low is good enough and works fine. This change switches uart rx from DIO_WAKE_FALLING to DIO_WAKE_LOW BUG=chrome-os-partner:60449 BRANCH=none TEST=cr50 can still resume on uart activity and plugging in the charger has no impact on cr50 remaining in deep sleep. Change-Id: If77126cb64cf2fa949a75d53bb40098f037a2aa4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/418335 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: I2CM: Enable i2c master for accessing INA chipsScott2016-10-111-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On both Reef and Gru there are INA (shunt bus voltage monitor) ICs connected to the Cr50 I2C master bus. The use case for these chips is in a lab setting using case closed debugging. Power to the INA chips is controlled by a separate Cr50 gpio signal. By default, the INAs are powered off and the I2C master bus is not connected. A function ina_connect() is provided which needs to be called prior to attempting to access the INAs via I2C. BRANCH=none BUG=chrome-os-partner:57059 TEST=manual Tested both Reef and Gru. Verified that console command 'ccd ina on|off' works as expected and that can repeatedly read registers on the INA using the following command "i2cxfer r16 0 0x40 0". Read 0x2771 [10097] which is the default value. In addition wrote register 14 (bits 15:1 are writeable) and verified the value was able to read the value back which was written. Change-Id: I670f7897555dae29642264531599dc4471c52bbd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/394168 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Add gpio input for platform reset (plt_rst_l)Scott2016-09-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | For TPM operation with Intel chipset APs, the signal PLT_RST_L needs to trigger a TPM reset. For current Reef boards, this signal is connected to DIOA13. The next version will have it on DIOM3. This CL adds support for platform reset connected on DIOA13 and uses a new board property so that it doesn't affect Kevin/Gru. BRANCH=none BUG=chrome-os-partner:55115 TEST=manual Used H1 dev board configured as Reef. Created high to low transisition on to verify that platform reset was detected. Tested on Kevin to ensure that resets were not occurring. Change-Id: I58f02b7ffa644a9197f4303ae6e640df181040bd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380336 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: make device state detect level triggeredMary Ruthven2016-09-211-3/+3
| | | | | | | | | | | | | | | | | The interrupts on all of the gpios detecting if the device is on were edge triggered. If the rising edge happened in between when the gpio level was read and when the interrupt was enabled, then the device state could be falsely detected as off for a short period of time. This change changes them to GPIO_INT_HIGH. BUG=none BRANCH=none TEST=buildall Change-Id: I9aa3cff14047cf4f6473c32f2cdc4724afca3414 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385164 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: remove unused detect_off interruptMary Ruthven2016-09-211-13/+6
| | | | | | | | | | | | | | | | The interrupts to detect when the falling edge on the UART signals are currently disabled and never reenabled. Power off is detected by polling and not through interrupts. This change removes all of those falling edge interrupts. BUG=none BRANCH=none TEST=cr50 can detect when the EC, AP, and Servo are off or on Change-Id: I0fd8a0d970f3235b26af6b90dd395ea7c75e0c17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385192 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: generate AP_INT_L pulse after i2cs processing finishedVadim Bendebury2016-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | The g i2c slave controller does not support clock stretching, so it is necessary to flow control the AP by some other means. Luckily there is an interrupt line which g can toggle and the AP can watch. This patch adds generating a pulse on the AP interrupt line once g finished processing the i2c transaction. In case of the read transaction the pulse is generated after the data to read is put in the i2cs transmit buffer. BRANCH=none BUG=chrome-os-partner:57338 TEST=with this patch and the AP firmware synchronizing on the interrupt pulse, the TPM initialization succeeds in coreboot and depthcharge. Change-Id: I16c09b59b7d772624baa9d1f5258aaff26f91ff9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385256 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: stop using the AP uart to detect servoMary Ruthven2016-09-131-10/+4
| | | | | | | | | | | | | | | | Now that the AP uart is enabled whenever the AP is on, stop using it to detect the state of servo. Using the EC uart is good enough and it simplifies the device state stuff. BUG=none BRANCH=none TEST=on reef and gru verify cr50 can detect servo and disable/enable cr50 uart at whenever it is attached/detached. Change-Id: I2fe6e796feaae5d90682d5015cdde6b46950dae6 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383955 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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