| Commit message (Collapse) | Author | Age | Files | Lines |
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The previous comments were not correct. ENTERING_RW is not a GPIO
at H1. The reason of marking it unimplemented in gpio.inc is to
avoid the compile error from cros FW common module.
BUG=None
BRANCH=cr50
TEST=make buildall.
Change-Id: Ieecbc9128e4071accbe4408d41ec51cefb68cffc
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1842031
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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It is not always possible to rely on PMU for resetting the I2CS
controller. Most of the AP firmware versions deploy the 'I2C unwedge'
cycle when coming out of reset, but not all of them, this is why Cr50
needs to be able to recover on its own in case there was a crash and
the I2C bus was left mid transaction with the H1 holding down the SDA
line.
A GPIO is dedicated to monitor the I2CS_SDA line during reset. If the
line is kept low, it could be a sign of a 'wedged' controller. The g
I2CS FSM will reset any time the I2C 'stop' condition is detected.
The create the 'stop' condition the I2C_SCL input is disconnected from
the bus and connected to an internal GPIO, then I2C_SCL level is set
to 'high' and register inverting the I2C_SDA value is toggled, which
looks like a transition from zero to one to the controller. thus
creating the 'stop' condition.
BRANCH=cr50, cr50-mp
BUG=b:135772657
TEST=the test was ran on a Pyro device, which uses I2C for
communication with H1 and which AP firmware does not deploy the
'I2C unwedge' cycle.
Test instrumentation involved setting a Chrome OS startup file
such that once booted, the AP starts continuously polling TPM for
value of an NVMEM index, creating I2C traffic. The host
workstation sends the 'apreset cold' command to the EC within a
few seconds of Chrome OS coming up.
First run a special Cr50 image which is not resetting I2CS using
PMU on TPM restarts, is was not trying to unwedge the stuck I2C
bus. On five experiments, it takes on average 32 reboots for
until I2C bus is locked up and the DUT falls into recovery.
Then loaded the Cr50 image with this patch and ran the test
again, it survived for 150 cycles without a problem.
Change-Id: Iffec33f97557e3acfd1cd5fb76ba158f8c23b608
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730143
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This is a documentation only change which adds a table showing how
internal GPIOs of the g chip are used on Cr50.
Adding this table will make it easier to keep track of the GPIOs when
adding new use cases.
BRANCH=cr50, cr50-mp
BUG=none
TEST=make buildall
Change-Id: I1e573bdc4b9628aae17c7ba976ba1554ee1050e6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730142
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The existing SYS_RST_L implementation enables the output on SYS_RST_L
before setting the level to 0, which results in cr50 briefly driving
SYS_RST_L high when SYS_RST_L is asserted. This patch switches SYS_RST_L
to a pseudo open drain mode, which eliminates the pulse.
The internal pull up on SYS_RST_L is not being removed, so the H1 will
still pull this line up when SYS_RST_L output is set to 1. Removing the
pull up will require careful analysis of existing designs, and if safe
will be done in a different patch.
BUG=b:117676461
BRANCH=cr50
TEST=assert/deassert sys_rst_l and check that 'sysrst' shows the correct
state. Verify this works on cheza which only pulls SYS_RST_L up to 1.8V
even though VDDIOM is 3.3V.
Change-Id: I50c9569e70c97cec434df3095f1b109f3248076b
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1282020
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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gpio.c has support for making pins open drain. This implementation will
prevent the signals from being driven high. Use the gpio.c support
instead of the hack we were using before.
BUG=none
BRANCH=cr50
TEST=the EC can assert CCD_MODE_L when cr50 has it deasserted. Verify
this on a ARM and x86 device in the lab.
Change-Id: I7f2a465782f2c60a850c25153fb65eb96fff0712
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1282019
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The ap_state machine as is is pretty hard to modify as it's implemented
now. The state machine has to have certain states set at certain points
to handle AP detection properly and it is very slow to detect AP off. It
takes a second and it will only detect AP off if TPM_RST_L stays
asserted for 1 second. This change modifies ap_state.c to use interrupts
instead of polling, so it can detect when the AP is off immediately and
wont miss any resets. This is required for the new closed loop reset
feature. Cr50 has to be able to detect all AP resets and it can't take 1
second for cr50 to determine the AP is off.
We used polling because we had to use APTX_CR50RX to detect AP state for
a while. The UART level changes a lot. Processing all of the interrupts
really impacted CCD uart, so we couldn't use interrupts to detect the
state. We had to poll. AP UART isn't used to detect AP state anymore on
any platforms, so it's ok to switch to interrupts now.
APTX_CR50RX is still used for ap uart detection in ap_uart_state.c. This
change doesn't modify that at all.
BUG=b:123544145
BRANCH=cr50
TEST=Make sure suspend and reboot stress tests still work on a bob and a
soraka. Check that Cr50 detects the AP state correctly.
Change-Id: I80eb97aecffe460b7857e66e7204a55b72c9dd47
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1446999
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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These gpios are detecting ap and ec uart. Rename them to reflect that.
We are adding another interrupt for ap state detection. Rename the uart
gpios, so it is a little less confusing.
BUG=none
BRANCH=cr50
TEST=none
Change-Id: I11c8c4465845540e9cda603ddb98c91a8022912b
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1446998
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The interrupt gpios are all grouped at the top of gpio.inc. They start
using PIN(1, 0) and use the next pin as interrupts are added.
EC_TX_CR50_RX used to be a standard interrupt, but we stopped using the
interrupt handler in chip/g/gpio.c and started using a dedicated
interrupt for this signal, so we could do uart bitbang faster. This
change moves EC_TX_CR50_RX, so we can keep the standard we were using
for interrupt definitions. It moves EC_TX_CR50_RX to PIN(1, 11,)
because that's the highest unused pin. We should be able to continue
counting up for interrupt definitions and counting down for other gpio
definitions.
BUG=none
BRANCH=cr50
TEST=use uart bitbang to program nocturne.
Change-Id: I46c1b296db57d774203ba097cc82722f31388d0b
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1443870
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Change the comments so it's more obvious what the sections are in
gpio.inc
BUG=none
BRANCH=none
TEST=none
Change-Id: I11566aa1748519df8cdc3cf9269e2a0c90c2dad9
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1443869
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Drives OEM specific GPIOs to enable and disable factory mode to a closed
source EC.
BUG=b:118683718
BRANCH=none
TEST=make buildall. Verified GPIO states with scope in both factory mode
enable and disable conditions. Verified GPIO states are reapplied
correctly after reboot, deep sleep, and power cycle.
Change-Id: I9bc547504478fded5f95c515027e1da0f245d524
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1358733
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The original bit bang programming implementation attempted to provide
a fully functional alternative UART interface for the case when EC
programming is required, so that proper UART parity can be ensured.
Come to think of it, this is not really necessary:
- EC programming over UART does not require full duplex.
- when EC is being programmed, the AP is held in reset, there is no
need to support AP console or TPM at that time, as a result
interrupts could be disabled for somewhat longer intervals.
This patch introduces the following modifications:
- remove uartn interface redirections - when bitbang mode is enabled
regular EC console is not available.
- instead of waiting for fixed amount of cycles on every bit, wait
for the deadline calculated when character transmission started on
tx side or when the original start bit was detected on rx side and
recalculated after each clock.
- when finishing receiving a character do not exit ISR right away,
spin for a duration of a character polling the rx line, in case
the EC keeps transmitting. The rx buffer is allocated on the ISR
stack and is limited to 20 bytes, which would probably cause an
overrun if this interface were used for reading flash contents
from the EC.
- connect USB EC console flow directly to the bit bang driver when
bit bang mode is enabled and disable interrupts from the EC UART.
- do not use the GPIO wrappers for bit bang interrupt processing -
it takes too long.
- when starting a bit bang session set the clock timer value to
zero, this allows not to worry about wraparound, which will happen
in almost 3 minutes, programming session should not take this
long.
- for the duration of 'bit bang enabled' state servo detection
interrupt is disabled, it gets re-enabled after bit bang mode is
disabled and servo_detect() gets to run on 1s hook.
- it is not enough to check the DIOB5 pinmux state to tell if EC
UART is connected or not, as this pin could be connected in bit
bang mode as well; always report EC TX UART as disconnected when
bit bang mode is enabled.
- for the duration of bit bang programming session suppress
'aggregate' GPIO interrupts, triggered per port when GPIO
interrupt is asserted.
Additional speed up could be achieved if gpio driver wrappers were
replaced with direct register accesses, but even as presented this
patch allows to reliably program the STM32 on Scarlet at 57600 baud,
which is 6 times faster than the current state.
BRANCH=cr50, cr50-mp
BUG=b:62539385
TEST=with some flash_ec modifications which make sure that bit bang
mode is enabled properly (fixing timing of setting boot0 and
resetting the EC), Scarlet device EC can be reprogrammed at 57600
baud 100 times in a row with and without logic analyzer connected
to the EC UART pins.
Change-Id: I2e3520f158943323cb015fa18650a7e177f03cc3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1171221
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The Cheza EC requires EC_RX_H1_TX be held low while the EC is being
reset to enter gang mode. This change adds another programming mode to
ec usb spi programming to do that.
BUG=b:74388083
BRANCH=cr50
TEST=The cheza boards aren't in, so I just tested EC_TX_CR50_RX_OUT
gpioset EC_TX_OUT 0 and 1 setup EC_TX_CR50_RX_OUT correctly as an
output when asserted and an input when deasserted.
Change-Id: I7fc9cba954f2af5a841f00ce5bf8a27251b33bbe
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1003529
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This change creates a state machine to handle ap uart detection. It
removes all of the ap_uart stuff from ap_state.c and moves it to
ap_uart_state.c. All boards will now use ap_uart to enable/disable ap
uart and tpm_rst_l to detect the ap state.
Separate ap uart detection from ap detection, so we can disable the ap
uart without enabling deep sleep. If the ap is in S3 on ARM devices,
Cr50 wont be in deep sleep, but the AP UART RX signal wont be pulled up.
In this case we need cr50 ap rx to be disabled and deep sleep to be
disabled.
BUG=b:35647982
BRANCH=cr50
TEST=run firmware_Cr50DeviceState on scalet and electro
Change-Id: I81336a9e232df8d44b325eef59327a1c06a80cba
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/884307
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This is the last state machine which used common/device_state.c. But
servo is more complex than that, because it needs to differentiate
state-isn't-known (debouncing) from state-isn't-knowable (Cr50 driving
EC TX), so it's cleaner to split it out the way we did AP and EC state
machines in previous CLs.
BUG=b:35587387
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
// Test detect at boot, even with CCD connected
Pull CCD_MODE_L low
Pull DETECT_SERVO high
Pull DETECT_EC high
reboot -> 'Servo connect'
// CCD is not driving EC UART TX
ccd -> EC on, Servo connected, CCD enabled, EC UART RX
// When servo disconnects CCD can drive EC TX
Pull DETECT_SERVO low --> 'Servo disconnect'
ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX
// Can't detect servo reconnecting if we're driving EC TX
Pull DETECT_SERVO high --> (no change)
ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX
// When we stop driving EC TX, can redetect servo
Pull EC_DETECT low --> See 'EC off', 'Servo connected'
ccd -> EC off, Servo connected, CCD enabled, EC UART disabled
// Test debouncing at boot
Pull DETECT_EC high
Pull DETECT_SERVO low
Pull CCD_MODE_L high
reboot
Within 1 sec, pull DETECT_SERVO high --> 'Servo connected'
// Test debouncing after boot
Pull DETECT_SERVO low then high < 1 sec --> (no message)
Change-Id: I964bd36c35f52c8ef7b3ea3793b6e0764e93587c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/636047
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The device state machines aren't quite similar enough to use common
code. Split the AP state machine out, the way we split out the EC
state machine in the previous CL.
BUG=b:35587387
BRANCH=cr50
TEST=manual, with Cr50 strapped (or hard-coded) not to use platform reset
and not to use TPM reset to detect the AP:
Pull CCD_MODE_L low, so Cr50 detects/enables CCD
Pull AP_DETECT high.
Pull INT_AP_L low (with resistor).
Pull AP_DETECT low --> See 'AP off' message
gpioget --> INT_AP_L=0
ccd --> AP UART disabled
Pull AP_DETECT high --> See 'AP on' message
gpioget --> INT_AP_L=1
ccd --> AP UART RX+TX
Pull AP_DETECT low for <1 sec then back high
(don't see AP off/on message)
gpioget --> INT_AP_L=1
ccd --> AP UART RX+TX
Reboot with AP_DETECT still low -> AP off at 1 second
Reboot with AP_DETECT still low and then assert AP_DETECT
within a second -> AP on immediately
Repeat with Cr50 strapped/hard coded to use platform reset, but
using TPM_RST_L instead of AP_DETECT. Note that this will also
show TPM reset debugging output when TPM_RST_L is asserted.
Change-Id: Ief9e4e5f2585ff925de1595cc8fbd5306c94a806
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634248
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The device state machines aren't quite similar enough to use common
code. Split the EC state machine out, the way we split out BattPrsnt
and CCD_MODE.
BUG=b:35587387
BRANCH=cr50
TEST=manual
Pull CCD_MODE_L high, so Cr50 detects/enables CCD
Pull EC_DETECT high.
reboot -> 'EC RX only', then 'EC on' at 1 second
Pull EC_DETECT low --> See 'EC off' message
ccd --> EC UART disabled
Pull EC_DETECT high --> See 'EC on' message
ccd --> EC UART RX+TX
Pull EC_DETECT low for <1 sec then back high
(don't see EC off/on messages)
ccd --> EC UART RX+TX
Reboot with EC_DETECT still low -> EC off at 1 second
Reboot with EC_DETECT still low and then assert EC_DETECT
within a second -> EC RX only, then EC connect at 1 second.
Change-Id: I71687e651d625cadd656934f4cb2bbadc0b58816
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/619750
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The code to mirror Rdd detect into CCD_MODE_L and handle keepalive is
now inside chip/g/rdd.c It uses a HOOK_SECOND state machine similar to
what's coming for EC/AP/Servo.
This also removes the explicit 'ccd enable' / 'ccd disable' commands,
since they'd be overridden by the HOOK_SECOND handler. If you need to
force CCD enabled, use 'ccd keepalive enable'.
BUG=b:64799106
BRANCH=cr50
TEST=With a CR50_DEV=1 images:
Disconnect CCD cable (pull RDCC1 and RDCC2 outside 0.2-2.0V)
gpioget --> CCD_MODE_L = 1
ccd --> CCD disabled
Connect CCD cable --> see 'Debug accessory connected'
gpioget --> CCD_MODE_L = 0
ccd --> CCD enabled
Briefly disconnect and reconnect CCD cable --> No debug output
gpioget --> CCD_MODE_L = 0
ccd --> CCD enabled
Disconnect CCD cable and wait a second --> 'disconnected'
gpioget --> CCD_MODE_L = 1
ccd --> CCD disabled
Force CCD_MODE_L = 0 externally, wait a second
gpioget --> CCD_MODE_L = 0
ccd --> CCD enabled
Stop forcing CCD_MODE_L externally, wait a second
gpioget --> CCD_MODE_L = 1
ccd --> CCD disabled
ccd keepalive enable
gpioget --> CCD_MODE_L = 0
ccd --> CCD enabled
ccd keepalive disable
gpioget --> CCD_MODE_L = 1
ccd --> CCD disabled
Change-Id: I65110b45e76f60390828e0fbbac8f36fc2cc9b37
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/619393
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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A common failure condition on the i2c bus is when the master
unexpectedly stops clocking the bus while the slave is driving the SDA
line low. In this case the master is not able to issue Stop or Start
sequences, which makes the bus unusable.
Good slave controllers are able to detect this condition and recover
from it by removing the pull down from the SDA line. This patch adds
this capability to the g chip i2c slave controller.
A new timer function is created which samples the SDA line twice a
second. If it detects that SDA is low in two consecutive invocations
and the number of i2cs read interrupts has not advanced, it decides
that the "hosed slave" condition is happening and reinitializes the
i2c driver, which removes the hold from the SDA line.
Even though the state of the SDA line is supposed to be accessible
through the I2CS_READVAL register, it in fact is not, reads always
return zero in the SDA bit. To work around this a GPIO (port 0, bit
14) is being allocated to allow to monitor the state of the line, it
is multiplexed to the same pin the SDA line uses.
When the AP is in low power modes the SDA line is held low, this state
should not trigger i2c reinitializations.
CQ-DEPEND=CL:616300
BRANCH=none
BUG=b:35648537
TEST=connected H1 on the test board to an I2c master capable of
stopping clocking mid byte. Observed that the existing code would
just sit in the "hosed" state indefinitely. The code with the fix
recovers from the condition (drives the SDA line high) 500ms to
1s after the failure condition is created.
Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/614391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add a pulldown to spi mosi and clk pins. The floating signals are
causing power issues with the spi buffer. This change adds pulldowns
to prevent the issues.
BUG=b:38509318
BRANCH=cr50
TEST=eve power drops to 2mW and reef power numbers are unchanged. Flash
the EC and AP on both boards using ccd.
Change-Id: I595920f461a67effcbdb52a4334683b6eca2b3b2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/595213
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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When installed in the factory test rig, the DIOB4 pin is set to high
by the moment the RW section starts.
Software behavior needs to change to comply with the factory test rig
requirements. Define the GPIO and add a function to report the factory
mode state.
BRANCH=cr50
BUG=b:63686091
TEST=tested along with the rest of the stack of patches.
Change-Id: I8c4158fc75138d717fc009496365c8e61b42a890
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579584
Reviewed-by: Nick Sanders <nsanders@chromium.org>
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Cr50 needs to be able to bit bang the EC UART in order to flash certain
ECs such as the STM32 family. This is because the UART block on the
chip has no provision to change the parity which is necessary for the
STM32 bootloader protocol.
This commit adds a configuration to bit bang the EC UART. It's been
tested at 9600 baud.
BUG=b:35648297
BRANCH=cr50
TEST=With a logic analyzer, verify that TX to the EC can be bit banged
with no issues at 9600.
TEST=With some other changes, verify that cr50 is able to flash an EC
image to an STM32 EC.
Change-Id: Ice72aff133f268b5b7f0868aeec590a21404d1af
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/503474
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This commit changes the behaviour of handling the CCD_MODE_L pin. When
Cr50 is not in CCD mode, it will stop driving the pin and turn it into
an input. This allows the pin to be driven by the EC. Cr50 will then
poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD
mode. Once the pin is deasserted, CCD mode is disabled.
However, when Cr50 itself makes the decision to enter CCD mode, it
changes the pin from an input to an output and drives the pin low.
NOTE: The rdd interrupt does not directly trigger CCD mode, but now
drives the pin low. A side-effect of the pin going low is that CCD is
enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the
pin to be setup as an input again.
CQ-DEPEND=CL:448988
BUG=b:35804738
BRANCH=cr50
TEST=Flash dev board, use `ccd` console command to both enable and
disable CCD. Verify that when CCD is enabled, the state of DIOM1 does
not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low
enables CCD. Letting it float disables CCD.
TEST=Verify that CCD mode is reflected in the device state.
Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/448161
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The cr50 needs to be aware of the power state of the system and of the
moment when the AP is reset, because this is when the TPM needs to be
reset too.
Arm and x86 platforms provide different hints in these cases.
In case of x86 there is a single signal cr50 can rely on: PLT_RST_L.
This active low signal is asserted when the system is going into any
power state deeper than s0ix. The cr50 can fall into deep sleep when
PLT_RST_L is asserted, and has to wake up and reset the TPM when this
signal is deasserted. There could be other wake triggers, but the tpm
should not be reset unless PLT_RST_L is inactive. It is also important
not to fall into deep sleep when PLT_RST_L is pulsed to reboot the
system.
In case of ARM there are two separate signals. Deasserting SYS_RST_L
signal is the trigger to reset the TPM, The GPIO_DETECT_AP going low
for a duration of time is the indication of the AP going into some
kind of sleep mode. The ARM case requires more clarification.
This adds run time configuration of the the sleep state control input.
Once the input turns low, the CHIPSET_SHUTDOWN signal is sent and deep
sleep mode is enabled. Again, this will require adjustment for ARM
platforms.
The wake from deep sleep state is controlled by the wake pins as
before, but by level instead of edge. This makes sure that in case the
trigger for deep sleep goes away while deep sleep preparation is under
way, the device resumes immediately instead of getting stuck missing
the edge.
The TPM_RST_ input is now triggering interrupts on deassertion
- this is the moment when the TPM needs to be reset. The ISR is being
renamed accordingly.
The processing previously happening inside the ISR is being moved into
a deferred function running on the hooks task context.
There is no need to invoke TPM reset related functions from the PMU
wake up ISR anymore.
BRANCH=none
BUG=chrome-os-partner:59007
TEST=as follows:
1. make buildall -j succeeds
2. started on Reef, still in progress after 100 iterations, early to
call
suspend_stress_test --suspend_min 40 --suspend_max 45 \
--wake_max 15 wake_min 10
(note that reef does not fall into s3 any more, so the test does not
verify H1 deep sleep)
3. modified the target to fall into s3 during the test and
successfully repeated it for 100 iterations
4. tried battery disconnect a few times and observe successful boot.
Change-Id: Ica06ec0d363b53eede3be327404ff5807fa3a610
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/436865
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Previously only 1 pin DI0A1 was being read to distinguish between
SPI/I2C configurations. This change adds code to support reading 4
strapping pins DIOA9|DIOA1 and DIOA12|DIOA6 and enabling the internal
pullup/pulldown reistors to differentiate between weak and strong
external pull up/dn restistors. An 8 bit strap config id is produced
and then a config table is searched to match the config id with known
configuraitons. The board properties to be used are read from the
config table.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Modified the Cr50 dev board with 1M and 5k pullup/pulldown resistors
and connected them to 4 GPIOs (defined as strapping pins). Tested the
12 possible external pullup/pulldown configurations and verified that
the correct 5 bit value was produced for each configuration.
Tested with both Reef and Gru. On Reef the strap config = 0x12 and on
Gru it reads 0x2 as expected. Verfifed TPM was functional on both systems.
Change-Id: I18c625a2b6b904bf4bcdaf2665ed9c3cbdafeb54
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421580
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Just a clean up patch attempting to make it easier to new users to
come up to speed with cr50 use of H1 GPIO subsystem.
BRANCH=none
BUG=none
TEST=none
Change-Id: I539e7629ee94ddef26ae1616dc6eb5c151e9d97e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412412
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Boards that have plt_rst_l had sys_rst_l currently use the two signals
to detect resets and reset the TPM. That meant that the TPM could reset
twice depending on the timing of those signals. On boards with
plt_rst_l, we should really just use that to detect system resets and
not sys_rst_l. On boards with plt_rst_l, sys_rst_l should only be used
as an output to trigger warm resets.
This change makes both boards use the gpio tpm_rst_l_in to detect AP
resets. That gpio will be connected to a different pin depending on
which board we are using. On Gru the gpio will be connected to diom0
which is sys_rst_l, and reef will use diom3 which is plt_rst_l.
BUG=chrome-os-partner:61789
BRANCH=none
TEST=manual
Use cr50 servo to verify the contents of /var/cache survive
reset after 'dut-control warm_reset:on sleep:0.5000
warm_reset:off'
test on gru and reef
verify that the system can boot to kernel
run 'sysrst pulse' and check that you only see one system reset
use 'pinmux' to verify the pins for the two types of boards are
setup properly
on reef diom0 is an input, diom3 is an input with wake_falling,
and gpio1_gpio1 uses diom3
on gru check that diom0 is an input with wake_falling, diom3 is
not configured, and gpio1_gpio1 uses diom0
Change-Id: I1f6e8bfa525ffa5585a18282b78014f36f0cfee6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428130
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Having cr50 resume on the falling edge of its uart rx signal is causing
some issues, and wake on low is good enough and works fine. This change
switches uart rx from DIO_WAKE_FALLING to DIO_WAKE_LOW
BUG=chrome-os-partner:60449
BRANCH=none
TEST=cr50 can still resume on uart activity and plugging in the charger
has no impact on cr50 remaining in deep sleep.
Change-Id: If77126cb64cf2fa949a75d53bb40098f037a2aa4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418335
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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On both Reef and Gru there are INA (shunt bus voltage monitor) ICs
connected to the Cr50 I2C master bus. The use case for these chips is
in a lab setting using case closed debugging. Power to the INA chips
is controlled by a separate Cr50 gpio signal.
By default, the INAs are powered off and the I2C master bus is not
connected. A function ina_connect() is provided which needs to be
called prior to attempting to access the INAs via I2C.
BRANCH=none
BUG=chrome-os-partner:57059
TEST=manual
Tested both Reef and Gru. Verified that console command 'ccd ina
on|off' works as expected and that can repeatedly read registers on
the INA using the following command "i2cxfer r16 0 0x40 0".
Read 0x2771 [10097] which is the default value. In addition
wrote register 14 (bits 15:1 are writeable) and verified the value was
able to read the value back which was written.
Change-Id: I670f7897555dae29642264531599dc4471c52bbd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394168
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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For TPM operation with Intel chipset APs, the signal PLT_RST_L needs
to trigger a TPM reset. For current Reef boards, this signal is
connected to DIOA13. The next version will have it on DIOM3.
This CL adds support for platform reset connected on DIOA13 and uses a
new board property so that it doesn't affect Kevin/Gru.
BRANCH=none
BUG=chrome-os-partner:55115
TEST=manual
Used H1 dev board configured as Reef. Created high to low transisition
on to verify that platform reset was detected. Tested on Kevin to
ensure that resets were not occurring.
Change-Id: I58f02b7ffa644a9197f4303ae6e640df181040bd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380336
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The interrupts on all of the gpios detecting if the device is on were
edge triggered. If the rising edge happened in between when the gpio
level was read and when the interrupt was enabled, then the device state
could be falsely detected as off for a short period of time. This change
changes them to GPIO_INT_HIGH.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I9aa3cff14047cf4f6473c32f2cdc4724afca3414
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385164
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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The interrupts to detect when the falling edge on the UART signals are
currently disabled and never reenabled. Power off is detected by polling
and not through interrupts. This change removes all of those falling
edge interrupts.
BUG=none
BRANCH=none
TEST=cr50 can detect when the EC, AP, and Servo are off or on
Change-Id: I0fd8a0d970f3235b26af6b90dd395ea7c75e0c17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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The g i2c slave controller does not support clock stretching, so it is
necessary to flow control the AP by some other means. Luckily there is
an interrupt line which g can toggle and the AP can watch.
This patch adds generating a pulse on the AP interrupt line once g
finished processing the i2c transaction. In case of the read
transaction the pulse is generated after the data to read is put in
the i2cs transmit buffer.
BRANCH=none
BUG=chrome-os-partner:57338
TEST=with this patch and the AP firmware synchronizing on the
interrupt pulse, the TPM initialization succeeds in coreboot and
depthcharge.
Change-Id: I16c09b59b7d772624baa9d1f5258aaff26f91ff9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385256
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Now that the AP uart is enabled whenever the AP is on, stop using it to
detect the state of servo. Using the EC uart is good enough and it
simplifies the device state stuff.
BUG=none
BRANCH=none
TEST=on reef and gru verify cr50 can detect servo and disable/enable
cr50 uart at whenever it is attached/detached.
Change-Id: I2fe6e796feaae5d90682d5015cdde6b46950dae6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383955
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup on reef.
On Kevin there is a bug preventing the EC from being able to pull
sys_rst_l up high enoug for cr50 to detect that it is pulled high. This
change adds an internal pullup back when cr50 detects that it is on a
kevin or gru.
BUG=chrome-os-partner:56945
BUG=chrome-os-partner:53544
BRANCH=none
TEST=On gru and kevin remove servo verify when apreset is run on the EC
it resets cr50 and the AP. Run pinmux and check that there is a pullup
on diom0 on kevin but not on gru.
Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381322
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This reverts commit 5e6da91fe86301d276b452a660139c27c3786a82.
Change-Id: I65b37c087a86fab06f6e23e895ceee2ae2def5ee
Reviewed-on: https://chromium-review.googlesource.com/381160
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
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This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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UART0 RX only needs to be disabled on reef. This change uses a system
property instead of a #define to disable UART0 RX that way it can just
be done on Reef not Gru or the dev board.
BUG=chrome-os-partner:55510
BRANCH=none
TEST=manual
rw 0x4060000c shows a value of 1 for reef and 3 for gru
gru kevin and reef still boot.
Connect DIOA13 to DIOA1 on the dev board and verify the console
can be used.
Change-Id: I5ee3559c2b35f959c0d67f233d1dfa40743b4064
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378336
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup.
Without the internal pull up SYS_RST_ODL is asserted when the EC is off.
This change modifies how sys_rst_asserted is handled so cr50 will ignore
the sys_rst interrupt whenever rbox asserts EC_RST to make sure cr50
doesn't reset itself every time it resets the EC. If the EC resets
itself and sys_rst_l is no longer pulled up, it is fine if cr50 resets.
BUG=chrome-os-partner:53544
CQ-DEPEND=CL:377504
BRANCH=none
TEST=manual
'rw 0x40550010 1' causes the EC to reset but not cr50
On the development board verify DIOM0 is not pulled up.
Test cr50 boots normally on reef, gru and kevin dvt1
Change-Id: Id8e8f6f7bb91741da34bdd6fec89eb841dd94f35
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376886
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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This reverts commit d0383d88146e19c64230670aa6769528e5228c76.
Change-Id: I76cac7902b0cd25300393efcf205cdbe9ade82c0
Reviewed-on: https://chromium-review.googlesource.com/376132
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
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Just adding a TODO comment to the gpio.inc file.
BUG=chrome-os-partner:56540
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I5fa1a765232fd31b03d8825324a3a6a964504b5a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374619
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup.
Without the internal pull up SYS_RST_ODL is not pulled up whenever the
EC is off. I changed how sys_rst_asserted is handled so it will ignore
the sys_rst interrupt whenever rbox asserts EC_RST to make sure cr50
doesn't reset itself every time it resets the EC. If the EC resets
itself and sys_rst_l is no longer pulled up, it is fine if cr50 resets.
BUG=chrome-os-partner:53544
BRANCH=none
TEST=manual
'rw 0x40550010 1' causes the EC to reset but not cr50
On the development board verify DIOM0 is not pulled up.
Test cr50 boots normally on reef and gru
Change-Id: Ic1d4d160ddb0d69081cb1f194d50939dac6fc5c2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373838
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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DIOM3 is no longer used. Remove it from gpio.inc
BUG=chrome-os-partner:55895,chrome-os-partner:55896
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I1f7aeab8135fa97aab04945b6a450e32903e2e84
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372405
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The input should be active low, not active high.
BUG=chrome-os-partner:49959
BRANCH=none
TEST=manual
Remove and reattach the battery. "gpioget BATT_PRES_L" shows the
GPIO value changing appropriately.
Change-Id: I7d513471f6ab5e7e8cd0e601148915697fa9162a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366134
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
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There is just one version of Cr50 firmware for all boards
that it's used on. However, on some boards the AP communicates
to the TPM via a SPI interface (i.e. Kevin) and on others, the
AP communicates via an I2C interface (i.e. Reef). In order to
dynamically discover which interface to configure, there are
strapping resistors added to the board which enables the Cr50
to detect which configuration to implement.
This CL is a first pass and is only looking at DIOA1 which is
pulled high for SPI and pulled low for I2C configurations.
The strapping resistor should be read when the AP is in reset
prior to it attempting to drive any of the lines used for
strapping. To ensure this condition is met, Cr50 will only
check the strapping options following a POR (power on reset).
Once the configuration type is discovered, a 'long_life'
register is used to hold the result so that the result can
always be available. The long_life register contents remain
unchanged until a subsequent power down event.
BRANCH=none
BUG=chrome-os-partner:50728
TEST=manual
Tested on Kevin and Reef. Verfifed by reading the stored value
that the SPI configuraiton is detected for Kevin and the I2C
interface is detected on Reef. In addition, verified on Kevin
that the Cr50 FW version is correctly reported to the AP which
means that TPM register reads via the slave SPI are functioning.
Change-Id: Ibd7624ad8e3b4126f6346dce0bc72f62a3cc6d18
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363014
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Cr50 was not waking up long enough after SPS_CS_L was asserted for the
spi slave transactions to start and disable sleep. It also was not
handling SYS_RST_L properly when it was asleep.
This change sets SPS_CS_L to be an edge triggered wake up source instead
of level triggered, because cr50 should just wake up on the edge and
disable sleep until the spi transaction is done.
It also adds sys_rst_l as a wakeup source. The sys_rst_asserted
interrupt cannot be triggered while cr50 is asleep, so the
pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at
resume. This change relies on the EC extending the delay in
chipset_reset to be long enough for SYS_RST_L to still be asserted when
cr50 resumes.
BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
make sure suzyq is disconnected.
verify ap boots up to the kernel after running
'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec
console.
Check that cr50 goes to sleep when the AP is not trying to use
the TPM.
When cr50 is asleep pwrbtn + refresh still resets the system.
Disable SYS_RST_L_IN as a wake source and verify the system
verification fails and requests a recovery image.
Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363606
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Add a GPIO to control the INA 3.3V power rail load switch on Reef.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=none
Change-Id: I2be33ebff376b50f9cc2962db5fc3fa11f4bb107
Reviewed-on: https://chromium-review.googlesource.com/361692
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
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Having DIO A4, A8, and A14 connected to the spi master output pads
prevents reef from booting. We need to tristate those pins when spi ccd
is not in use.
This change disconnects those pins from the spi peripheral when spi is
disabled and reconnects them when spi is enabled.
BUG=chrome-os-partner:53582
BRANCH=none
TEST=manual
use 'pinmux' to verify DIOA4, DIOA8, and DIOA14 are set have
GPIO 7, 8, and 9 as their output sources when not using the usb
spi interface.
Check the usb spi interface still works.
Enable usb spi then disable ccd and check that the pins are
connected back to the non-peripheral gpios.
Verify the AP on kevin and reef can be flashed using servo.
Verify the AP boots successfully on both.
Change-Id: I85d70422a30da445076432d2bfc81960aeba8578
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357883
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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If the UART0 RX pad is not pulled up, cr50 will get held up on all of
the interrupts triggered by the low signal. This causes cr50 to reboot
continuously. UART0 RX was moved to DIOA13, which does not have an
internal pull up. This means we have to rely on an external pull up.
Because not having an external pull up on DIOA13 could prevent the
system from booting and UART0 RX is only used as an alternate debugging
mechanism from suzyq, we decided it is best for UART0 RX to be disabled
by default.
BUG=none
BRANCH=none
TEST=Connect UART1_RX to DIOA1 and test that it still accepts input.
Disconnect it from any pads. Verify the system boots normally and
console input from DIOA1 no longer works but the suzyq shell still does.
Change-Id: I68988c59cfce610cc6c360bf8dd9685e98ab12ff
Reviewed-on: https://chromium-review.googlesource.com/357881
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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We need to have an internal pull down so the UART TX signals will be
pulled low when servo is disconnected.
BUG=chrome-os-partner:54547
BRANCH=none
TEST=On gru test that servo detection works.
Change-Id: I7d549766273862eb23c0645b887f3db4a0adbab1
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353764
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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