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* usb_i2c: Fail if board I2C bridge is disabledRandall Spangler2017-07-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb_i2c_board_is_enabled(). On Cr50, this is now also connected to the I2C CCD capability. The USB-I2C bridge can only be used when the capability is available. On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is a no-op, add a dummy implementation which always returns true. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 Connect host PC to dev board USB port On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x8001 ccdoops --> reset I2C config ccd i2c disable --> I2C disabled On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x0006 ccd i2c enable --> I2C enabled ccdunlock --> I2C disabled ccdoops --> I2C enabled ccdset i2c unlesslocked ccdlock --> I2C disabled ccdunlock --> I2C enabled Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590577 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Rename uartn_enabled() to uartn_tx_is_connected()Randall Spangler2017-07-291-7/+9
| | | | | | | | | | | | | | | Because that's what it means. That is, it reports the state of uartn_tx_connect(), not uartn_enable(). No functional changes; just a rename. BUG=none BRANCH=cr50 TEST=make buildall -j Change-Id: Ie2273b277bd73a40307be7ec215417c1225cd567 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590859
* cr50: protect EC/AP reset commands using CCD V1Randall Spangler2017-07-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sysrst and ecrst commands are now protected by the RebootECAP capability. They can print the state of the reset lines when the capability is not allowed, but can only change the state or pulse the reset lines when the capability is allowed. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build: ccdoops --> reset CCD config and go to Opened state ecrst pulse --> works sysrst pulse --> works ccdunlock ecrst pulse --> access denied sysrst pulse --> access denied ecrst --> prints state sysrst --> prints state ccdoops ccdset rebootecap unlesslocked ccdunlock ecrst pulse --> works sysrst pulse --> works Change-Id: Ia9ebe67bdc1e85129051caf94f20fb2fb84b76da Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590071 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Have CCD_MODE_L respect "ccd keepalive".Aseda Aboagye2017-06-011-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | If CCD was set to the "keepalive" mode, removing the debug accessory would cause the CCD_MODE_L pin to be pulled high, ignoring the keepalive state. CCD was still kept alive, but the state reflected on the pin didn't indicate so. This commit changes the behaviour such that the CCD_MODE_L pin is set up as an input only when CCD keepalive is not enabled. BUG=None BRANCH=cr50 TEST=Plug in debug accessory and remove debug accessory. Verify that CCD_MODE_L is high after removal. TEST=Enable ccd keepalive. Remove debug accessory. Verify that CCD_MODE_L is still low. Change-Id: I407994d5c394a717d6e1a87f283f6441bd26bf55 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/520603 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Only drive CCD_MODE_L when in CCD mode.Aseda Aboagye2017-03-071-25/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the behaviour of handling the CCD_MODE_L pin. When Cr50 is not in CCD mode, it will stop driving the pin and turn it into an input. This allows the pin to be driven by the EC. Cr50 will then poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD mode. Once the pin is deasserted, CCD mode is disabled. However, when Cr50 itself makes the decision to enter CCD mode, it changes the pin from an input to an output and drives the pin low. NOTE: The rdd interrupt does not directly trigger CCD mode, but now drives the pin low. A side-effect of the pin going low is that CCD is enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the pin to be setup as an input again. CQ-DEPEND=CL:448988 BUG=b:35804738 BRANCH=cr50 TEST=Flash dev board, use `ccd` console command to both enable and disable CCD. Verify that when CCD is enabled, the state of DIOM1 does not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low enables CCD. Letting it float disables CCD. TEST=Verify that CCD mode is reflected in the device state. Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/448161 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: enable utmi wakeupsMary Ruthven2017-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | We had disabled wakeups on the AP phy when we were running on gru, because the AP phy was not in use. We never changed that for reef, so UTMI wakeups were disabled even when the AP USB was supposed to be enabled. After Cr50 went to sleep any usb transactions would drop bits, because Cr50 wouldn't notice anything was happening until it woke up on one of the HOOK_TICK events. This change reenables UTMI wakeups on boards with AP usb. It writes 1 to USB_PCGCCTL_STOPCLK. This makes the controller disable the PHY clock whenever it detects a usb suspend. When it resumes out of suspend, this bit has no effect. BUG=b:35774906 BRANCH=cr50 TEST=Boot up reef. Wait until cr50 goes to sleep run 'usb_updater -f' and verify that it runs successfully. Make sure deep sleep still works Change-Id: I54bd866111b5c9b5738575f23757e0cbe4907ec4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448988 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Have INAs and I2Cm enabled when rdd is attachedScott2017-02-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INAs are only used for development and testing purposes. Therefore, the 3.3V rail to the INAs is off by default and the I2Cm module is not enabled. Enabling INA power and connecting the I2Cm module was done at the beginning of each USB to I2C request. The problem with this approach is that INA measurments didn't always succeed due to not enough time for the INAs to initialize. Rather than add some arbitrary delay, it is better to tie the INAs to when rdd is attached/detached. It is only when rdd is attached that the INAs will be accessed, so there is no need to enable/disable for each individual I2C transaction. This CL ties the enabling/disabling of the INA and I2Cm module to the rdd state. This change makes the previous use of usb_i2c_board_enable() and usb_i2c_board_disable() obslete. BRANCH=none BUG=chrome-os-partner:62375 TEST=manual Connect servo with suzyq connected: sudo servod -p 0x5014 -b eve -c eve_r0_inas.xml Then execute single INA reads dut-control pp3300_dx_edp_mv and verify that it returns meaningful numbers. Without this CL single reads via dut-control would always return 0. Change-Id: I799552bfd0701efd1828a0d720ac2a6cedee5ca1 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/436864 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add command to enable ccd indefinitelyMary Ruthven2017-01-201-18/+40
| | | | | | | | | | | | | | | | | | | For FAFT or debugging purposes we may want to leave ccd enabled no matter what the voltages on the CC lines are. This change adds a 'ccd force enable' which will keep ccd enabled until 'ccd disable' is run. BUG=chrome-os-partner:61701 BRANCH=none TEST=Plug in suzyq. Run 'ccd force enable'. Disconnect suzyq and on the cr50 uart run 'ccd' to verify ccd is still enabled. Make sure the other ccd commands work ok. Change-Id: Ia7087ade3070a1320a74b985f4699533ecc396ef Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/427346 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: extend sysrst pulse to 20msMary Ruthven2017-01-181-3/+10
| | | | | | | | | | | | | | | | Increase the sysrst pulse to be long enough to reset the AP. This change increases it to 20ms by default, but adds a parameter to set the interval in the sysrst pulse command. BUG=none BRANCH=none TEST='sysrst pulse' will cause the AP to reset and 'sysrst pulse 1000' shows that sys_rst_l is asserted and 1 second later it is deasserted. Change-Id: I66b0d627480852dc166f62dc0fddd02f094b6162 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/429150 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: keep board properties related code in board.cVadim Bendebury2016-12-201-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are plans to extend use of the LONG_LIFE_SCRATCH1 register for other purposes than keeping board properties. Just as the board properties, the new use is also very board specific. This patch moves the board properties code from chip/g to board/cr50, where it belongs. Instead of reading board properties bitmap and checking if various bits are set, api functions are now provided to allow determining various properties settings without actually looking at the properties bitmap. CQ-DEPEND=CL:*313057 BRANCH=none BUG=chrome-os-partner:58961 TEST=verified that both Gru and Reef boot with the new image, additionally, on Reef confirmed that it is possible to communicate with the H1 over USB, and that plt_reset signal is handled properly. Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547 Reviewed-on: https://chromium-review.googlesource.com/422081 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: remove the pull down on uart2 txMary Ruthven2016-11-211-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | The pulldown on diob5 is used to detect when servo is detached. It is unnecessary during deep sleep and when the EC console is active because servo detection is disabled. Having the pull-down enabled during these times can increase power consumption. This change disables the pulldown when the EC console and deep sleep are enabled. It also disables the diob5 input during deep sleep. BUG=chrome-os-partner:60020 BRANCH=none TEST=manual Disconnect servo Use the suzyq consoles to turn off the AP. Enable deep sleep. Measure the power consumed by vddiob and make sure it is around 0.3mW when the EC is in hibernate and when it is not. Change-Id: I8a653c28800cfbeeb1b4b8598d166846124c6b53 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/412940 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Stop disabling the AP/EC uart when ccd is disabledMary Ruthven2016-11-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This change removes the uart disable in rdd_disconnect. It used to be necessary because we used to disable device state detection in rdd_disconnect. Without device state detect we had to disable the AP and EC uart to make sure there were no interrupt storms. Now we keep device state detection running all the time. It handles enabling/disabling the AP and EC uart when it senses the RX signals aren't pulled up. UART is only enabled/disabled when cr50 detects that the AP or EC state changed from off to on or on to off. If the debug cable is detached and then reattched the uart will be disabled on detach, but it won't be reenabled until the AP/EC are rebooted. BUG=chrome-os-partner:58222 BRANCH=none TEST=Detach and reattach suzyq without rebooting the AP or EC and make sure both consoles come back after reattaching the cable. Change-Id: Id104e12dc533e8d7047f32aebd41abd1c959d267 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410269 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: add usb i2c driverMary Ruthven2016-10-141-47/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is based off of the protocol in the stm32 directory. We should unify these implementations and the other ccd endpoints at some point. Right now I though that I should keep the implementation the same as the other g chips ccd drivers. BUG=chrome-os-partner:57059 BRANCH=none CQ-DEPEND=CL:390015 TEST=manual download the servo patch and run 'sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml' Test the usb i2c bridge by running 'dut-control | grep pp' Attach servo and verify cr50 will not enable i2c Change-Id: I0f72671505f5451a960d3baea4b2c34b6910d892 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388896 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* g: use devid 0 and 1 to create a serial numberMary Ruthven2016-10-111-1/+1
| | | | | | | | | | | | | | | | | To be able to identify different cr50 devices connected to the same machine we need a serial number. This change uses dev id 0 and 1 to come up with one. BUG=chrome-os-partner:56641 BUG=chrome-os-partner:58342 BRANCH=none TEST=lsusb -vd 18d1:5014 | grep iSerial shows different numbers for different devices. Verify when ccd is disabled the serial number is 0. Change-Id: I85c54af4a21bdfd0542019c02aa8420d9a879fae Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395633 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add press and release options to powerbtn commandMary Ruthven2016-10-111-7/+25
| | | | | | | | | | | | | | | | | This change adds options to the powerbtn console command to press and release the power button. BUG=chrome-os-partner:58123 BRANCH=none TEST=manual 'powerbtn press' force a power button press 'powerbtn release' release the power button. This will not override the signal if the button is physically pressed. Change-Id: I52631d30dbae874ba6637f728cb6e435cb626e12 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/396207 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: I2CM: Enable i2c master for accessing INA chipsScott2016-10-111-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On both Reef and Gru there are INA (shunt bus voltage monitor) ICs connected to the Cr50 I2C master bus. The use case for these chips is in a lab setting using case closed debugging. Power to the INA chips is controlled by a separate Cr50 gpio signal. By default, the INAs are powered off and the I2C master bus is not connected. A function ina_connect() is provided which needs to be called prior to attempting to access the INAs via I2C. BRANCH=none BUG=chrome-os-partner:57059 TEST=manual Tested both Reef and Gru. Verified that console command 'ccd ina on|off' works as expected and that can repeatedly read registers on the INA using the following command "i2cxfer r16 0 0x40 0". Read 0x2771 [10097] which is the default value. In addition wrote register 14 (bits 15:1 are writeable) and verified the value was able to read the value back which was written. Change-Id: I670f7897555dae29642264531599dc4471c52bbd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/394168 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: ecrst and sysrst commands should show stateBill Richardson2016-10-071-21/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of the ecrst and sysrst commands don't have a way to show the state of the EC_RST_L and SYS_RST_L. This tweaks the commands to accept an optional "pulse" argument in addition to the boolean arg, which will assert, pause, then deassert the relevant signal. With no args at all, the current signal state is shown. BUG=chrome-os-partner:58123 BUG=chrome-os-partner:56835 BRANCH=none TEST=manual sysrst pulse resets the AP sysrst on/off asserts/deasserts SYS_RST_L sysrst displays the current SYS_RST_L state ecrst pulse resets the EC (and AP) ecrst on/off asserts/deasserts EC_RST_L ecrst displays the current EC_RST_L state Change-Id: I8e1c9a577afd9ed9e770f1b3f5c0a69e4607de66 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395587 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: add console commands to have parity with servoMary Ruthven2016-10-051-0/+76
| | | | | | | | | | | | | | | | | | | | | | This change adds apreset, ecreset, ec_rst, sys_rst and powerbtn options to the ccd console command. BUG=chrome-os-partner:58123 BUG=chrome-os-partner:56835 BRANCH=none TEST=manual sysrst resets the AP sysrst on/off controls SYS_RST_L ecrst resets the ec ecrst on/off controls EC_RST_L powerbtn 500 will simulate a power button press for 500 ms Change-Id: I89adc88eb407730c9d57811a07bfef8fcf63c5b9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393809 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: notify chipset hooks when the AP state changesMary Ruthven2016-09-221-6/+1
| | | | | | | | | | | | | | | | | | | | | Cr50 monitors UART1 RX to sense the state of the AP. This signal can be used to tell if it is in S0. If the signal is pulled up then the AP is on. If it is not pulled up then the AP is not in S0. This change notifies HOOK_CHIPSET_SUSPEND when UART1 RX is not pulled up, and then notifies HOOK_CHIPSET_RESUME when the signal is high again. The AP usb can be disabled during suspend, so this change changes the hook that triggers disabling the AP usb to be attached to HOOK_CHIPSET_SUSPEND instead of HOOK_CHIPSET_RESUME. BUG=chrome-os-partner:55747 BRANCH=none TEST=buildall Change-Id: I47fb38a4bbcd72424ec2535d61e87f820cf1bcd7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383978 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: release the AP usb if the AP is shutdownMary Ruthven2016-09-161-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | When cr50 connects to the AP usb it should only initialize the usb when it knows that the AP is on. If usb is incorrectly initialized it can prevent cr50 from going to sleep. In this change the AP usb will be initialized when suzyq is disconnected or on HOOK_CHIPSET_RESUME and it will be released on HOOK_CHIPSET_SHUTDOWN. BUG=chrome-os-partner:55747 BRANCH=none TEST=manual On reef run apreset and verify the AP can communicate with cr50 over usb after it boots up. Run poweroff and verify cr50 has released the usb. power the AP back on and check that it can communicate with cr50 again Change-Id: Id35010525e2354ee140d3b7220fb5ea434a0993f Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383979 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: AP console is always available via CCDBill Richardson2016-09-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Input to the EC UART console is restricted by default so that casual passers-by can't type random commands to it through the case-closed debug connection. However, there's no need to restrict the AP UART console, since it's entirely under the AP's control. This CL leaves the AP console enabled by default whenever the CCD cable is connected. It will be disabled when the AP is powered down or while servo is attached, but enabled otherwise. BUG=chrome-os-partner:55322 BRANCH=none TEST=make buildall, test on Cr50 hardware Use the "ccd" command to see and modify the UART console settings, and the "devices" command to observe how things change when servo is connected and things are powered up and down. Change-Id: I5cc453bc60473269e22112cf49f61495733abb10 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382152 Commit-Ready: Bill Richardson <wfrichar@google.com> Tested-by: Bill Richardson <wfrichar@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: connect to AP phy on reef when not in ccdMary Ruthven2016-08-251-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 needs to connect to the AP phy when not in ccd so cr50 can be updated and used as a gnubby. This change uses the strapping options to detect when it is on reef and modifies the ccd behavior to initialize usb on the AP phy when ccd is disabled. On gru the cr50 behavior is unchanged. In RDD this change removes the checks that the current_map is the correct one based on the detected debug state. rdd_init calls rdd_interrupt to set up the usb and ccd state correctly. Having that check prevents that initial rdd_interrupt from calling rdd_detached. Before rdd_detached just disabled usb and we knew during init it would already be disabled. Now we want to make sure it is called if a debug accessory is not attached to initialize usb on the AP PHY. BUG=chrome-os-partner:56098 BRANCH=none TEST=manual verify ccd still works on gru disconnect suzyq and reset reef. run lsusb on the AP and verify it shows cr50 as a device. connect suzyq and check that the AP no longer sees cr50. disconnect suzyq and verify the AP sees it again Change-Id: I3c1ccc54895835bce12302f3ea43fc2e751b4c97 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/372920 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Use parse_bool() for boolean argsBill Richardson2016-08-221-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The parse_bool() function exists so we don't have to litter our console commands with stuff like this: if (!strncasecmp(argv[1], "on") || !strncasecmp(argv[1], "enable" || !strncasecmp(argv[1], "true" || [...] This CL uses parse_bool instead of that kind of thing so I don't have to remember which commands use "enable" and which use "on" and so forth. I only changed the commands that Cr50 uses. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hardware I tested all the affected commands to ensure that they still work correctly: usb, ccd, flashwp (which doesn't do anything anyway). Change-Id: I7d875ab22934fb4b500e3d0f62ebe3e04101272d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373658 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: disable usb wakeup when debug accessory is disconnectedMary Ruthven2016-07-191-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | USB is only used for CCD. USB should not be enabled as a wakeup source unless a debug accessory is detected, because that is the only USB traffic we care about. The rest may be from other sources like the HID interface or something else using those signals. This change disables the utmi wake source when the debug accessory is attached and enables it when it is connected. BUG=chrome-os-partner:54796 BRANCH=none TEST=manual The SPI_CS_L pin still gets triggered and will wake up cr50 before usb so disable wake up pins as a wakeup source. Verify Cr50 goes to sleep and plugging in a SuzyQ will wake it up and after removing it Cr50 will go back to sleep. Change-Id: Ib97244016b0af244c340259915def9f4d8f97569 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360693 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: disable device monitoring when not in ccdMary Ruthven2016-07-121-5/+21
| | | | | | | | | | | | | | | When cr50 is not trying to do ccd, we dont need to monitor the devices. Disable device state detection interrupts and the AP and EC UARTs. BUG=none BRANCH=none TEST=gru and kevin monitor devices correctly when ccd is enabled, and dont monitor anything when it is disabled. Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356770 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: Dont switch from PHY 1 to 0 when disabling CCDMary Ruthven2016-07-111-8/+2
| | | | | | | | | | | | | | | | | The AP no longer uses PHY0 to to interact with Cr50. Cr50 only uses PHY1 so dont switch the PHY when disabling CCD just release the usb. BUG=none BRANCH=none TEST=After running 'ccd disable' the command 'usb' still returns PHY B, but 'lsusb | grep 5014' on the host doesn't show any devices. When CCD is enabled 'lsusb | grep 5014' shows a device on the host. Change-Id: Icec0acc7a0d00f7eb56c6feef3ff4cf5a3f99735 Reviewed-on: https://chromium-review.googlesource.com/359931 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: enable case closed debugMary Ruthven2016-06-031-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a ccd console command to control the usb endpoints. The uart console command is moved into this command so 'ccd uart [enable|disable]' controls the AP and EC TX signals instead of the 'uart' console command. CCD can be enabled using 'ccd enable'. This switches the PHY used by the USB controller to be the external PHY. Changing the PHY exposes the cr50, AP, and EC consoles as well as the upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles will be read only until 'ccd uart enable' is called. Cr50 can be updated using the usb upgrade endpoint. The EC and AP can be updated using the USB SPI endpoint. When CCD is disabled the usb controller will switch to using the AP PHY. None of the endpoints will be visible to the host. The USB SPI endpoint can be used to flash the EC or AP using 'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled running flashrom using the raiden_debug_spi programmer will fail. Cr50 will not forward the commands to the external AP or EC ROM, so flashrom will not be able to find the chip. The UART TX signals are now controlled by the 'ccd uart' console command instead of the 'uart' console command. The UART TX is enabled separately from CCD, because we want to be able to enable CCD while servo is connected, and having the cr50 UART TX pins wired directly to the Servo TX lines could damage both devices. The AP and EC consoles are be read only until 'ccd uart enable' is called. 'ccd uart disable' disconnects the AP and EC TX pins from the UART peripheral. When RDD becomes reliable on cr50, ccd_set_mode will select the PHY being used by the g chip USB controller. BUG=chrome-os-partner:49960,chrome-os-partner:52281 BRANCH=none TEST=manual TEST SERVO power cycle the DUT connect servo and check that the AP and EC consoles still work check that both the AP and EC can be flashed using servo. TEST SUZY Q Attach Suzy Q Connect to the all three consoles. Check that the cr50 console is in read-write mode and the EC and AP consoles are read only. Attach Servo. Verify all of the servo functionality described above still works with suzy q attached and ccd enabled. Disconnect Servo. run 'ccd uart enable' on the cr50 console and check both the AP and EC consoles can be written to. Check that the AP and EC can be programmed using the raiden_debug_spi programmer. Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342563
* cr50: dont drive UART output if servo is connectedMary Ruthven2016-05-271-12/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the power and servo connection states to enable and disable the EC and AP UART output. Contention between the cr50 and servo can prevent either uart from working, and possibly damage kevin or servo. If both UARTs are enabled, then cr50 cant know if servo is connected, so it is best if the UARTs are disabled before connecting servo. If servo is connected or if a device is not powered on then the UART output wont be enabled. The two UARTs are enabled separately and one can be enabled without the other. Any disabled UART will be monitored for a servo connection. If servo is detected, then all UARTs will be disabled. BUG=chrome-os-partner:52056,chrome-os-partner:52322 BRANCH=none TEST=manual Power on the EC only. Check only the EC UART is enabled. Without disabling the uarts power on the AP and verify both are now enabled. Turn of the AP. run 'uart enable. Verify only the EC UART is enabled. Then attach servo and check that the AP and EC UART are disabled. Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342828
* cr50: monitor the state of Servo, the EC, and APMary Ruthven2016-05-271-6/+13
| | | | | | | | | | | | | | | | | There are a couple of issues that cr50 has when it cannot know the state of servo, the EC, and the AP. This change adds support so we can detect when the AP or EC has been powered on and when servo has been connected. It uses the UART RX signals to monitor the power state of the AP and EC. The TX signals are used to monitor the state of servo. BUG=chrome-os-partner:52056,chrome-os-partner:52322 BRANCH=none TEST=verify device states are correct when the AP and EC are powered on or off and when Servo is attached or detached Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344019
* Cr50: Move board-specific rdd stuff out of chip/g/Bill Richardson2016-04-291-6/+7
| | | | | | | | | | | | | Poking GPIOs is something that belongs in board/ not chip/ BUG=none BRANCH=none TEST=make buildall; test on Kevin Change-Id: I798053c3760415ed787800d37eb81c765b826399 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341065 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: enable AP and EC UART in CCD MODEMary Ruthven2016-04-151-0/+64
When the debug cable is plugged in enable the EC and AP UART output. Disable the output when the cable is disconnected so servo can use the UARTs. BUG=chrome-os-partner:52322 BRANCH=none TEST=Verify commands can be sent to the EC UART through usb when suzy q is connected. Verify servo can interact with the EC UART when suzy q is not connected. Change-Id: I2ce0e9da464b24e295e732aa638bfc32323cc72d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338858 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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