summaryrefslogtreecommitdiff
path: root/board/cr50/rdd.c
Commit message (Collapse)AuthorAgeFilesLines
* ccdblock can block EC-CR50 communicationNamyoon Woo2020-02-201-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 'EC_CR50_COMM' a new option for ccdblock console command. It can be useful for system rescue purpose like you want to force cr50 to yield EC_UART (especially TX) port to servo. BUG=chromium:1047287 BRANCH=cr50, cr50-mp TEST=ran manually ccdblock. > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > > > ccdblock EC_CR50_COMM enable CCD ports blocked: EC_CR50_COMM > [73.386550 CCD state: UARTEC I2C SPI] > > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTEC I2C SPI CCD ports blocked: EC_CR50_COMM > > > ccdblock EC_CR50_COMM disable CCD ports blocked: (none) > [104.781623 CCD state: UARTEC+TX I2C SPI] ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) Change-Id: I7816c201054f1793906bd19d4b58755593d2fbac Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2042118 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* restructure EC-EFS moduleNamyoon Woo2020-02-201-0/+1
| | | | | | | | | | | | | | | - add ec_efs, which tracks the system boot mode. - add ec_comm.h header file for EC-EFS related functions. - revised vboot.h header file. BUG=b:141143112 BRANCH=cr50 TEST=none Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* control UART_EC RX/TX based on EC-CR50 communication statusNamyoon Woo2020-02-191-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows EC-CR50 communication to enable EC UART only if EC is on and bitbang mode is disabled. EC UART shall be enabled even when CCD_CAP_GSC_TX_EC_RX is disabled, EC UART is ccdblocked, or servo is connected. EC-CR50 comm supporting boards are supposed to have H1 dominate EC UART TX line against servo. Servo detection, which is checked every second, shall be delayed during EC-CR50 communication because EC UART TX pin (GPIO_SERVO_DETECT) is used as an output. Servo state shall be held as it was. Once EC-CR50 communication is done, the servo detection will resume or CCD state gets updated based on what it used to be before EC-CR50 communication. BUG=chromium:1035706 BRANCH=cr50 TEST=manually tested on a reworked Helios. // CCD connection only > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ecrst pulse Pulsing EC reset EC_RST_L is deasserted // Servo connection only > ccdstate AP: off AP UART: off EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: I2C CCD ports blocked: (none) Change-Id: I02667bee004d237d846393a18f247970982c71b7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023239 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* control EC USB-UART bridgeNamyoon Woo2020-02-191-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL separates the control on USB-UART bridge of EC device from EC UART control. USB-UART bridge shall be enabled if CCD connection is detected and the CCD capability is enabled. Otherwise, EC USB-UART shall be disabled. By doing so, CCD capability can be observed even when EC-CR50 communication enables EC UART. This patch increases the flash usage by 204 bytes BUG=b:148247228 BRANCH=cr50, cr50_mp TEST=ran firmware_Cr50CCDServoCap on Helios. > ccd State: Locked Password: none Flags: 0x000001 Capabilities: 0000000000000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX UARTEC USBEC CCD ports blocked: (none) > ccd State: Opened Password: none Flags: 0x800001 Capabilities: 5555454115000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC+TX CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX CCD ports blocked: (none) Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* revise the uart tx connect/disconnect functionsstabilize-quickfix-12871.27.B-cr50_stabstabilize-12871.91.B-cr50_stabstabilize-12871.65.B-cr50_stabstabilize-12871.57.B-cr50_stabstabilize-12871.253.B-cr50_stabstabilize-12871.24.B-cr50_stabstabilize-12871.103.B-cr50_stabstabilize-12871.102.B-cr50_stabstabilize-12859.B-cr50_stabrelease-R81-12871.B-cr50_stabNamyoon Woo2020-01-221-39/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reduces redundant condition checking in connecting or disconnecting UART TX. BUG=none BRANCH=cr50 TEST=manually checked ccd state with/without servo connection and/or ccd connection. [AFTER] > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX I2C SPI CCD ports blocked: EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: I2C SPI CCD ports blocked: AP EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: ignored CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* printf: Convert %T to %pTEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | In order to be more compliant to standards, and ultimately turn on compile-time printf format validation, switch the non-standard %T into %pT, which takes a pointer to a 64-bit timestamp as an argument. For convenience, define PRINTF_TIMESTAMP_NOW, which will use the current time as the timestamp value, rather than forcing everyone to pass a pointer to get_time().val. For a couple of instances, simply use CPRINTS instead. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Cq-Depend:chrome-internal:1473305 Change-Id: I83e45b55a95ea27256dc147544ae3f7e39acc5dd Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704216 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add command for forcing servo disconnectMary Ruthven2019-03-301-3/+25
| | | | | | | | | | | | | | | | | | | Early proto boards may not have the servo detection setup correctly. This change adds a method to work around this issue, so people can use the consoles even if cr50 thinks servo is connected. BUG=b:119690767 BRANCH=cr50 TEST=Use 'ccdblock ignore_servo enable' on cheza EVT verify ec uart becomes read write. Make sure uart becomes read only after 'ccdblock ignore_servo disable'. Change-Id: I9cf04b742bec166b1cf6f0b90d5fe41346769ea7 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341162 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-10/+10
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: speed up bit bang EC programmingVadim Bendebury2018-08-161-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original bit bang programming implementation attempted to provide a fully functional alternative UART interface for the case when EC programming is required, so that proper UART parity can be ensured. Come to think of it, this is not really necessary: - EC programming over UART does not require full duplex. - when EC is being programmed, the AP is held in reset, there is no need to support AP console or TPM at that time, as a result interrupts could be disabled for somewhat longer intervals. This patch introduces the following modifications: - remove uartn interface redirections - when bitbang mode is enabled regular EC console is not available. - instead of waiting for fixed amount of cycles on every bit, wait for the deadline calculated when character transmission started on tx side or when the original start bit was detected on rx side and recalculated after each clock. - when finishing receiving a character do not exit ISR right away, spin for a duration of a character polling the rx line, in case the EC keeps transmitting. The rx buffer is allocated on the ISR stack and is limited to 20 bytes, which would probably cause an overrun if this interface were used for reading flash contents from the EC. - connect USB EC console flow directly to the bit bang driver when bit bang mode is enabled and disable interrupts from the EC UART. - do not use the GPIO wrappers for bit bang interrupt processing - it takes too long. - when starting a bit bang session set the clock timer value to zero, this allows not to worry about wraparound, which will happen in almost 3 minutes, programming session should not take this long. - for the duration of 'bit bang enabled' state servo detection interrupt is disabled, it gets re-enabled after bit bang mode is disabled and servo_detect() gets to run on 1s hook. - it is not enough to check the DIOB5 pinmux state to tell if EC UART is connected or not, as this pin could be connected in bit bang mode as well; always report EC TX UART as disconnected when bit bang mode is enabled. - for the duration of bit bang programming session suppress 'aggregate' GPIO interrupts, triggered per port when GPIO interrupt is asserted. Additional speed up could be achieved if gpio driver wrappers were replaced with direct register accesses, but even as presented this patch allows to reliably program the STM32 on Scarlet at 57600 baud, which is 6 times faster than the current state. BRANCH=cr50, cr50-mp BUG=b:62539385 TEST=with some flash_ec modifications which make sure that bit bang mode is enabled properly (fixing timing of setting boot0 and resetting the EC), Scarlet device EC can be reprogrammed at 57600 baud 100 times in a row with and without logic analyzer connected to the EC UART pins. Change-Id: I2e3520f158943323cb015fa18650a7e177f03cc3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1171221 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: bitbang does not need to support multiple UARTs.Vadim Bendebury2018-08-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The ability to support multiple UART interfaces complicates bit bang EC programming implementation without bringing any real benefits - we are not going to have to bit bang more than one UART interface in real Chrome OS hardware. In preparation in introducing bit a bang speed up patch let's change the API to not require passing the UART number to bit bang functions. To keep servod happy for now, the 'bitbang' cli command is being left unchanged and as such still requires to pass the UART number, it is just ignored. BRANCH=cr50, cr50-mp BUG=b:62539385 TEST=just verified that Cr50 still builds, the real test is done in the speed up patch. Change-Id: Icd5476ad777791ca483844cbf49316ddf58f03a3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1171220 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: disable ccd ports when ext ccd is disabledMary Ruthven2018-07-251-1/+6
| | | | | | | | | | | | | | | | | | CCD I2C, SPI, and UART capabilities should all be disabled when ccd ext is disabled. There is no need for cr50 to monitor these while noone is using ccd. BUG=b:111701874 BRANCH=cr50 TEST=disable ccd and check ccdstate. Make sure no state flags are set. Enable ccd and verify ccdstate flags are then enabled. Change-Id: Ia4f4208c6c139f912a632d1592d9adab7fa9f3e6 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1147876 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "cr50: add support for enabling terminations on ap suspend"Mary Ruthven2018-05-171-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit cfcac78e626ce08ccc1c45c91c61127b6088e80f. Reason for revert: Removing all s3 termination support. It's not necessary and it causes scarlet to boot into recovery. Original change's description: > cr50: add support for enabling terminations on ap suspend > > rk3399 systems need terminations on the SPI signals in S3 and all other > low power states. Add support for enabling the pulldowns and pullups on > the correct pins. > > With this change, if BOARD_NEEDS_S3_TERM is set in the board properties, > cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown > on all of the SPS signals. To keep the pulldowns from interfering with > the sps peripheral, s3_term will also disable the input for those > signals. > > BUG=b:62200096 > BRANCH=cr50 > TEST=Flash onto bob. Make sure cr50 enables and disables terminations > when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do > anything. > > Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883 > Signed-off-by: Mary Ruthven <mruthven@google.com> > Reviewed-on: https://chromium-review.googlesource.com/991338 > Commit-Ready: Mary Ruthven <mruthven@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Reviewed-by: Randall Spangler <rspangler@chromium.org> Bug: b:62200096 Change-Id: I00c5051a48d4578badf9ce6622dea1af9903f4fd Reviewed-on: https://chromium-review.googlesource.com/1062687 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add support for enabling terminations on ap suspendMary Ruthven2018-04-131-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | rk3399 systems need terminations on the SPI signals in S3 and all other low power states. Add support for enabling the pulldowns and pullups on the correct pins. With this change, if BOARD_NEEDS_S3_TERM is set in the board properties, cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown on all of the SPS signals. To keep the pulldowns from interfering with the sps peripheral, s3_term will also disable the input for those signals. BUG=b:62200096 BRANCH=cr50 TEST=Flash onto bob. Make sure cr50 enables and disables terminations when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do anything. Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/991338 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: create ap_uart state machineMary Ruthven2018-02-021-2/+3
| | | | | | | | | | | | | | | | | | | | | | | This change creates a state machine to handle ap uart detection. It removes all of the ap_uart stuff from ap_state.c and moves it to ap_uart_state.c. All boards will now use ap_uart to enable/disable ap uart and tpm_rst_l to detect the ap state. Separate ap uart detection from ap detection, so we can disable the ap uart without enabling deep sleep. If the ap is in S3 on ARM devices, Cr50 wont be in deep sleep, but the AP UART RX signal wont be pulled up. In this case we need cr50 ap rx to be disabled and deep sleep to be disabled. BUG=b:35647982 BRANCH=cr50 TEST=run firmware_Cr50DeviceState on scalet and electro Change-Id: I81336a9e232df8d44b325eef59327a1c06a80cba Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/884307 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: mark ccdstate console command safeMary Ruthven2017-12-051-3/+3
| | | | | | | | | | | | | | | | ccdstate just prints state. It is very useful for debugging ccd/servo contention issues. This change makes it a safe command so it is accessible even when the console is locked. BUG=none BRANCH=cr50 TEST=make buildall Change-Id: I2e754f5978c83fcaca737e7a590dcf5ee445522c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/809864 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add ccdblock command to block portsRandall Spangler2017-09-291-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when CCD is opened, there is no way to disable the EC and/or AP UARTs. But if there is some problem with the EC and/or AP, and their UARTs are spamming interrupts, it can make debugging more difficult. If servo detection malfunctions, then CCD may drive the ports and interfere with servo. Add a new ccdblock command to disable the AP UART, EC UART, or any ports shared with servo, until the next cr50 reboot. BUG=b:65639347 BRANCH=cr50 TEST=manual with CR50_DEV=1 image, AP/EC powered on, suzyq connected ccdblock --> (none) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI ccdblock AP on ccdstate --> UARTEC+TX I2C SPI ccdblock EC on ccdstate --> I2C SPI ccdblock -> AP EC ccdblock AP off ccdstate --> UARTAP+TX I2C SPI ccdblock EC off --> (none) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI ccdblock SERVO on ccdstate --> UARTAP UARTEC ccd lock ccdblock AP on --> access denied Change-Id: I3dcc8314fc98a17af57f2fe0d150ecd1a19ccf52 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693041 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Defragment codeRandall Spangler2017-09-091-107/+7
| | | | | | | | | | | | | | | | | For historical reasons, CCD, reset, and power button control were scattered around several files. Consolidate the code in more sensible (in retrospect) places. No functional changes, just moving code. BUG=none BRANCH=cr50 TEST=make buildall; boot cr50 Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/653766 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Consolidate CCD device enableRandall Spangler2017-09-061-76/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage their own enabling and disabling of the ports (UART, SPI, etc.) This is tricky because the rules for when ports should be enabled are non-trivial and must be applied in the correct order. In additionl the changes all need to be serialized, so that the hardware ends up in the correct state even if multiple state machines are changing simultaneously. Consolidate all of that into chip/g/rdd.c. The debug command for it is now 'ccdstate', which just prints the state machines. This will allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd open', etc. Also include UART bit-banging into that state which must be consistent. Previously, it was possible for bit-banging to leave UART TX connected, instead of returning it to the previous state. Use better names for CCD config fields for UART. I'd had them backwards. BUG=b:62537474 BRANCH=cr50 TEST=manual, with a CR50_DEV=1 image 1) No servo or CCD Pull SERVO_DETECT low (disconnected) Pull CCD_MODE_L high (disabled) Pull EC_DETECT and AP_DETECT high (on) Reboot. RX is enabled even if cables are disconnected so we buffer. ccdstate -> UARTAP UARTEC Pull EC_DETECT low. ccdstate -> UARTAP Pull EC_DETECT high and AP_DETECT low. ccdstate -> UARTEC Pull AP_DETECT high. ccdstate -> UARTAP UARTEC 2) Servo only still allows UART RX Pull SERVO_DETECT high (connected). ccdstate -> UARTAP UARTEC 3) Both servo and CCD prioritizes servo. Pull CCD_MODE_L low (enabled). ccdstate -> UARTAP UARTEC Reboot, to make sure servo wins at boot time. ccdstate -> UARTAP UARTEC Bit-banging doesn't work when servo is connected. bitbang 2 9600 even -> superseded by servo bitbang -> disabled ccdstate -> UARTAP UARTEC 4) CCD only allows more ports and remembers we wanted to bit-bang Pull SERVO_DETECT low. ccdstate --> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate --> UARTAP+TX UARTEC+TX I2C SPI Reboot and see we don't take over servo ports until we're sure servo isn't present. ccdstate --> UARTAP UARTEC (for first second) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that) 5) Bit-banging takes over ECTX bitbang 2 9600 even bitbang -> baud rate 9600, parity even ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI 6) Permissions work. Allow easy access to full console and ccdopen: ccdset OpenNoTPMWipe always ccdset OpenNoLongPP always ccdset GscFullConsole always Default when locked is full AP UART EC RO, no I2C or SPI ccdlock ccdstate -> UARTAP+TX UARTEC No EC transmit permission means no bit-banging bitbang 2 9600 even bitbang -> disabled ccdstate -> UARTAP+TX UARTEC But it remembers that we wanted to ccdopen ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI Try turning on/off permissions ccdset UartGscTxECRx always ccdlock ccdstate -> UARTAP+TX UARTEC+TX No read means no write either ccdset UartGscRxECTx ifopened ccdlock ccdstate -> UARTAP+TX ccdopen ccdset UartGscRXAPTx ifopened ccdlock ccdstate -> (nothing) Check AP transmit permissions too ccdopen ccdset UartGscRxAPTx always ccdset UartGscTxAPRx ifopened ccdlock ccdstate -> UARTAP Check I2C ccdopen ccdset I2C always ccdlock ccdstate -> UARTAP I2C SPI port is enabled if either EC or AP flash is allowed ccdopen ccdset flashap always ccdlock ccdstate -> UARTAP I2C SPI ccdopen ccdset flashec always ccdset flashap ifopened ccdlock ccdstate -> UARTAP I2C SPI Back to defaults ccdoops Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615928 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Use own CCD EXT state machineRandall Spangler2017-09-011-21/+45
| | | | | | | | | | | | | | | | | | | | | | | | | The state machine in common/case_closed_debug.c only handles a subset of what we need to do for Cr50 external case closed debugging, and also supports a 'partial' CCD state that doesn't exist for Cr50. Move the few lines of code from that we actually need into our file. BUG=none BRANCH=cr50 TEST=manual Assert CCD_MODE_L See 'CCD EXT enable' Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint Confirm firmware update over USB works Deassert CCD_MODE_L See 'CCD EXT disable' Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint Confirm firmware update over USB does not work (can't find device) Change-Id: Id96f2770632839a9690740ece54bc2eb71d39a38 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/647909 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: use ccd_ext_is_enabled() instead of ccd_get_mode()Randall Spangler2017-09-011-9/+5
| | | | | | | | | | | | | | | | | | | Currently, only usb_pd_protocol.c cares about the actual ccd mode (disabled/partial/enabled). Everything else just cares whether it's enabled or not. So promote the boolean ccd_is_connected() from board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to match the new nomenclature (since 'CCD' itself is now too overloaded). This will make it easier to handle CCD state directly in board/cr50 after we split it from common/case_closed_debug.c BUG=none BRANCH=cr50 TEST=make buildall; boot cr50; make sure USB endpoints still work Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648212 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: Move Rdd keepalive to chip driverRandall Spangler2017-09-011-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | Previously, chip/g/rdd provided a method for an external console command to override the Rdd cable detect state. But since we'll be refactoring the 'ccd' command, it's tidier to move this to a console command inside the rdd driver itself. BUG=none BRANCH=cr50 TEST=manual, with no debug cable present rdd enable -> Rdd connect rdd -> keepalive rdd disable rdd -> connected (hasn't had a chance to run state machine) (wait <1 sec) rdd -> debouncing (wait 1 sec) -> Rdd disconnect Change-Id: I141eedf8070b4ad2c96cc5a364f4e37dc29bed70 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/647991 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Split servo state machine into its own fileRandall Spangler2017-09-011-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the last state machine which used common/device_state.c. But servo is more complex than that, because it needs to differentiate state-isn't-known (debouncing) from state-isn't-knowable (Cr50 driving EC TX), so it's cleaner to split it out the way we did AP and EC state machines in previous CLs. BUG=b:35587387 BRANCH=cr50 TEST=manual with CR50_DEV=1 build // Test detect at boot, even with CCD connected Pull CCD_MODE_L low Pull DETECT_SERVO high Pull DETECT_EC high reboot -> 'Servo connect' // CCD is not driving EC UART TX ccd -> EC on, Servo connected, CCD enabled, EC UART RX // When servo disconnects CCD can drive EC TX Pull DETECT_SERVO low --> 'Servo disconnect' ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX // Can't detect servo reconnecting if we're driving EC TX Pull DETECT_SERVO high --> (no change) ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX // When we stop driving EC TX, can redetect servo Pull EC_DETECT low --> See 'EC off', 'Servo connected' ccd -> EC off, Servo connected, CCD enabled, EC UART disabled // Test debouncing at boot Pull DETECT_EC high Pull DETECT_SERVO low Pull CCD_MODE_L high reboot Within 1 sec, pull DETECT_SERVO high --> 'Servo connected' // Test debouncing after boot Pull DETECT_SERVO low then high < 1 sec --> (no message) Change-Id: I964bd36c35f52c8ef7b3ea3793b6e0764e93587c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/636047 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Split AP state machine into its own fileRandall Spangler2017-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the AP state machine out, the way we split out the EC state machine in the previous CL. BUG=b:35587387 BRANCH=cr50 TEST=manual, with Cr50 strapped (or hard-coded) not to use platform reset and not to use TPM reset to detect the AP: Pull CCD_MODE_L low, so Cr50 detects/enables CCD Pull AP_DETECT high. Pull INT_AP_L low (with resistor). Pull AP_DETECT low --> See 'AP off' message gpioget --> INT_AP_L=0 ccd --> AP UART disabled Pull AP_DETECT high --> See 'AP on' message gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Pull AP_DETECT low for <1 sec then back high (don't see AP off/on message) gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Reboot with AP_DETECT still low -> AP off at 1 second Reboot with AP_DETECT still low and then assert AP_DETECT within a second -> AP on immediately Repeat with Cr50 strapped/hard coded to use platform reset, but using TPM_RST_L instead of AP_DETECT. Note that this will also show TPM reset debugging output when TPM_RST_L is asserted. Change-Id: Ief9e4e5f2585ff925de1595cc8fbd5306c94a806 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/634248 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Only enable UART RX when EC/AP is onRandall Spangler2017-08-301-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, some code paths such as CCD permissions change could result in enabling EC or AP UART RX when the EC or AP is off. This could result in interrupt storms. BUG=none BRANCH=cr50 TEST=manual // Initial conditions Assert CCD_MODE_L Deassert DETECT_SERVO // Both RX and TX disabled when processor turns off // and re-enabled when it turns back on Deassert DETECT_EC ccd -> EC UART disabled Assert DETECT_EC ccd --> EC UART RX+TX Deassert DETECT_AP ccd -> AP UART disabled Assert DETECT_AP ccd --> AP UART RX+TX // TX disabled when CCD disabled Deassert CCD_MODE_L ccd --> EC UART RX, AP UART RX Assert DETECT_SERVO ccd --> EC UART RX, AP UART RX // Don't enable TX when detecting EC, if servo is connected Deassert DETECT_EC ccd -> EC UART disabled Assert DETECT_EC ccd --> EC UART RX // Don't enable TX when detecting CCD, if servo is connected Assert CCD_MODE_L ccd --> EC UART RX, AP UART RX // When servo disconnects, enable TX if CCD is connected Deassert DETECT_SERVO ccd --> EC UART RX+TX, AP UART RX+TX Change-Id: Icb144c23e949afb0384c242965aa729b078b03eb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642349 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Let state machines print their own statesRandall Spangler2017-08-291-3/+4
| | | | | | | | | | | | | | | | | | | Add a function to translate device_state enum into a string, then use it for printing the ec and RDD state. Refactor ec_state so that all state transitions go through a set_state() function, which makes it easier to turn on debugging all state transitions. That's normally not compiled in because it would be spammy during debouncing. BUG=none BRANCH=cr50 TEST=ccd command prints EC and RDD states Change-Id: Ie7bc56c7b66beee23d1d1989711c640e5e39ce43 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642121 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Split EC state machine into its own fileRandall Spangler2017-08-251-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the EC state machine out, the way we split out BattPrsnt and CCD_MODE. BUG=b:35587387 BRANCH=cr50 TEST=manual Pull CCD_MODE_L high, so Cr50 detects/enables CCD Pull EC_DETECT high. reboot -> 'EC RX only', then 'EC on' at 1 second Pull EC_DETECT low --> See 'EC off' message ccd --> EC UART disabled Pull EC_DETECT high --> See 'EC on' message ccd --> EC UART RX+TX Pull EC_DETECT low for <1 sec then back high (don't see EC off/on messages) ccd --> EC UART RX+TX Reboot with EC_DETECT still low -> EC off at 1 second Reboot with EC_DETECT still low and then assert EC_DETECT within a second -> EC RX only, then EC connect at 1 second. Change-Id: I71687e651d625cadd656934f4cb2bbadc0b58816 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619750 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Refactor Rdd state machineRandall Spangler2017-08-231-53/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to mirror Rdd detect into CCD_MODE_L and handle keepalive is now inside chip/g/rdd.c It uses a HOOK_SECOND state machine similar to what's coming for EC/AP/Servo. This also removes the explicit 'ccd enable' / 'ccd disable' commands, since they'd be overridden by the HOOK_SECOND handler. If you need to force CCD enabled, use 'ccd keepalive enable'. BUG=b:64799106 BRANCH=cr50 TEST=With a CR50_DEV=1 images: Disconnect CCD cable (pull RDCC1 and RDCC2 outside 0.2-2.0V) gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Connect CCD cable --> see 'Debug accessory connected' gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Briefly disconnect and reconnect CCD cable --> No debug output gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Disconnect CCD cable and wait a second --> 'disconnected' gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Force CCD_MODE_L = 0 externally, wait a second gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Stop forcing CCD_MODE_L externally, wait a second gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled ccd keepalive enable gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled ccd keepalive disable gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Change-Id: I65110b45e76f60390828e0fbbac8f36fc2cc9b37 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619393 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Remove BOARD_AP_USB propertyRandall Spangler2017-08-171-11/+0
| | | | | | | | | | | | | | | | | | | We previously disabled the USB PHY to the AP. But the BOARD_AP_USB property lingered on. Remove the property. Also clean up the idle task deciding when to do utmi wakes. With the AP USB connection disabled, that's only necessary when the debug cable is attached, so we can check that explicitly. BUG=none BRANCH=cr50 TEST=make buildall; boot CR50_DEV=1 image Change-Id: If81a7bcfe845d9d70dcc7e16239244a4f5f2427b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616301 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Add helper functions for device-is-enabledRandall Spangler2017-08-171-7/+7
| | | | | | | | | | | | | | | | | | | | A subsequent CL will massively refactor the device state machines. Add the helper functions which will be used by that CL, so that the refactoring touches fewer files. No change in functionality. BUG=none BRANCH=cr50 TEST=make buildall; boot cr50 with a CR50_DEV=1 image Change-Id: I3499d45e93fa15b6de9c04ce398d1c5bfbbc01e9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616300 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Merge CCD device handling to rdd.cRandall Spangler2017-08-081-8/+8
| | | | | | | | | | | | | | | | | | | | | The device_state module is used for debouncing GPIO inputs to determine device sstate. It was overkill for managing the CCD cable (RDD) attach/detach state, and split that handling between 3 files (board.c, rdd.c, device_state.c). Move all of that logic into rdd.c so it's easier to maintain. BUG=none BRANCH=cr50 TEST=manual plug in CCD cable (or ground DIOM1) ccd command reports cable connected and AP UART TX+RX unplug CCD cable (or un-ground DIOM1) ccd command reports cable disconnected and AP UART disabled Change-Id: Id8fcd3a51605ae7a4843668ea18dd0ef84aceb2c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/604499 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: stop using AP PHYMary Ruthven2017-08-011-55/+0
| | | | | | | | | | | | | | | Remove the code switching between PHY0 and PHY1. We now only use the CCD PHY on all boards. BUG=b:36488273 BRANCH=cr50 TEST=ccd works fine. cr50 usb doesn't show up on the AP. You cannot switch the PHY on cr50. Change-Id: I6ff641af9d7129daa8592f952f9df97c3862395b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/595201 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: CCD V1 controls UART accessRandall Spangler2017-08-011-19/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP and EC UART now use the CCD V1 capabilities to determine when access is allowed. Transmit to AP and EC can be toggled independently from read access to output from those UARTs. Note that disabling read access disables both transmit and receive. That is, it's not possible to set a UART where transmit is allowed but receive isn't. Why would you want to do that, anyway? See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 ccdoops ccdset cr50fullconsole always -> so we can use ccd command for testing ccd -> AP RX+TX, EC RX+TX ccdset uartecrx unlesslocked ccdset uartectx ifopened ccdset uartaprx always ccdset uartaptx unlesslocked ccdunlock ccd -> AP RX+TX, EC RX ccdlock ccd -> AP RX, EC disabled ccdoops ccdset cr50fullconsole always ccd -> AP RX+TX, EC RX+TX ccdset uartaprx ifopened ccdlock ccd -> AP disabled, EC RX Change-Id: I55db5897bb52cd60658ab221eadf5c59fc86744a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/595196 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_i2c: Fail if board I2C bridge is disabledRandall Spangler2017-07-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb_i2c_board_is_enabled(). On Cr50, this is now also connected to the I2C CCD capability. The USB-I2C bridge can only be used when the capability is available. On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is a no-op, add a dummy implementation which always returns true. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 Connect host PC to dev board USB port On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x8001 ccdoops --> reset I2C config ccd i2c disable --> I2C disabled On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x0006 ccd i2c enable --> I2C enabled ccdunlock --> I2C disabled ccdoops --> I2C enabled ccdset i2c unlesslocked ccdlock --> I2C disabled ccdunlock --> I2C enabled Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590577 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Rename uartn_enabled() to uartn_tx_is_connected()Randall Spangler2017-07-291-7/+9
| | | | | | | | | | | | | | | Because that's what it means. That is, it reports the state of uartn_tx_connect(), not uartn_enable(). No functional changes; just a rename. BUG=none BRANCH=cr50 TEST=make buildall -j Change-Id: Ie2273b277bd73a40307be7ec215417c1225cd567 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590859
* cr50: protect EC/AP reset commands using CCD V1Randall Spangler2017-07-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sysrst and ecrst commands are now protected by the RebootECAP capability. They can print the state of the reset lines when the capability is not allowed, but can only change the state or pulse the reset lines when the capability is allowed. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build: ccdoops --> reset CCD config and go to Opened state ecrst pulse --> works sysrst pulse --> works ccdunlock ecrst pulse --> access denied sysrst pulse --> access denied ecrst --> prints state sysrst --> prints state ccdoops ccdset rebootecap unlesslocked ccdunlock ecrst pulse --> works sysrst pulse --> works Change-Id: Ia9ebe67bdc1e85129051caf94f20fb2fb84b76da Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590071 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Have CCD_MODE_L respect "ccd keepalive".Aseda Aboagye2017-06-011-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | If CCD was set to the "keepalive" mode, removing the debug accessory would cause the CCD_MODE_L pin to be pulled high, ignoring the keepalive state. CCD was still kept alive, but the state reflected on the pin didn't indicate so. This commit changes the behaviour such that the CCD_MODE_L pin is set up as an input only when CCD keepalive is not enabled. BUG=None BRANCH=cr50 TEST=Plug in debug accessory and remove debug accessory. Verify that CCD_MODE_L is high after removal. TEST=Enable ccd keepalive. Remove debug accessory. Verify that CCD_MODE_L is still low. Change-Id: I407994d5c394a717d6e1a87f283f6441bd26bf55 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/520603 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Only drive CCD_MODE_L when in CCD mode.Aseda Aboagye2017-03-071-25/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the behaviour of handling the CCD_MODE_L pin. When Cr50 is not in CCD mode, it will stop driving the pin and turn it into an input. This allows the pin to be driven by the EC. Cr50 will then poll the CCD_MODE_L pin to see when it is pulled low and then enter CCD mode. Once the pin is deasserted, CCD mode is disabled. However, when Cr50 itself makes the decision to enter CCD mode, it changes the pin from an input to an output and drives the pin low. NOTE: The rdd interrupt does not directly trigger CCD mode, but now drives the pin low. A side-effect of the pin going low is that CCD is enabled. Once Cr50 decides to leave CCD mode, it then reconfigures the pin to be setup as an input again. CQ-DEPEND=CL:448988 BUG=b:35804738 BRANCH=cr50 TEST=Flash dev board, use `ccd` console command to both enable and disable CCD. Verify that when CCD is enabled, the state of DIOM1 does not disable CCD. Verify that when CCD is disabled, pulling DIOM1 low enables CCD. Letting it float disables CCD. TEST=Verify that CCD mode is reflected in the device state. Change-Id: I44645f28b362977ca6a502b646e4f4ff1a7430c7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/448161 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: enable utmi wakeupsMary Ruthven2017-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | We had disabled wakeups on the AP phy when we were running on gru, because the AP phy was not in use. We never changed that for reef, so UTMI wakeups were disabled even when the AP USB was supposed to be enabled. After Cr50 went to sleep any usb transactions would drop bits, because Cr50 wouldn't notice anything was happening until it woke up on one of the HOOK_TICK events. This change reenables UTMI wakeups on boards with AP usb. It writes 1 to USB_PCGCCTL_STOPCLK. This makes the controller disable the PHY clock whenever it detects a usb suspend. When it resumes out of suspend, this bit has no effect. BUG=b:35774906 BRANCH=cr50 TEST=Boot up reef. Wait until cr50 goes to sleep run 'usb_updater -f' and verify that it runs successfully. Make sure deep sleep still works Change-Id: I54bd866111b5c9b5738575f23757e0cbe4907ec4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448988 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Have INAs and I2Cm enabled when rdd is attachedScott2017-02-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INAs are only used for development and testing purposes. Therefore, the 3.3V rail to the INAs is off by default and the I2Cm module is not enabled. Enabling INA power and connecting the I2Cm module was done at the beginning of each USB to I2C request. The problem with this approach is that INA measurments didn't always succeed due to not enough time for the INAs to initialize. Rather than add some arbitrary delay, it is better to tie the INAs to when rdd is attached/detached. It is only when rdd is attached that the INAs will be accessed, so there is no need to enable/disable for each individual I2C transaction. This CL ties the enabling/disabling of the INA and I2Cm module to the rdd state. This change makes the previous use of usb_i2c_board_enable() and usb_i2c_board_disable() obslete. BRANCH=none BUG=chrome-os-partner:62375 TEST=manual Connect servo with suzyq connected: sudo servod -p 0x5014 -b eve -c eve_r0_inas.xml Then execute single INA reads dut-control pp3300_dx_edp_mv and verify that it returns meaningful numbers. Without this CL single reads via dut-control would always return 0. Change-Id: I799552bfd0701efd1828a0d720ac2a6cedee5ca1 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/436864 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add command to enable ccd indefinitelyMary Ruthven2017-01-201-18/+40
| | | | | | | | | | | | | | | | | | | For FAFT or debugging purposes we may want to leave ccd enabled no matter what the voltages on the CC lines are. This change adds a 'ccd force enable' which will keep ccd enabled until 'ccd disable' is run. BUG=chrome-os-partner:61701 BRANCH=none TEST=Plug in suzyq. Run 'ccd force enable'. Disconnect suzyq and on the cr50 uart run 'ccd' to verify ccd is still enabled. Make sure the other ccd commands work ok. Change-Id: Ia7087ade3070a1320a74b985f4699533ecc396ef Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/427346 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: extend sysrst pulse to 20msMary Ruthven2017-01-181-3/+10
| | | | | | | | | | | | | | | | Increase the sysrst pulse to be long enough to reset the AP. This change increases it to 20ms by default, but adds a parameter to set the interval in the sysrst pulse command. BUG=none BRANCH=none TEST='sysrst pulse' will cause the AP to reset and 'sysrst pulse 1000' shows that sys_rst_l is asserted and 1 second later it is deasserted. Change-Id: I66b0d627480852dc166f62dc0fddd02f094b6162 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/429150 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: keep board properties related code in board.cVadim Bendebury2016-12-201-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are plans to extend use of the LONG_LIFE_SCRATCH1 register for other purposes than keeping board properties. Just as the board properties, the new use is also very board specific. This patch moves the board properties code from chip/g to board/cr50, where it belongs. Instead of reading board properties bitmap and checking if various bits are set, api functions are now provided to allow determining various properties settings without actually looking at the properties bitmap. CQ-DEPEND=CL:*313057 BRANCH=none BUG=chrome-os-partner:58961 TEST=verified that both Gru and Reef boot with the new image, additionally, on Reef confirmed that it is possible to communicate with the H1 over USB, and that plt_reset signal is handled properly. Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547 Reviewed-on: https://chromium-review.googlesource.com/422081 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: remove the pull down on uart2 txMary Ruthven2016-11-211-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | The pulldown on diob5 is used to detect when servo is detached. It is unnecessary during deep sleep and when the EC console is active because servo detection is disabled. Having the pull-down enabled during these times can increase power consumption. This change disables the pulldown when the EC console and deep sleep are enabled. It also disables the diob5 input during deep sleep. BUG=chrome-os-partner:60020 BRANCH=none TEST=manual Disconnect servo Use the suzyq consoles to turn off the AP. Enable deep sleep. Measure the power consumed by vddiob and make sure it is around 0.3mW when the EC is in hibernate and when it is not. Change-Id: I8a653c28800cfbeeb1b4b8598d166846124c6b53 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/412940 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Stop disabling the AP/EC uart when ccd is disabledMary Ruthven2016-11-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This change removes the uart disable in rdd_disconnect. It used to be necessary because we used to disable device state detection in rdd_disconnect. Without device state detect we had to disable the AP and EC uart to make sure there were no interrupt storms. Now we keep device state detection running all the time. It handles enabling/disabling the AP and EC uart when it senses the RX signals aren't pulled up. UART is only enabled/disabled when cr50 detects that the AP or EC state changed from off to on or on to off. If the debug cable is detached and then reattched the uart will be disabled on detach, but it won't be reenabled until the AP/EC are rebooted. BUG=chrome-os-partner:58222 BRANCH=none TEST=Detach and reattach suzyq without rebooting the AP or EC and make sure both consoles come back after reattaching the cable. Change-Id: Id104e12dc533e8d7047f32aebd41abd1c959d267 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410269 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: add usb i2c driverMary Ruthven2016-10-141-47/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is based off of the protocol in the stm32 directory. We should unify these implementations and the other ccd endpoints at some point. Right now I though that I should keep the implementation the same as the other g chips ccd drivers. BUG=chrome-os-partner:57059 BRANCH=none CQ-DEPEND=CL:390015 TEST=manual download the servo patch and run 'sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml' Test the usb i2c bridge by running 'dut-control | grep pp' Attach servo and verify cr50 will not enable i2c Change-Id: I0f72671505f5451a960d3baea4b2c34b6910d892 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388896 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* g: use devid 0 and 1 to create a serial numberMary Ruthven2016-10-111-1/+1
| | | | | | | | | | | | | | | | | To be able to identify different cr50 devices connected to the same machine we need a serial number. This change uses dev id 0 and 1 to come up with one. BUG=chrome-os-partner:56641 BUG=chrome-os-partner:58342 BRANCH=none TEST=lsusb -vd 18d1:5014 | grep iSerial shows different numbers for different devices. Verify when ccd is disabled the serial number is 0. Change-Id: I85c54af4a21bdfd0542019c02aa8420d9a879fae Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395633 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add press and release options to powerbtn commandMary Ruthven2016-10-111-7/+25
| | | | | | | | | | | | | | | | | This change adds options to the powerbtn console command to press and release the power button. BUG=chrome-os-partner:58123 BRANCH=none TEST=manual 'powerbtn press' force a power button press 'powerbtn release' release the power button. This will not override the signal if the button is physically pressed. Change-Id: I52631d30dbae874ba6637f728cb6e435cb626e12 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/396207 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: I2CM: Enable i2c master for accessing INA chipsScott2016-10-111-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On both Reef and Gru there are INA (shunt bus voltage monitor) ICs connected to the Cr50 I2C master bus. The use case for these chips is in a lab setting using case closed debugging. Power to the INA chips is controlled by a separate Cr50 gpio signal. By default, the INAs are powered off and the I2C master bus is not connected. A function ina_connect() is provided which needs to be called prior to attempting to access the INAs via I2C. BRANCH=none BUG=chrome-os-partner:57059 TEST=manual Tested both Reef and Gru. Verified that console command 'ccd ina on|off' works as expected and that can repeatedly read registers on the INA using the following command "i2cxfer r16 0 0x40 0". Read 0x2771 [10097] which is the default value. In addition wrote register 14 (bits 15:1 are writeable) and verified the value was able to read the value back which was written. Change-Id: I670f7897555dae29642264531599dc4471c52bbd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/394168 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: ecrst and sysrst commands should show stateBill Richardson2016-10-071-21/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of the ecrst and sysrst commands don't have a way to show the state of the EC_RST_L and SYS_RST_L. This tweaks the commands to accept an optional "pulse" argument in addition to the boolean arg, which will assert, pause, then deassert the relevant signal. With no args at all, the current signal state is shown. BUG=chrome-os-partner:58123 BUG=chrome-os-partner:56835 BRANCH=none TEST=manual sysrst pulse resets the AP sysrst on/off asserts/deasserts SYS_RST_L sysrst displays the current SYS_RST_L state ecrst pulse resets the EC (and AP) ecrst on/off asserts/deasserts EC_RST_L ecrst displays the current EC_RST_L state Change-Id: I8e1c9a577afd9ed9e770f1b3f5c0a69e4607de66 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395587 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: add console commands to have parity with servoMary Ruthven2016-10-051-0/+76
| | | | | | | | | | | | | | | | | | | | | | This change adds apreset, ecreset, ec_rst, sys_rst and powerbtn options to the ccd console command. BUG=chrome-os-partner:58123 BUG=chrome-os-partner:56835 BRANCH=none TEST=manual sysrst resets the AP sysrst on/off controls SYS_RST_L ecrst resets the ec ecrst on/off controls EC_RST_L powerbtn 500 will simulate a power button press for 500 ms Change-Id: I89adc88eb407730c9d57811a07bfef8fcf63c5b9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393809 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
View Lorry Controller Status