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path: root/board/cr50/scratch_reg1.h
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* scratch_reg: reorganize BOARD_ALL_PROPERTIESMary Ruthven2019-03-061-5/+11
| | | | | | | | | | | | | | | | List one board property per line and alphabetize the list, so the BOARD_ALL_PROPERTIES definition is more readable. BUG=none BRANCH=cr50 TEST=none Change-Id: Ic0a8d83b380c4f61c89c54535a1c350daf4ae39f Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1481656 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add no ina support board propertyMary Ruthven2019-03-061-1/+7
| | | | | | | | | | | | | | | | | | Mistral also uses the ina pins as gpios. Add a board property for no ina support. Use that instead of the closed source set board property for the usb_i2c_enable code. BUG=b:124949444 BRANCH=cr50 TEST=flash on mistral. Make sure EN_PP3300_INA_L isn't asserted when ccd is enabled. Change-Id: If06a65bc4a1ef7b374a44fc53d65ea5daed336df Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1480711 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: add board_closed_loop_reset propertyMary Ruthven2019-01-311-1/+7
| | | | | | | | | | | | | BUG=b:123544145 BRANCH=cr50 TEST=none Change-Id: If9b12685f7f70f0653d137bbfa15f6a6232343e0 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1443868 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add board strapping options for Sarien/ArcadaKeith Short2018-11-161-2/+19
| | | | | | | | | | | | | | | | | | | | | Add 2 new board properties: * BOARD_WP_DISABLE_DELAY - forces an additional delay after detecting battery removal before disabling write protect * BOARD_CLOSED_SOURCE_SET1 - enables custom CR50 options for Sarien/Arcada boards that use a closed source EC Add Sarien/Arcada to board_cfg_table. BUG=b:118688072 BRANCH=none TEST=make buildall, flashed RW Cr50 firmware onto Careena board and verified boots new version Change-Id: Ic9ffdf4861c2239a1e68eb682152c70fb1f9bfc3 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1310093 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: enable ITE CCD programmingVadim Bendebury2018-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support of ITE EC programming by Cr50. ITE EC sync sequence generator implementation is being added to the image, I2C RX and TX queue sizes are increased to be able to accommodate messages sent during programming session. Board level callback function is provided to request ITE SYNC sequence generation on the next boot, and to reset the H1 with a 10 ms delay, necessary for CCD host USB communications to quiesce. Board startup code is modified to when requested invoke function generating ITE SYNC sequence early in the boot before jitter configuration is locked. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263898 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Revert "cr50: add support for enabling terminations on ap suspend"Mary Ruthven2018-05-171-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit cfcac78e626ce08ccc1c45c91c61127b6088e80f. Reason for revert: Removing all s3 termination support. It's not necessary and it causes scarlet to boot into recovery. Original change's description: > cr50: add support for enabling terminations on ap suspend > > rk3399 systems need terminations on the SPI signals in S3 and all other > low power states. Add support for enabling the pulldowns and pullups on > the correct pins. > > With this change, if BOARD_NEEDS_S3_TERM is set in the board properties, > cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown > on all of the SPS signals. To keep the pulldowns from interfering with > the sps peripheral, s3_term will also disable the input for those > signals. > > BUG=b:62200096 > BRANCH=cr50 > TEST=Flash onto bob. Make sure cr50 enables and disables terminations > when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do > anything. > > Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883 > Signed-off-by: Mary Ruthven <mruthven@google.com> > Reviewed-on: https://chromium-review.googlesource.com/991338 > Commit-Ready: Mary Ruthven <mruthven@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Reviewed-by: Randall Spangler <rspangler@chromium.org> Bug: b:62200096 Change-Id: I00c5051a48d4578badf9ce6622dea1af9903f4fd Reviewed-on: https://chromium-review.googlesource.com/1062687 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add support for enabling terminations on ap suspendMary Ruthven2018-04-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | rk3399 systems need terminations on the SPI signals in S3 and all other low power states. Add support for enabling the pulldowns and pullups on the correct pins. With this change, if BOARD_NEEDS_S3_TERM is set in the board properties, cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown on all of the SPS signals. To keep the pulldowns from interfering with the sps peripheral, s3_term will also disable the input for those signals. BUG=b:62200096 BRANCH=cr50 TEST=Flash onto bob. Make sure cr50 enables and disables terminations when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do anything. Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/991338 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: add properties to BOARD_ALL_PROPERTIESMary Ruthven2018-01-291-1/+2
| | | | | | | | | | | | | | Add BOARD_DEEP_SLEEP_DISABLED and BOARD_DETECT_AP_WITH_UART to BOARD_ALL_PROPERTIES, so they will be updated after cr50 reboots. BUG=b:35647982 BRANCH=cr50 TEST=test deep sleep on scarlet Change-Id: I8999ae7c6c1dad6799b5fdb99ebf5d7618a21c2b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/882343 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: add board property deep sleep and detect ap flagsMary Ruthven2017-12-121-0/+4
| | | | | | | | | | | | | | | Add the flags for board_deep_sleep_allowed and board_detect_ap_with_tpm_rst. BUG=b:35647982 BRANCH=cr50 TEST=run firmware_DeepCr50SleepStress on electro. Make sure Bob can still detect the AP state and doesn't enter deep sleep Change-Id: I39e45f6eacc1cbdcb3ab1caaecd0836f8a2c073a Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/699294 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Remove BOARD_AP_USB propertyRandall Spangler2017-08-171-3/+2
| | | | | | | | | | | | | | | | | | | We previously disabled the USB PHY to the AP. But the BOARD_AP_USB property lingered on. Remove the property. Also clean up the idle task deciding when to do utmi wakes. With the AP USB connection disabled, that's only necessary when the debug cable is attached, so we can check that explicitly. BUG=none BRANCH=cr50 TEST=make buildall; boot CR50_DEV=1 image Change-Id: If81a7bcfe845d9d70dcc7e16239244a4f5f2427b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616301 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Preserve CCD state across deep sleepRandall Spangler2017-07-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two bits in a long-life register to hold the current CCD state across deep sleep. Update the bits on CCD config change, and restore them on init. This is necessary because Cr50 loses RAM contents on deep sleep. It would be really inconvenient to open CCD, get a cup of coffee, and come back to find CCD has locked again because Cr50 was idle too long. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build ccdinfo --> state=opened idle d ccdunlock ccdinfo --> state=unlocked (wait for deep sleep) sysinfo --> reset flags = hibernate wake-pin ccdinfo --> state=unlocked reboot sysinfo --> reset flags = hard ccdinfo --> state=opened Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575996 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add LONG_LIFE bit to suppress RO uart.Marius Schilder2017-05-121-0/+6
| | | | | | | | | | | BRANCH=None BUG=None Change-Id: Icfb20bff28a593c9058d67ad09f188c567b7401c Reviewed-on: https://chromium-review.googlesource.com/454240 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Store console lock state in NvMem vars.Aseda Aboagye2017-02-271-7/+3
| | | | | | | | | | | | | | | | | | | | | | This commit enables the use of the nvmem vars module. The console lock state is migrated from using the long life scratch register, to nvmem vars instead which will persist across power on reboots. BUG=b:35586145 BRANCH=None TEST=Flash a dev image. Lock the console. Remove all power from the system. Power on system and verify that console is still locked. Unlock the console, remove power from the system, power on the system, verify that the console is now unlocked. TEST=Repeat the above test, but using the nvtestvar console command instead. Change-Id: I03a2098bb0017cfca59889457a332eafb0e95db6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/445804 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Use BATT_PRES_L as source of write protect.Aseda Aboagye2017-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the Cr50 write protect behaviour to simply follow the state of the battery present pin. The state can still be overridden both ways by using the `wp` console command. A user can either force write protect enabled or force write protect disabled. Additionally, the behaviour can be reset to follow the state of the battery pin by issuing `wp follow_batt_pres`. However, the ability to force the write protect state requires an unlocked console. BUG=chrome-os-partner:62726 BRANCH=None TEST=Plug in battery, verify that WP is enabled. Plug in AC and unplug battery, verify that WP is disabled. TEST=Unplug battery, unplug AC, plug in AC, verify that WP is disabled. TEST=Unplug battery, verify that WP is disabled. Use `wp' command to enable WP, verify that it is enabled. TEST=Plug in battery, disable WP using `wp` command, put cr50 into deep sleep, wake it up, verify that WP is still disabled. TEST=Plug in AC, plug in battery, disable WP using `wp` command, unplug and plug battery connector, verify that WP is still disabled. Change-Id: I83d9820067800801ddbde311eab0853c3c2216d3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/439485 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Implement reading all strapping pins for board configScott2017-01-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously only 1 pin DI0A1 was being read to distinguish between SPI/I2C configurations. This change adds code to support reading 4 strapping pins DIOA9|DIOA1 and DIOA12|DIOA6 and enabling the internal pullup/pulldown reistors to differentiate between weak and strong external pull up/dn restistors. An 8 bit strap config id is produced and then a config table is searched to match the config id with known configuraitons. The board properties to be used are read from the config table. BRANCH=none BUG=chrome-os-partner:59833 TEST=manual Modified the Cr50 dev board with 1M and 5k pullup/pulldown resistors and connected them to 4 GPIOs (defined as strapping pins). Tested the 12 possible external pullup/pulldown configurations and verified that the correct 5 bit value was produced for each configuration. Tested with both Reef and Gru. On Reef the strap config = 0x12 and on Gru it reads 0x2 as expected. Verfifed TPM was functional on both systems. Change-Id: I18c625a2b6b904bf4bcdaf2665ed9c3cbdafeb54 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421580 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use the correct reset signal for gru and reefMary Ruthven2017-01-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boards that have plt_rst_l had sys_rst_l currently use the two signals to detect resets and reset the TPM. That meant that the TPM could reset twice depending on the timing of those signals. On boards with plt_rst_l, we should really just use that to detect system resets and not sys_rst_l. On boards with plt_rst_l, sys_rst_l should only be used as an output to trigger warm resets. This change makes both boards use the gpio tpm_rst_l_in to detect AP resets. That gpio will be connected to a different pin depending on which board we are using. On Gru the gpio will be connected to diom0 which is sys_rst_l, and reef will use diom3 which is plt_rst_l. BUG=chrome-os-partner:61789 BRANCH=none TEST=manual Use cr50 servo to verify the contents of /var/cache survive reset after 'dut-control warm_reset:on sleep:0.5000 warm_reset:off' test on gru and reef verify that the system can boot to kernel run 'sysrst pulse' and check that you only see one system reset use 'pinmux' to verify the pins for the two types of boards are setup properly on reef diom0 is an input, diom3 is an input with wake_falling, and gpio1_gpio1 uses diom3 on gru check that diom0 is an input with wake_falling, diom3 is not configured, and gpio1_gpio1 uses diom0 Change-Id: I1f6e8bfa525ffa5585a18282b78014f36f0cfee6 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/428130 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: keep wp and console state through deep sleepMary Ruthven2016-12-211-0/+35
After every reboot, we were resetting the write protect and console lock states back to default. With this change the wp and lock states will be preserved through deep sleep. They will still be reset on any other type of reboot (like Power On reset or panic). The states are also cleared if the system detects a rollback even when booting from the deep sleep. With this patch it is going to be impossible to remove hardware write protection guarding writes into AP and EC firmware flash, unless the cr50 console is unlocked. Locking the console would reinstate hardware write protection automatically even if it was disabled when the console was unlocked. Two long life scratch register 1 bits are used to keep the console and write protect states over resets. To make code cleaner bitmap assignments of the long life scratch register is put in its own include file. BUG=chrome-os-partner:58961 BRANCH=none TEST=manual On prod/dev images verify that the default wp and console lock states are still correct. change the lock and write protect states from the default and verify they are preserved through deep sleep. reboot cr50 and make sure that they are reset. unlock the console and enable flash writes, then set fallback counter on cr50 to the value of 6 (rw 0x40000128 1; rw 0x4000012c 6) and put the AP into deep sleep by hitting Alt-H-VolUp. In five minutes press the power button on the device to bring it back from s5. Observe cr50 fall back to an older image and console lock and wp disabled. Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420812 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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