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* tpm_nvmem_ops.c: add function to get size of nvmem hidden objectstabilize-quickfix-13310.91.B-cr50_stabstabilize-quickfix-13310.76.B-cr50_stabstabilize-quickfix-13310.73.B-cr50_stabstabilize-13310.99.B-cr50_stabstabilize-13310.94.B-cr50_stabstabilize-13310.83.B-cr50_stabstabilize-13310.74.B-cr50_stabstabilize-13310.72.B-cr50_stabrelease-R85-13310.B-cr50_stabVadim Sukhomlinov2020-06-262-0/+23
| | | | | | | | | | | | | | | | | | Added service function read_tpm_nvmem_size() to return size of hidden nvmem object, which is needed in FIPS framework code, but can't be implemented locally due to conflicting headers between TPM2 library and Cryptoc library, and util.h BUG=none TEST=make BOARD=cr50; meaningul test will be added in upcoming CLs Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: Iab9520170cfdcd754f1fe2e79143f75766284921 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2258534 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* common.h: consolidate stdbool.h and stddef.hVadim Sukhomlinov2020-06-252-3/+1
| | | | | | | | | | | | | | | | | | | Many source files over time started to respect 'bool' and 'size_t' types for better code readability. However, these types are defined in stdbool.h and stddef.h headers, so each time they were used there was a need to include them. util.h included both, and one option was to use it, but it conflicts with TPM2 library on definition MAX/MIN BUG=none TEST=make buildall -j Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: Ia0aca578e901c60aeafee5278471c228194d36bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2258540 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* ecc: fix padding for ECDSA sign and verify, add more test vectorsVadim Sukhomlinov2020-06-251-6/+25
| | | | | | | | | | | | | | | | | | | https://crrev.com/c/2222386 added support for short EC keys to some functions. Extending this support to sign and verify. Added test vectors for regression testing in tpmtest.py BUG=b:157528390 TEST=tpmtest.py Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I3db2c9eee9da995d45d534a2732130948548ead8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2265605 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* fips_rand: FIPS-compliant way to generate randomsVadim Sukhomlinov2020-06-244-1/+577
| | | | | | | | | | | | | | | | | | Add proper TRNG health tests and CR50-wide DRBG with reseeding BUG=b:138578157 TEST=tpmtest.py -t1 fails after cr50 reboot. rand_perf in console (kick-off FIPS TRNG test) and then tpmtest.py -t1 and tpmtest.py -t2 should succeed. Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I94c2dbd7a00dedcf1a0f318539a3c73c0c8076ef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2251381 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: do not trigger unnecessary legacy NVMEM partition checksVadim Bendebury2020-06-221-1/+1
| | | | | | | | | | | | | | | | The logic of deciding if the alternative RW image is newer than a certain version needs to be updated to accommodate moving to higher prod and prepvt major version numbers. BUG=none TEST=the 'nvmem_find_partition: No Legacy Partitions found.' message is not printed during startup any more when updating from 6.3 to 6.4. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I59e18712b3365446c29f569bf0b50f95ab67df95 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2250658 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ec.tasklist: increase stack for console task for development modeVadim Sukhomlinov2020-06-181-1/+9
| | | | | | | | | | | | | | | | | | | | | Due to changes in internal structures, stack consumption for SHA2, HMAC, HMAC_DRBG grew up, and when combined with stack growth due to changes in cprintf cause crash for some development console commands. This patch increase console stack for CR50_DEV and CRYPTO_TEST modes. BUG=none TEST=manual, build with CR50_DEV or CRYPTO_TEST, run taskinfo Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I7170c65e4b8092d165c478f505a435f834744ed9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2251382 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: use NIST-compliant configuration of TRNGVadim Sukhomlinov2020-06-171-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to NIST SP 800-90B only vetted conditioning mechanism should be used for post-processing raw entropy. See SP 800-90B, 3.1.5.1 Using Vetted Conditioning Components. Use of non-vetted algorithms is governed in 3.1.5.2, but assumes conservative coefficient 0.85 for entropy estimate, which increase number of requests to TRNG to get desirable entropy. More details on entropy estimate tests are in associated bug. Entropy measurements using NIST assessment tool didn't report noticeable change in entropy estimate. However, more changes are needed to use DRBG instead of raw TRNG for all purposes. TRNG changes reviewed also at https://crrev.com/c/1926384 BUG=b:138577834 TEST=test/tpm_test/nist_entropy.sh Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I5a578b90b8b7a77fae6a218eec48e87e7644ab44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2240519 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50/board: add board-local FIPS settingVadim Sukhomlinov2020-06-163-0/+82
| | | | | | | | | | | | | | | | | | | | | | | Implement board-local configuraration of FIPS 140-2/3 policy as complementary to FWMP policy. This is intended mostly for lab testing and dogfooding, when FWMP policy is not feasible. board_fips_enforced() returns status of FIPS from FWMP and NVRAM and caches state to avoid expensive operations later. BUG=b:138577491 TEST=manual, make buildall -j Actual test command to be added in upcoming CLs Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I8fa651e56e6e76a87bbc4dd911e7a8c0546e7e0f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2247112 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: rename ver_stateMary Ruthven2020-06-121-2/+2
| | | | | | | | | | | BUG=b:158843230 TEST=run 'ver' on cr50 Change-Id: Ia22cbc74dc23156a11caceb587f8380aa68ce23b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2243312 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: append 0 to ec points if necessary.Leo Lai2020-06-111-7/+35
| | | | | | | | | | | | | | | | | | | | | This CL enables cr50 to accept EC points of which X and/or Y component has less than 32 bytes. For testing, the following 4 data inputs can pass the test: 1. Creating salted session with a full-length ephemeral key. 2. Creating salted session with a short ephemeral key. 3. Walking through enrollment flow with a full-length ephemeral key. 4. Walking through enrollment flow with a short ephemeral key. BUG=b:157528390 TEST=see the comment above. Change-Id: I12c744ab00391a31d81d4ac6b6e644981ae46f48 Signed-off-by: Leo Lai <cylai@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2222386 Tested-by: Leo Lai <cylai@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add functionality for ACVP tests of elliptic curve implementationstabilize-lazor-13278.B-cr50_stabVadim Sukhomlinov2020-06-051-112/+212
| | | | | | | | | | | | | | | | | | | | | | NIST ACVP test expects access to test point is on curve and verification of signature with arbitrary public key. Current implementation supported only fixed public key. ACVP tests to be submitted separately. Added two new test commands to support ACVP: - TEST_POINT - test that given point is on selected curve - TEST_VERIFY_ANY - same as TEST_VERIFY, but use provided Q - TEST_SIGN_ANY - same as TEST_SIGN, but use provided d (private key) BUG=b:138578319 TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py Change-Id: Ibeabede935f5bbac918b3043072e05f8a6417aa4 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227077 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* ap_ro: add handling of the corrupted hashVadim Bendebury2020-06-053-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch closes the AP RO verification loop on the Cr50 side. If the check is triggered, the valid AP hash is found, and the RO contents is found to not match the hash, the Cr50 will - assert the EC reset; - set a flag to prevent the code from deasserting EC reset; - start a periodic hook to reassert EC reset in case the user hits power+refresh. This will prevent the Chrome OS device from booting. A new CLI command is being added to display the verification state. In developer images the new command would allow to clear the failure state, when running prod images the only way out of the failure state would be the powercycle. BUG=b:153764696 TEST=verified that erasing or programming AP RO hash when board ID is set is impossible. Verified proper shutdown in case AP RO has is present and the AP RO space is corrupted and recovery using the new cli command when running a dev image. Verified that 'ecrst off' properly reports the override. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I1029114126a9a79f80385af7bc8d5467738e04ca Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2218676 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* remove CR50_SQAMary Ruthven2020-06-023-5/+2
| | | | | | | | | | | | | | | | | | | | | | | SQA images won't be built anymore. This change removes the SQA support. It deletes all SQA ifdefs and replaces CR50_RELAXED with CR50_DEV. BUG=b:158011401 TEST=manual build regular image and check eraselfashinfo and rollback aren't included. build image with CR50_SQA=1 and check it's no different than the regular image. build DBG image and make sure it still starts open, it has the eraseflashinfo and rollback commands, and it can flash old cr50 images. Change-Id: I5e94c88b1903cfcf0eee0081fc871e55fc8586c7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227149 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* cr50: Add support for ACVP tests of HMAC implementationsVadim Sukhomlinov2020-06-021-16/+98
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support NIST ACVP testing, new commands to provide access to HMAC implementations (software, and hardware accelerated HMAC SHA-256) with CRYPTO_TEST_SETUP added: - Software HMAC (_cpri_StartHMAC) TPM implementation - dcrypto HMAC (DCRYPTO_HMAC_SHA256_init) Updated hash_test.py to support different hash algorithms for hash and HMAC, added HMAC tests. BRANCH=cr50 TEST=make BOARD=cr50 CRYPTO_TEST=1 -j && test/tpm_test/tpmtest.py BUG=b:138578319 Change-Id: I57da2f27734fc7e5dbc896d75c5f8b2ed60e3b18 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1854885 Reviewed-by: Gurleen Grewal <gurleengrewal@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Gurleen Grewal <gurleengrewal@google.com> (cherry picked from commit 32c349afe72541570984a32bd85b8f1fcf2acb39) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227074 Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* Introduce BOARD_CFG_LONG_INT_AP_BIT in TPM_BOARD_CFG registerNamyoon Woo2020-06-012-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch assigns the bit offset 0 in TPM_BOARD_CFG register to indicate the status of INT_AP_L extension. The bit 1 means INT_AP_L pulse extension is activated, and 0 means it is not. BUG=b:148691139 TEST=tested on atlas and on careena. 1. Checked the default TPM_BOARD_CFG (PWRDN_SCRATCH21) value was zero and the INT_AP_L assertion duration was 4~10 microseconds. > md 0x400000f4 1 // memory dump on GC_PMU_PWRDN_SCRATCH21 400000F4: 0x00000000 2. Attempted to change the board configuration (with a hacked UART command.). The register value was unchanged. > brdcfg 0x01 TPM_BOARD_CFG = 0x00000000 > md 0x400000f4 1 400000F4: 0x00000000 3. Forced to write the board configuration with a hacked UART command. The register value was changed. > brdcfg 0x01 force TPM_BOARD_CFG = 0x80000001 > md 0x400000f4 1 400000F4: 0x80000001 4. Checked the INT_AP_L assertion duration extended to 110 microseconds or longer. 5. After cr50 deep sleep, checked the pulse duration was still extended. - turned AP off. - disconnected Suzy-Qable. - waited three seconds - connected Suzy-Qable, and checked the reset cause was 'hibernate rbox'. > md 0x400000f4 1 400000F4: 0x8000001 6. With 100 usec long INT_AP pulse, checked trunks_cliend regression_test, stress_test and ext_command_test runs good. Checked dmesg and found no TPM errors through all tests. (ap) $ trunks_client --regression_test (ap) $ trunks_client --stress_test (ap) $ trunks_client --ext_command_test 7.checked no character loss during uart_stress_tester. (chroot) $ uart_stress_tester.py -c -t 600 /dev/ttyUSB2 /dev/ttyUSB1 8. the shortest duration of INT_AP_L assertion and deassertion observed in logic analyzer were 110 usec and 152 usec. 9. measured the depthcharge exit timestamp and cr50 flash time with or without INT_AP pulse extended to 100 usec, on atlas and helios: -----------------+-------------------+------------------ | atlas | helios -----------------+-------------------+------------------ boot (sec) | 1.398 -> 1.402 | 1.004 -> 1.011 cr50 flash (sec) | 10.800 -> 14.609 | 16.024 -> 16.466 -----------------+-------------------+------------------ Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I2b9f9defb63cf05f9d91b741ccb4b49c4c6bc8e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202839 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Introduce TPM_BOARD_CFG registerNamyoon Woo2020-06-012-0/+52
| | | | | | | | | | | | | | | | | | This patch adds the TPM vendor-defined register, TPM_BOARD_CFG, which indicates the board configuration status. This register is attributed as one-time-programmable and the value is maintained across deep sleeps. Cr50 allows a write on this register right after a cr50 reset until it receives a TPM2_PCR_Extend command. BUG=b:148691139 TEST=none Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I89ae5a53c15990ef78812aec5da81a59f04d7d98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202838 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* apply INT_AP_L extension on I2CS interfaceNamyoon Woo2020-05-291-6/+9
| | | | | | | | | | | | | | | | This patch applies INT_AP_L extension on I2CS. It uses GPIO_MONITOR_I2CS_SDA to detect a transaction start during INT_AP_L assertion and to deassert INT_AP_L. BUG=b:148691139 TEST=None Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iedd59b488dfdfaaf71dd71eda6437f1a9402d3c4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2150517 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Use a long pulse of INT_AP_L for SPSNamyoon Woo2020-05-293-0/+192
| | | | | | | | | | | | | | | | | | | | This patch adds a feature to extend each level of GPIO_INT_AP_L at least for 100 microseconds. The assertion (low GPIO_INT_AP_L) duration might be shorter only if AP asserts a SPS CS before INT_AP_L deassertion, because it means means AP recognized GPIO_INT_AP_L assertion already. This patch increases the flash usage by 280 bytes. BUG=b:148691139 TEST=None Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ie74b236bc5352e9fc21fe600c12946e50955160a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114430 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* ap RO verification: enable loggingVadim Bendebury2020-05-291-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When AP RO verification is attempted, a lot of thing could go wrong, and the operator would usually have very little insight into what's happening unless there is a terminal connected to the Cr50 console. This patch adds a new log event for registering the AP RO verification progress. The event payload is a single byte value, logging the following events: 0 - refresh key press is detected 1 - power button has been released before AP RO check was triggered 2 - trigger sequence timeout (refresh button not pressed in time) 3 - AP RO check triggered 4 - could not run the check, hash space not programmed 5 - could not run the check, hash space corrupted 6 - AP RO verification failed 7 - AP RO verification succeeded BUG=b:153764696 TEST=verified logging during various AP RO verification attempts: $ gsctool -a -L Log time zone is PST Dec 31 69 16:00:01 : 00 May 06 20 21:20:49 : 09 01 May 06 20 21:21:53 : 09 00 May 06 20 21:21:54 : 09 00 May 06 20 21:21:55 : 09 03 May 06 20 21:21:56 : 09 07 May 06 20 21:23:03 : 09 00 May 06 20 21:23:04 : 09 00 May 06 20 21:23:05 : 09 02 May 07 20 11:21:52 : 09 00 May 07 20 11:21:53 : 09 00 May 07 20 11:21:54 : 09 01 May 08 20 11:57:21 : 09 00 May 08 20 11:57:22 : 09 00 May 08 20 11:57:23 : 09 03 May 08 20 11:57:24 : 09 04 May 08 20 12:07:15 : 09 00 May 08 20 12:07:16 : 09 00 May 08 20 12:07:17 : 09 03 May 08 20 12:07:19 : 09 07 May 08 20 12:09:20 : 09 00 May 08 20 12:09:21 : 09 00 May 08 20 12:09:22 : 09 03 May 08 20 12:09:23 : 09 06 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I739f9dbb2e7b8fc87601d61e1f87eb49d85bdf14 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2191283 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* ap_ro_verification: enable AP RO verification supportVadim Bendebury2020-05-291-0/+2
| | | | | | | | | | | | | | | | | | This patch flips on the switch for the AP RO verification implementation. BUG=b:153764696 TEST=generated AP integrity verification data using the ap_ro_hash.py script and then ran the verification procedure, observing the 'hash match' message on the Cr50 console. Also verified that the Open Box RMA procedure still succeeds. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I15f19aefcb11a055e66994e33976b98ce6fdf099 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220829 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Plug in the AP RO verification implementationVadim Bendebury2020-05-292-2/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds plumbing necessary to invoke the AP RO verification function in response to the operator entering the 'magic sequence' of holding the power button pressed and pressing/releasing the refresh button three times within five seconds. The code used during the 'Open box RMA' verification process is used, with the physical presence confirmation phase bypassed. This patch also makes sure that attempts to use CCD to program AP or EC flash while AP RO verification is in progress would fail. BUG=b:153764696, b:154966209 TEST=with the next patch applied, generated AP integrity verification data using the ap_ro_hash.py script and then ran the verification procedure, observing the 'hash match' message on the Cr50 console. Also verified that the Open Box RMA procedure still succeeds. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ic101fb892554ebb05f9ebe6d1546bfb439f74043 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171399 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* board_id: refactor to expose function checking INFO1 board ID spaceVadim Bendebury2020-05-201-19/+0
| | | | | | | | | | | | | This patch makes it possible to check if the INFO1 Board ID space is programmed or not. BUG=b:153764696 TEST='make buildall -j' Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ic771956a08e276c2e1a426729a8ecdae3f86a04f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204974 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* usb_spi: refactor to allow use in different contextsstabilize-quickfix-13099.93.B-cr50_stabstabilize-13099.94.B-cr50_stabstabilize-13099.90.B-cr50_stabstabilize-13099.85.B-cr50_stabstabilize-13099.73.B-cr50_stabstabilize-13099.72.B-cr50_stabstabilize-13099.70.B-cr50_stabstabilize-13099.118.B-cr50_stabstabilize-13099.110.B-cr50_stabstabilize-13099.101.B-cr50_stabrelease-R84-13099.B-cr50_stabVadim Bendebury2020-05-141-29/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code which allows to read a section of AP or EC flash and calculate the section's SHA256 sum does not allow calculating the sum over multiple non-adjacent flash areas. This patch changes the implementation to allow calculations over more than one region. Initialization, calculation and reporting of the result become three separate API entries. The loop counting the number of the read flash chunks, is being simplified, a watchdog kick added to the brief loop interruptions, as it turns out that sleeping alone is not enough to prevent watchdog expiration when calculating hash over large SPI flash ranges. Also simplified prototypes for usb_spi_board_enable() and usb_spi_board_disable(). BUG=b:153764696 TEST=created an RO descriptor for the Atlas DUT and verified that 'gsctool -O' succeeds. Cq-Depend: chrome-internal:2939596 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iec7b8634c7c80ebc7600c5b708879eb322bc7fec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163569 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* make cr50 agnostic about EC-EFS2Namyoon Woo2020-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes cr50 respond EC-EFS2 related TPM commands no matter it has the board property, BOARD_EC_CR50_COMM_SUPPORT or not. board_has_ec_cr50_comm_support() calls remain for configuring GPIO_EC_PACKET_MODE_EN only. BUG=b:155214584 TEST=checked gsctool running on Coral. [before] $ gsctool --getbootmode finding_device 18d1:5014 Found device. found interface 3 endpoint 4, chunk_len 64 READY ------- Error 8 in Getting boot mode [after] $ gsctool --getbootmode finding_device 18d1:5014 Found device. found interface 3 endpoint 4, chunk_len 64 READY ------- Boot mode = 0x00: NORMAL Also checked 'ec_comm' uart command. [before] > ec_comm No EC-CR50 comm support Invalid argument Usage: ec_comm [corrupt] [after] > ec_comm uart : 0xff packet mode : DISABLED phase : 0 preamble_count : 0 bytes_received : 0 bytes_expected : 0 response : 0x0000 ec_hash : UNLOADED <-- It is marked as unloaded, secdata_error_code : 0x00001203 <-- because of NVMEM error. boot_mode : NORMAL <-- Still, boot_mode is normal. Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I08dc9abd8f194c83484b5be9b0a5e8844b2fd221 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2185872 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* VENDOR_CC_WP: allow to enable write protection (WP)Vadim Bendebury2020-04-141-1/+10
| | | | | | | | | | | | | | | | | | | | | | | The gsctool utility allows to examine the device WP status, but does not allow to set it. It would be useful to provide the user with a means of enabling WP at any time. This patch extends the existing vendor command VENDOR_CC_WP implementation to allow an optional one byte parameter. If the parameter is present, the Cr50 will unconditionally invoke set_wp_state(1) when processing the command. BUG=b:153881773 TEST=with the corresponding gsctool.c changes coming up in the next patch verified that attempts to enable WP when running the unmodified Cr50 image fail with error message "Early Cr50 versions do not support setting WP", and that the updated Cr50 image allows to enable WP using 'gsctool -a -w enable' Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I75c200bbb9085e9f74c227ef80f782defdaaa29e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2149519 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Implement sequence for detecting trigger for AP RO verificationVadim Bendebury2020-04-131-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When supported, the AP RO verification would be triggered by the operator pressing and keeping pressed the power button and then pressing and releasing a few times the refresh key. As proposed in this patch, to trigger the verification the operator must complete the sequence within 3 seconds by pressing the refresh key three times. The sequences is controlled by periodic polling. Enabling refresh key press interrupts was investigated, the issue is that the key generates plenty of interrupts due to dribbling, to the tune of a hundred each time it is pressed. It is much cheaper to just poll every 20 ms. The CONFIG_AP_RO_VERIFICATION config flag controls enabling of this feature. BUG=b:141191727 TEST=enabled the new feature and verified proper operation by both detecting the trigger and abandoning the sequence due to released power button or not enough times pressed refresh key. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I55376a87009d6f8020358ad11db1e47d0b8393ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2144944 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Add a sw flag to indicate usb_i2c statusNamyoon Woo2020-04-091-7/+6
| | | | | | | | | | | | | | | Cr50 used to read GPIO_EN_PP3300_INA_L value to detect if USB_I2C is enabled. However it requires an external pullup. Instead, this patch adds a sw flag to indicate USB_I2C status, so that it can keep USB_I2C status regardless external HW factors. BUG=b:152946978 TEST=ran flash_ec on waddledee, ampton, and dragonegg. Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: Ie1a3a8c790e9643a3b49b6c519167ee3bdecc650 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2140535 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* speed up AP State polling when CCD is active.Vadim Bendebury2020-04-081-2/+27
| | | | | | | | | | | | | | | | | | | It turns out that the Cr50 not shutting off the AP UART quickly enough causes violation of the JSL power sequence requirements due to the leakage caused by the active UART lines. Let's speed up AP state polling when CCD is active. When CCD is not active the UART is shut of to start with. BUG=b:152446186 TEST=running the new image verified that that timing constraints are not violated any more. Also verified reliable UART=>USB bridging operation. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iffb7f8bc33c4516bb7cf5cbf58c5ced277cd1aec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139732 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* tpm2: clean up stubs.cVadim Bendebury2020-03-251-17/+4
| | | | | | | | | | | | | | | Drop the unused function and use ccprintf() instead of uart_printf(). Using ccprintf() will make it easier to use this code when packet mode is enabled. Used tabs in the changed lines s to pacify repo upload. BUG=b:149964350 TEST=make buildall -j Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I97522e9278a4393ef75b9a6a90e6995ba2449f30 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114237
* change the init proiorities of ec_efs_init() and ec_comm_init()release-R82-12974.B-cr50_stabNamyoon Woo2020-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reprioritizes ec_comm_init() and ec_efs_init() so that they won't be executed prior to board_init(), which executes nvmem_init(). BUG=b:151187315 BRANCH=cr50 TEST=let cr50 reboot a few times, and checked the console message and the ec_comm command output that Kernel secdata was reloaded without error. Swapped cr50 image from normal to dev, vice versa, and repeated the rebooting. [Reset cause: hard] [0.003799 Inits done] strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005893 Valid strap: 0xe properties: 0xa00041] [0.007991 init_jittery_clock_locking_optional: run level high, ... [0.045539 init took 29953] [0.051185 tpm_rst_asserted] [0.052074 EC-COMM: Initializtion] Console is enabled; type HELP for help. ... > ec_comm ... response : 0xec00 ec_hash : LOADED secdata_error_code : 0x00000000 > Change-Id: Ia695896986374ac9d23ac111fe0086ec6a13923e Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2093102 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* move ec_comm implementation to common directoryNamyoon Woo2020-03-105-652/+2
| | | | | | | | | | | | | | | This patch moves ec_comm.c and ec_efs.c from board/cr50 to common/, so that they can be shared with other board configuration (like host). This is to build unittest for those files. BUG=none BRANCH=cr50 TEST=make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I67ac313054ebe4604848a176f0a42e3483957e74 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094076 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* fix in EC-EFS command, SET_BOOT_MODENamyoon Woo2020-03-101-1/+1
| | | | | | | | | | | | | | | | This patch changes fixes the pre-condition to check before it processes the command, SET_BOOT_MODE. It should check if the current boot mode is NORMAL mode, but it used to check if the input parameter value is NORMAL mode. BUG=none BRANCH=cr50 TEST=make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I85e0a3a1ed27a276262a7b9d3889c826cca14d19 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094075 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: Provision DIOM4 as inputVadim Bendebury2020-02-271-0/+10
| | | | | | | | | | | | | | | | | This will allow using this pin a physical presence indicator on certain platforms. BRANCH=cr50,cr50-mp BUG=b:144455668 TEST=tried the new image on the red board, observed DIOM4 level changing when shorting it to ground. Change-Id: I7c20b094d73d49321921c5afa67e0db9825ea82f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076499 Reviewed-by: Yicheng Li <yichengli@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* capitalize enum tpm_read_rv and tpm_write_rvstabilize-volteer-12931.B-cr50_stabNamyoon Woo2020-02-225-25/+25
| | | | | | | | | | | | This patch fixes a coding style violation in enum name. BUG=none BRANCH=cr50 TEST=none Change-Id: I53eb8aa0905ecfc841a4fe7a738df74d571e321b Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065493
* EC-CR50 communicationNamyoon Woo2020-02-223-4/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports EC-CR50 communication. EC activates EC-CR50 communication by setting high DIOB3, and send a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes the packet, and sends a response packet back to EC. EC deactivates EC-CR50 communication by putting low DIOB3. This patch supports two kinds of EC-CR50 commands: - CR50_COMM_CMD_SET_BOOT_MODE - CR50_COMM_CMD_VERIFY_HASH Cr50 stores some of EC-EFS context in a powerdown register before deep sleep and restores it after wakeup. This patch increases flash usage by 1456 bytes. BUG=b:119329144 BRANCH=cr50 TEST=Checked "ec_comm" console command on Octopus and reworked Helios. Checked uart_stress_tester.py running without character loss. Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add TPM vendor-specific commands to support EC-EFS2Namyoon Woo2020-02-221-0/+43
| | | | | | | | | | | | | | | | | | | Based on the design in go/ec-efs2, this patch adds two TPM vendor-specific commands: - VENDOR_CC_GET_BOOT_MODE - VENDOR_CC_RESET_EC BUG=b:141578322 BRANCH=cr50 TEST=tested with EC-EFS supporting EC/AP firmware. With CR50 dev image, tested with gsctool on Octopus and Helios by sending each of new vendor commands. Checked flash_ec working on Scarlet in bitbang mode. Change-Id: Ia8f38a7b9cc45b172a1a1ef7e216034e520b79c7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956409 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* read EC Firmware hash from kernel secdata during board initNamyoon Woo2020-02-223-1/+73
| | | | | | | | | | | | | | Cr50 reads EC Firmware hash from kernel secdata. This data shall be used for EC-EFS (Early Firmware Selection) procedure. BUG=chromium:1020578, b:148489182 BRANCH=cr50 TEST=none Change-Id: Id8942b5b49dd5b0412d198a12ee0bf87fd59d47f Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956159 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ccdblock can block EC-CR50 communicationNamyoon Woo2020-02-203-4/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 'EC_CR50_COMM' a new option for ccdblock console command. It can be useful for system rescue purpose like you want to force cr50 to yield EC_UART (especially TX) port to servo. BUG=chromium:1047287 BRANCH=cr50, cr50-mp TEST=ran manually ccdblock. > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > > > ccdblock EC_CR50_COMM enable CCD ports blocked: EC_CR50_COMM > [73.386550 CCD state: UARTEC I2C SPI] > > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTEC I2C SPI CCD ports blocked: EC_CR50_COMM > > > ccdblock EC_CR50_COMM disable CCD ports blocked: (none) > [104.781623 CCD state: UARTEC+TX I2C SPI] ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) Change-Id: I7816c201054f1793906bd19d4b58755593d2fbac Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2042118 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* restructure EC-EFS moduleNamyoon Woo2020-02-208-12/+134
| | | | | | | | | | | | | | | - add ec_efs, which tracks the system boot mode. - add ec_comm.h header file for EC-EFS related functions. - revised vboot.h header file. BUG=b:141143112 BRANCH=cr50 TEST=none Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* optimize read_tpm_nvmem()Namyoon Woo2020-02-191-3/+6
| | | | | | | | | | | | | | | | | | This patch optimizes read_tpm_nvmem() by replacing NvGetIndexData() and NvGetIndexInfo() with NvReadIndexDta() and NvReadIndexInfo() respectively. This will reduce NvFindHandle() calls from three to one. BUG=b:148489182 BRANCH=cr50, cr50-mp TEST=The function execution time reduces from 1.2 msec to 550 usec. Cq-Depend:chromium:2038108 Change-Id: I6659480d8b60578f3d0b9dc3f62a677ae8489a57 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037920 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* control UART_EC RX/TX based on EC-CR50 communication statusNamyoon Woo2020-02-192-3/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows EC-CR50 communication to enable EC UART only if EC is on and bitbang mode is disabled. EC UART shall be enabled even when CCD_CAP_GSC_TX_EC_RX is disabled, EC UART is ccdblocked, or servo is connected. EC-CR50 comm supporting boards are supposed to have H1 dominate EC UART TX line against servo. Servo detection, which is checked every second, shall be delayed during EC-CR50 communication because EC UART TX pin (GPIO_SERVO_DETECT) is used as an output. Servo state shall be held as it was. Once EC-CR50 communication is done, the servo detection will resume or CCD state gets updated based on what it used to be before EC-CR50 communication. BUG=chromium:1035706 BRANCH=cr50 TEST=manually tested on a reworked Helios. // CCD connection only > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ecrst pulse Pulsing EC reset EC_RST_L is deasserted // Servo connection only > ccdstate AP: off AP UART: off EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: I2C CCD ports blocked: (none) Change-Id: I02667bee004d237d846393a18f247970982c71b7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023239 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* control EC USB-UART bridgeNamyoon Woo2020-02-191-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL separates the control on USB-UART bridge of EC device from EC UART control. USB-UART bridge shall be enabled if CCD connection is detected and the CCD capability is enabled. Otherwise, EC USB-UART shall be disabled. By doing so, CCD capability can be observed even when EC-CR50 communication enables EC UART. This patch increases the flash usage by 204 bytes BUG=b:148247228 BRANCH=cr50, cr50_mp TEST=ran firmware_Cr50CCDServoCap on Helios. > ccd State: Locked Password: none Flags: 0x000001 Capabilities: 0000000000000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX UARTEC USBEC CCD ports blocked: (none) > ccd State: Opened Password: none Flags: 0x800001 Capabilities: 5555454115000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC+TX CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX CCD ports blocked: (none) Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add Asurada strapMary Ruthven2020-02-191-0/+7
| | | | | | | | | | | BUG=b:147835918 BRANCH=cr50 TEST=none Change-Id: I07d4071c4fe99df0a030be1e087f43a696081c3c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051101 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* use gpio_set_wakepin() to enable or disable wake pinsNamyoon Woo2020-02-131-62/+29
| | | | | | | | | | | | | | | | | This uses gpio_set_wakepin() to setup the wake pins instead of writing to the PINMUX EXITEN registers directly. This patch reduces the flash usage by 248 bytes. BUG=b:35587259 BRANCH=cr50 TEST=checked pinmux configuration hasn't changed on coral. Checked firmware_Cr50DeviceState running good on coral. Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Defer call to board_reboot_ec() in key_combo0_irq()Mathew King2020-02-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | On Wilco devices the recovery key combination will trigger an irq which will reboot the EC to enter recovery mode. CL:1881752 moved a 30 ms delay and made it synchronous. This change works in most contexts except for within an irq which cannot sleep so when a user presses the recovery key combo the H1 will hard reboot when the sleep is called. This change defers the call to board_reboot_ec() so that it is no longer in the irq context. BUG=b:147404780 TEST=On Drallion and Sarien press pwr + F2, recovery mode is entered without to hold the keys for an extended period of time. Also verified that programming flash over CCD still works on Drallion. BRANCH=none Change-Id: Ib7ebbe2c67b575b6a99d01a4055bb00ee9d15b7e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2020328 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* make DIOB3 interruptible and wakable for EC-EFS2Namyoon Woo2020-02-085-8/+121
| | | | | | | | | | | | | | | | | | | | | If the board supports EC-CR50 communication, Cr50 enables both rising/falling-edge triggered interrupt on DIOB3 pin and makes it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4. If the board does not support EC-CR50 communication, Cr50 connects GPIO_AP_FLASH_SELECT to DIOB3. If EC puts high on DIOB3 to activate EC-CR50 communication, CR50 enables UART_EC RX and TX. BUG=chromium:1035706 BRANCH=cr50 TEST=none Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* revise the uart tx connect/disconnect functionsstabilize-quickfix-12871.27.B-cr50_stabstabilize-12871.91.B-cr50_stabstabilize-12871.65.B-cr50_stabstabilize-12871.57.B-cr50_stabstabilize-12871.253.B-cr50_stabstabilize-12871.24.B-cr50_stabstabilize-12871.103.B-cr50_stabstabilize-12871.102.B-cr50_stabstabilize-12859.B-cr50_stabrelease-R81-12871.B-cr50_stabNamyoon Woo2020-01-221-39/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reduces redundant condition checking in connecting or disconnecting UART TX. BUG=none BRANCH=cr50 TEST=manually checked ccd state with/without servo connection and/or ccd connection. [AFTER] > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX I2C SPI CCD ports blocked: EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: I2C SPI CCD ports blocked: AP EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: ignored CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add support for using a strap pin as a ccd gpioMary Ruthven2020-01-173-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a mechanism which allows to use one of board strap pins as the CCD gpio and makes DIOA9 the CCD pin on boards with strap os 0xE. This change uses 2 bits from the board properties to determine which pin is used as the ccd gpio. 0 - no ccd gpio 1 - DIOA1 2 - DIOA9 3 - DIOA12 DIOA6 is another strap pin, but there's only one valid strap with a 5kPU left, so I decided not to use another board property bit to support it as a possible ccd gpio. I want to save the board property bit, since we're running out of them and there are so many other I2C straps boards can use. We can add it later if we need to. BUG=b:147812066 BRANCH=cr50 TEST=manual. Use pinmux and gpiocfg to verify the output is only enabled when the gpio is asserted. no added brdproperties - nothing is different with pinmux run on Puff gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button pressed gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button released add BOARD_CCD_REC_LID_PIN_DIOA1 to SPI board pinmux output adds DIOA1 27 IN GPIO1_GPIO10 GPIO1_GPIO10 24 DIOA1 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA9 to SPI board pinmux output adds DIOA9 27 IN GPIO1_GPIO10 GPIO1_GPIO10 16 DIOA9 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA12 to I2C board pinmux output adds DIOA12 27 IN GPIO1_GPIO10 GPIO1_GPIO10 13 DIOA12 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output Change-Id: If74385135a572e7e5d0763fad9f5368fdec8d7a0 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006210 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* add BOARD_EC_CR50_COMM_SUPPORT to board propertiesNamyoon Woo2020-01-144-4/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL add a board property indicating EC-CR50 communication support. The target boards are Volteer,Dedede,Puff, and Zork. It shall be detected if the H1 strap configuration value is either 0x0E or 0xE0. BUG=b:146567516, chromium:1027660 BRANCH=cr50 TEST=Flashed AP firmware through CCD on Grunt, Octopus, Scarlet and Atlas. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:2 a6:0 a12:0 [0.005886 Valid strap: 0xa properties: 0x41] > brdprop properties = 0x1141 > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600b8: DIOB3 3 IN GPIO0_GPIO2 400600c0: DIOB4 0 IN PD ... 40060100: GPIO0_GPIO2 7 DIOB3 ... 40060120: GPIO0_GPIO10 6 DIOB4 Flashed AP firmware on a reworked board with 1M ohm on DIOA1 and 5k ohm on DIOA9. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005886 Valid strap: 0xe properties: 0x200041] > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600c0: DIOB4 3 IN PD GPIO0_GPIO2 ... 40060100: GPIO0_GPIO2 6 DIOB4 ... 40060120: GPIO0_GPIO10 6 DIOB4 Change-Id: If60765190a385a0e728177911b1ec738c6a00d99 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979612 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* drop chip factory mode supportVadim Bendebury2020-01-132-22/+0
| | | | | | | | | | | | | | | | There is no need to keep the code supporting chip factory mode in Chrome OS production branches, this code is never used outside of the chip factory environment. BRANCH=cr50, cr50-mp BUG=none TEST=built an image, verified that an Atlas device boots up into the previously created Chrome OS account. Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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