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* Remove cyan ec configurationBernie Thompson2015-10-279-788/+0
| | | | | | | | | | | | | | We no longer need to build cyan on ToT, so we can remove it. BUG=chrome-os-partner:44576 TEST=None BRANCH=None Change-Id: Ifaad4570cb8e1c427e0c341073e4bacd29462974 Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309000 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Remove CONFIG_PORT80_TASK_EN from boards.Aseda Aboagye2015-10-231-1/+0
| | | | | | | | | | | | | | | | | | There is no port 80 task for the MEC1322 anymore, therefore no board should be using this define. I forgot to remove these at the time. BUG=None BRANCH=None TEST=make -j buildall tests CQ-DEPEND=CL:308450 Change-Id: Ie44474470edb40bc94ec95be9663b509e0ba299a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/308451 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Change the Port 80 task to a timer IRQ.Aseda Aboagye2015-10-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | The port 80 task just polls every 1ms until disabled when the system goes into suspend. Therefore, this commit configures a 1ms timer interrupt that will be used for the port 80 writes instead of using an entire task. This saves task stack space as well as context switches. BUG=chrome-os-partner:46062 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS and verify using the `port80' console comamnd that there are bytes in the port80 history. TEST=make -j buildall tests Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305591 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion: add config option to use the old accelerometer ref frameAlec Berg2015-09-171-16/+0
| | | | | | | | | | | | | | | | | | | | | | | Add config option to use the old accelerometer reference frame, which is used on samus and products using 3.14 or earlier kernel. This fixes samus so that the lid angle calculation is correct again. This also moves the accel_orientation structure out of the board directory and into common code, since it purely is a function of the reference frame being used. BUG=chrome-os-partner:43494 BRANCH=none TEST=test on samus, verify lid angle calculation is correct once again. also, enable the motion_lid test and verify that it passes. Change-Id: I948a74a71964b54c68be66e828a030ddd0418947 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300510 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver: Refactor Kionix Accelerometer drivers.Aseda Aboagye2015-09-151-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a new basic driver for the Kionix KX022 Accelerometer. Currently, the driver is capable of reading the sensor data and manipulating its ODR, resolution, and range. This sensor also has integrated support for Directional Tap/Double-Tap(TM), however that functionality is not yet implemented in the driver. Lastly, since this accelerometer is very similar to the previous KXCJ9, this commit tries to combine the drivers. Note, the variant of the Kionix accelerometer MUST be specified in the private data structure. BUG=chrome-os-partner:43494 BRANCH=None TEST=Build GLaDOS EC with driver enabled and verify that valid accelerometer data is read, and that range, resolution, and odr can all be modified. TEST=Build samus EC image and verify that the lid still works. Additionally, verify that I can change the odr, rate, and resolution. TEST=make buildall tests Change-Id: I238ff1dc13f5342a93f8f701a0da85c52f25d214 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/299013 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* eoption: Remove unused eeprom option storage codeAnton Staaf2015-09-081-1/+0
| | | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I2174a904df160d19d47f1aa2d053349356cb4291 Reviewed-on: https://chromium-review.googlesource.com/297805 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cyan, kunimitsu, strago: motion_sense: use new rate calculationGwendal Grignou2015-08-291-10/+46
| | | | | | | | | | | | | | | | | | | | | | Use new config structure. Remove pre-init when sensors are shutdown in S3 on strago: motion_sense is not setting ODR to 0 inconditionally when sensors are not active. active_mask now means state (S0, S3, S5) where sensors are powered on. When sensor is powered but unused, EC can use the config array to set the polling and ODR to 0. BUG=chromium:513458 TEST=On Cyan, verify the sensors are working in S0. In S3, check the motion_sense task is idle (now sensor to probe). Check the task comes back on resume. BRANCH=cyan,strago Change-Id: Ib3d118b7139f94755fef4cb73fc1274e9e2f2826 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295781 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* cyan: fix sensors matricesGwendal Grignou2015-08-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Matches definitons set in chromium/chromeos/accelerometer/accelerometer_types.h. Using that standard, the coordinate frames of the lid and base DO NOT line up perfectly when the lid is fully closed or fully open. Therefore, rotate the lid vector 180 along the X axis before calculating the lid angle. BRANCH=cyan BUG=chrome-os-partner:40177 TEST=When the device is open 180 degrees, check the sensors agree with each other: Flat on the back (Z pointing to the sky): localhost devices # cat */*raw -1008 [keyboard : X] -112 [keyboard : Y] 16544 [kyeboard : Z] -256 [lid : X ] 2000 [lid : Y ] 16336 [lid : Z ] On the right side (X pointing to the ground) localhost devices # cat */*raw -16928 -48 -1040 -16176 432 80 On the bottom edge (Y pointing to the sky) localhost devices # cat */*raw -192 15872 1648 496 15936 752 Check the angle as calculated by the EC is correct using accelinfo. Change-Id: Ib8ee42da8cf818213f892b1f024253f37a4da488 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/294716 Reviewed-by: Jonathan Ross <jonross@chromium.org> Reviewed-by: Eric Caruso <ejcaruso@chromium.org>
* Cyan: Added Clamshell/Tablet mode supportli feng2015-08-102-19/+31
| | | | | | | | | | | | | | | | | | | | | Enabled lid angle calculation. Clamshell/Tablet mode is decided by lid angle. Accelerometers are set to be active in S3 also. Trackpad is enabled/disabled by GPIO TP_INT_DISABLE. Keyboard scan and trackpad are enabled in clamshell mode and disabled in tablet mode. Removed enable_keyboard() since keyboard is enabled in clamshell S0 and S3. BUG=chrome-os-partner:41353 TEST=Verify in clamshell mode, system can be waken up from S3 by keyboard/trackpad; And not tablet mode. BRANCH=None Change-Id: Ic5fb5a562e8426288eae2fb9815a213fe5033955 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/287341 Reviewed-by: Shawn N <shawnn@chromium.org>
* accel: mechanical changes from i2c_addr to addrGwendal Grignou2015-07-301-2/+2
| | | | | | | | | | | | | | | Encode both the I2C address and SPI GPIO CS in addr field. Mechanical change to rename i2c_addr into addr. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: I1c7435398deacb27211445afa27a08716d224c06 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288513 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-302-2/+8
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* cyan: Increase chipset stack size.Divagar Mohandass2015-07-281-1/+1
| | | | | | | | | | | | | | Chipset task is overflowing and causing runtime crash. Increasing the chipset task stack size by 128 bytes. BUG=chrome-os-partner:43329 BRANCH=none TEST=Build/flash EC and boot the platform to OS. Change-Id: I4e444cc48979c74810851ab2625b982fdabdeb73 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/289112 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cyan: GPIO leakage fixesKyoung Kim2015-07-201-11/+15
| | | | | | | | | | | | | | | | | | | Fixes for GPIO leakage 1. LPC_CLKRUN 2. JTAG pins 3. LED ports from OD to PP 4. NC pins BUG=None TEST=Booted Cyan EVT BRANCH=None Change-Id: I36c1f3456f0b59155ff825e981b0b38efb9ec35e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/285131 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* Cyan: Enabling heavysleep idle task at S3Kyoung Kim2015-07-173-0/+5
| | | | | | | | | | | | | | | | enable heavysleep idle task for Cyan BUG=None TEST=Cyan PreEVT BRANCH=None Change-Id: I1b1139cc5a91d4b76959e4d64b3d363449e555e9 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283552 Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* cyan: fix issues with write protectionAndrey Petrov2015-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fixes cyan/board.h to use correct SPI part * Adds new flash protection regions in spi_flash_reg.c * Sets SRP register in flash_physical_protect_at_boot() * Fixes a bug in COMPARE_BIT macro * Makes spi_flash_set_status() fail only when both HW pin is asserted AND SRP(s) are set * Makes sure set_flash_set_status() completes before returning BUG=chrome-os-partner:40908 BRANCH=master TEST=on Cyan: With WP pin de-asserted: flashrom -p ec --wp-enable flashrom -p ec --wp-status, make sure it is enabled flashrom -p ec --wp-disable flashrom -p ec --status, make sure it is disabled flashrom -p ec --wp-enable Assert WP pin (either with screwdriver or dut-control) flashrom -p ec --wp-disable make sure it failed Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276671 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Allow multiple hibernate wake sourcesShawn Nematbakhsh2015-07-162-1/+6
| | | | | | | | | | | | | | | | | Allow multiple GPIOs to wake the EC from hibernate by requiring boards to define hibernate_wake_pins and hibernate_wake_pins_used. In addition, clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST as an input due to a bug on certain boards. BUG=chrome-os-partner:42104 TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC wakes with power button press or with "dut-control lid_open:no". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13a6e062393cab8ed7129eda253585951f771109 Reviewed-on: https://chromium-review.googlesource.com/285924 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* motion: Add sample frequency per sensorGwendal Grignou2015-07-151-2/+4
| | | | | | | | | | | | | | | | | | | | | Store at which frequency each sensor should be sampled. This frequency is different from the sensor frequency: - sensor frequency: frequency at which the sensor produce information. - sensor sampling frequency: frequency at the which the EC gater information. If 2 sensors must be sampled at very different frequency, we don't want to oversample the slow one, and filling the software FIFO unnecessarily. BRANCH=smaug TEST=Unit test. Check that frequency is correct when sensor frequencies change from IIO driver. BUG=chrome-os-partner:39900 Change-Id: I4272963413f53d4ca004e26639dc7a2affd317eb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284616 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cyan: Enable PG3 for CyanKyoung Kim2015-07-152-9/+17
| | | | | | | | | | | | | | | | | Enable SOC G3 and Psuedo G3 for Cyan BUG=none TEST=Cyan EVT BRANCH=none Change-Id: Iaaa535786b1ac7485414f3bfb902357501fe47f5 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283553 Reviewed-by: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* cleanup: remove board_discharge_on_ac() unless custom func neededAlec Berg2015-07-142-10/+0
| | | | | | | | | | | | | | | | | | Remove duplicate board_discharge_on_ac() functions and create CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM for boards that have a unique implementation of board_discharge_on_ac(). BUG=chrome-os-partner:42294 BRANCH=none TEST=make -j buildall. load on samus and test 'ectool chargecontrol discharge' forces discharging on AC, and 'ectool chargecontrol normal' resumes normal charging. Change-Id: I2b7c04b9278d07748d6d41798ceab1a7e90684e4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284911 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* strago/cyan:Enable USB port power controlDivya Jyothi2015-07-141-0/+3
| | | | | | | | | | | BUG=None TEST=Verified USB ports power GPIO pin on/off BRANCH=None Change-Id: Ie1896367993b9453cdbd5e0a868e6fabc5819933 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/284663 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Strago/Cyan: Change USB power pin name to generic one.li feng2015-07-141-2/+2
| | | | | | | | | | | | | | | | Removed USB enable/disable as it will be handled by HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled. BUG=none TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value changed when state switch between S3 and S5. BRANCH=none Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283593 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: remove GPIO_INT_DSLEEP from chips where it's not usefulAlec Berg2015-07-131-10/+10
| | | | | | | | | | | | | | | | | | GPIO_INT_DSLEEP is useful on LM4 to save power when in deep sleep by allowing us to disable clock to gpio blocks unless it's needed as a wake source. The MEC and ST chips don't have this option, so all gpio's can be used as wake source from deep sleep. Therefore remove this flag from all boards where this flag doesn't do anything to remove confusion. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I4cb175431a22f100035a81b32e9367b510f4836e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284742 Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix stack overflow exception in host-command task.Chiranjeevi Rapolu2015-07-081-1/+1
| | | | | | | | | | | | | | | | Increase host-command task stack size by 128 to avoid stack overflow exception. BRANCH=None BUG=chrome-os-partner:42071 TEST=Test for general functionality and confirm that no stack overflow happens. Change-Id: I5513dbca84cf556357c25cddbcde00e0db6d271b Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282810 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cyan: Enable Hash computation to facilitate Software Sync.Shamile Khan2015-06-161-0/+1
| | | | | | | | | | | | | | | BUG=chrome-os-partner:40526 TEST=Enable Software Sync in Coreboot and Depthcharge. Compile EC followed by Coreboot and program Coreboot. Compile a new version of EC and program it. Reboot and check EC version of RW image when Login Screen appears. The version should not be the latest. BRANCH=none Change-Id: Ib6f5aa57fdda607a5c1cf59c8786a4a3a46b575f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276426 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Retry i2c operation if fails on nack'd(EC_ERROR_BUSY).li feng2015-06-041-0/+3
| | | | | | | | | | | | | | | Retry count is defined by CONFIG_I2C_NACK_RETRY_COUNT. BUG=chrome-os-partner:37494 TEST=Tested on Cyan, observed retry happens on nack'd i2c. BRANCH=None Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I73ed15a52335de6c5a5b647660bfe431a8238716 Reviewed-on: https://chromium-review.googlesource.com/274689 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* Increase charger/console/hook stack sizes.Chiranjeevi Rapolu2015-06-041-3/+3
| | | | | | | | | | | | | | | | | | | | Charger task is overflowing and causing crash. Increased charger task stack size by 128 bytes. Also increased console/hook by 128 bytes as these are also close to its limit. BRANCH=None BUG=chrome-os-partner:40766 TEST=1.Program EC image. 2. Run various tests to verify charger stack doesn't overflow. Change-Id: I6e350584508fa3a47769982b1e0cf3e3aea9ded6 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/274204 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* Cyan: Correct the accelerometer orientation matricesVijay Hiremath2015-06-042-14/+16
| | | | | | | | | | | | BUG=chrome-os-partner:40177 BRANCH=none TEST=Verified the lid angle from accelinfo console command by rotating the lid. Change-Id: Ib91258285990942f0307ae8b29983f588e972747 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/274850 Reviewed-by: Shawn N <shawnn@chromium.org>
* cyan: Added board version support.Kevin K Wong2015-05-272-3/+4
| | | | | | | | | | | BUG=none TEST=Verified correct board version is returned via "version" console command. BRANCH=none Change-Id: I97cf9911e3279ea7b6ad2f3bb383cde43c5114ba Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272985 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Simplify GPIO listsSteven Jian2015-05-272-117/+117
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* cyan: led controlHsu Henry2015-05-271-9/+39
| | | | | | | | | | | | | | New led control from Yuna since it is close to CrOS UI. BUG=chrome-os-partner:37576 BRANCH=cyan TEST="make BOARD=cyan" and check the two factors in CrOS: shutdown=4% and full= 97%. Change-Id: I8aa7ae5f35a3f3f6f15c6131a1f8fb581025de2d Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/272815 Reviewed-by: Mohammed Habibulla <moch@google.com>
* Cyan: add battery cutoff commandHsu Henry2015-05-221-11/+3
| | | | | | | | | | | | | | The battery of cyan only support specific shipmode command. BUG=chrome-os-partner:40464 BRANCH=cyan TEST=verify that "ectool batterycutoff" and "ectool batterycutoff at-shutdown" are workable. Change-Id: I48538d57eda77ae798b3b843252df297c2d8fa81 Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/272414 Reviewed-by: Mohammed Habibulla <moch@google.com>
* Cyan: Add interrupt disable pin for track pad.Hsu Henry2015-05-201-2/+2
| | | | | | | | | | | | | | EVT board should enable it (low) since we need a workable track pad in factory. Pre-EVT board work fine because of unstuffed resistor. BUG=none BRANCH=cyan TEST=Check the pin is low by ec console. Change-Id: I9602534aeadca76e24915d12701b3cd4e801746a Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/272103 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Use CONFIG_BATTERY_CUT_OFF for supported boardsShawn Nematbakhsh2015-05-162-21/+2
| | | | | | | | | | | | | | | | | Common battery cut-off host command / console command infrastructure already exists behind CONFIG_BATTERY_CUT_OFF, so add the config rather duplicating the code at the board level. BUG=chromium:488157 TEST=Manual on Squawks. Verify that both "cutoff" on the ec console and "ectool batterycutoff" succeed to cut-off the battery. BRANCH=None Change-Id: I159026d54924e058ea0262db04d8770c663ee613 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271513 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cyan: enable power button to wake up EC from HIB modeli feng2015-05-131-2/+1
| | | | | | | | | | | | | | | BUG=chrome-os-partner:39082 BRANCH=none TEST=manual Press ALT+H+volume-up to force EC into HIB mode. Then pressing power button will wake up EC. Change-Id: Ie662c8c2c719e75a71b03ef8431752d7961f8237 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/268823 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* driver: Use common data structure to store default accel valuesGwendal Grignou2015-05-121-10/+32
| | | | | | | | | | | | | | | Move structure used by lms6ds0 to motion_sense.h, so that bosh driver can use the same mechanism. Use code to avoid reading chip range when reading data. BUG=none BRANCH=none TEST=Check Bosh driver is working as expected. Change-Id: Id8b5bb8735e479a122ef32ab9a400fba189d7488 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270453 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Move EC_CMD_GSV_PAUSE_IN_S5 handler to common codeShawn Nematbakhsh2015-05-071-0/+1
| | | | | | | | | | | | | | | | The same code exists in four (soon to be five!) different power sequencing drivers, so move it up to common. BUG=None TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console, verify that system again goes to G3 on shutdown. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c Reviewed-on: https://chromium-review.googlesource.com/269566 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Braswell: Turn on/off the USB power while S5->S3/S3->S5.Hsu Henry2015-05-051-2/+2
| | | | | | | | | | | | | | The USB power is off in S5 with previous ChromeBook. The braswell platfrom should be the same as before. BUG=chrome-os-partner:39507 BRANCH=cyan TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console. Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/267451 Reviewed-by: Shawn N <shawnn@chromium.org>
* cyan: Set Motion Sensors to Pre-init state in S3Shamile Khan2015-05-052-4/+24
| | | | | | | | | | | | | | | In S3 state, sensors loose their power. Prevent any initiation of communication with the sensors. BUG=None TEST=With Servo connected, verify that no I2C failures are reported on EC Console when system is brought to S3. BRANCH=None Change-Id: I1988c40aa9de48403e9e3a6be5aec3b7267c29e0 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/268481 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: rename motion sensor CONFIG_ optionsBill Richardson2015-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames some motion sensor options to start with more consistent prefixes. For gesture (tap) detection: CONFIG_GESTURE_DETECTION: CONFIG_SENSOR_BATTERY_TAP => CONFIG_GESTURE_SENSOR_BATTERY_TAP For detecting lid angle: CONFIG_LID_ANGLE: CONFIG_SENSOR_BASE => CONFIG_LID_ANGLE_SENSOR_BASE CONFIG_SENSOR_LID => CONFIG_LID_ANGLE_SENSOR_LID BUG=none BRANCH=none TEST=make buildall Change-Id: Ib8f645902a5585346e1d8d2cbf73d825c896a521 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/268777 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Added task-based Port80 POST code support.Kevin K Wong2015-04-272-0/+3
| | | | | | | | | | | | | | | | | | | | | | With mec1322's EMI set to decode IO 0x800, it does not have any other interfaces to support POST code via IO 0x80. This change is to enable Port80 POST code support via polling method. Limitation: - POST Code 0xFF will be ignored. - POST Code frequency is greater than 1 msec. BUG=chrome-os-partner:39386 TEST=Verified Port80 POST code is captured in EC console. Verified "port80 task" console command will disable/enable Port80 task. Verified "port80 poll" will get the last Port80 POST code. BRANCH=none Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/266783 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cyan: Added changes based on pre-EVT hardware changes.Kevin K Wong2015-04-245-38/+47
| | | | | | | | | | | BUG=none TEST=Verified system is able to boot to kernel. BRANCH=none Change-Id: I7fa4a45bf2209098b5c3794f197d4010c05c356e Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/266835 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: initial version of lfw loaderAndrey Petrov2015-04-231-0/+16
| | | | | | | | | | | | | | | | | | | | | lfw is a customized boot loader with max targeted code size of 4k and data size of 2k.It supports minimal functionalities required to support chromebooks RO/RW architecture.It is placed in the write porected section with RO image . Capabilities include SPI,DMA,UART with minimal debugging support. Currently sysjump support is missing and exception handling is very basic. BUG=chromium:37510 TEST=make buildall -j, flashing and booting on strago BRANCH=None Change-Id: I803998d489297dfe0745dcccbb54412035d73f78 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265904 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i2c: Support multiple I2C ports on the same controllerShawn Nematbakhsh2015-04-222-12/+8
| | | | | | | | | | | | | | | mec1322 I2C controller 0 has two attached ports. Modify the I2C driver so that both ports are usable. BUG=chrome-os-partner:38335,chrome-os-partner:38945 TEST=Manual on strago. Verify that i2cscan is functional. BRANCH=None Change-Id: I18d9d516984d041a38c86fd4ec1b0bfa4e885c9f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/265951 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Changed to generate ec.bin for the firmware binary.Icarus Sparry2015-04-151-4/+0
| | | | | | | | | | | | | | | | | | | | | Previously for the mec1322 chip an ec.bin file was created in the normal way and then it was "packed" in a post-processing stage to produce ec.spi.bin. This change allows a chip or board build.mk file to specify the rules used to produce ec.bin, and uses this for the mec1322 to do the packing. This means that we can use the standard "ec.bin" name, and do not need to alter other scripts, such as the script which creates chromeos-firmwareupdate. BUG=None TEST=buildall -j, flash on strago and see it still works. BRANCH=NONE Change-Id: I3f880d64e60d14f82cb1d21c8b3f2d4ae5e0dfef Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265544 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
* mec1322: Added CONFIG_SWITCH support.Kevin K Wong2015-04-131-1/+0
| | | | | | | | | | | | | This allows switch status to be updated to EC MemMap. BUG=none TEST=Verified mmapinfo console command is reporting the correct info. BRANCH=none Change-Id: I3b6683be8b92b59dffb3227e0a72a122dcda56a2 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265493 Reviewed-by: Shawn N <shawnn@chromium.org>
* gpio: Refactor IRQ handler pointer out of gpio_listAseda Aboagye2015-04-101-86/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the gpio_info struct, we had a irq_handler pointer defined even though a majority of the GPIOs did not have irq handlers associated. By removing the irq_handler pointer out of the struct, we can save some space with some targets saving more than others. (For example, ~260 bytes for samus_pd). This change also brings about a new define: GPIO_INT(name, port, pin, flags, signal) And the existing GPIO macro has had the signal parameter removed since they were just NULL. GPIO(name, port, pin, flags) In each of the gpio.inc files, all the GPIOs with irq handlers must be defined at the top of the file. This is because their enum values from gpio_signal are used as the index to the gpio_irq_handlers table. BUG=chromium:471331 BRANCH=none TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power button, keyboard, charging, all still working. TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build fail. TEST=make -j BOARD=peppy tests TEST=make -j BOARD=auron tests TEST=make -j BOARD=link tests Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263973 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cyan: Move interrupt enabled gpios to topAseda Aboagye2015-04-091-8/+9
| | | | | | | | | | | | | | | | | | All GPIOs with interrupt handlers should be together at the top of the gpio.inc file. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I54926d81c55f25e1ec5ed9a286579cd40b47063c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/264953 Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mec1322: Added CONFIG_KEYBOARD_KSO_BASE to align KBD KSO00 pin to board designKevin K Wong2015-04-091-3/+5
| | | | | | | | | | | | | | | MEC1322 KSO00~03 pin has an alternate JTAG function. For board that needs JTAG function, this #define allows hardware to use a different set of KSO pins. For example - Uses KSO04~16 instead of KSO00~KSO12. BUG=none TEST=Verified keyboard is functional with all keys detected BRANCH=none Change-Id: I1e3c1c2b6a4420cb6296b6bc921affa8c0ed5800 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/264610 Reviewed-by: Shawn N <shawnn@chromium.org>
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