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* led_pwm: support different pwm modulesTing Shen2019-12-271-3/+5
| | | | | | | | | | | | | | | | add enable() and set_duty() into struct pwm_led, to support PWMs other than the default one. BUG=b:135086465 TEST=verify led works on grunt BRANCH=none Change-Id: I1fd919d4990a145df272a7ee0b2072612f80cd44 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1963730 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-011-0/+4
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+3
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* Remove GPIOs for eSPI VW sleep signalsAbe Levkoy2019-10-301-5/+0
| | | | | | | | | | | | | | | | | | Remove non-interrupt GPIO configurations for SLP_S3_L and SLP_S4_L for dragonegg and tglrvpu_ite. The GPIO names thus defined are only referenced in the rest of the codebase if virtual wires are not enabled for those signals, in which case the GPIOs will be configured as interrupts. BUG=b:143288478,b:139553375 TEST=Build dragonegg and tglrvpu_ite BRANCH=none Change-Id: I7b59bb315e333ab62257f206159d95a6d3c6a0ca Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881757 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* icelake: Cleanup GPIO_PCH_DSW_PWROKKeith Short2019-10-151-7/+8
| | | | | | | | | | | | | | | | | | Change GPIO_EC_PCH_DSW_PWROK to GPIO_PCH_DSW_PWROK to match convention for EC to PCH signals used by other Intel processors (specifically cannonlake already used GPIO_PCH_DSW_PWROK). BUG=none BRANCH=none TEST=buildall -j Change-Id: I59fb8d3ee3867c70dde74c186ba3974490c3cd27 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848252 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* driver/tcpm/it83xx: Enable TCPC receive SOP'Ruibin Chang2019-08-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable TCPC receive SOP' for communication with cable, when we are Vconn source role. BUG=None BRANCH=None TEST=test on board: ampton and reef_it8320 1.SRC connects to SNK via E-mark cable, sources Vconn successfully, and receives cable's ack of discover id request. 2.SRC connects to SNK via E-mark cable, but not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 3.console cmd pdcable 0 2019-07-30 11:43:40 > pdcable 0 2019-07-30 11:43:45 Cable Type: Passive 2019-07-30 11:43:45 Connector Type: Type C 2019-07-30 11:43:45 Cable Current: 5A 2019-07-30 11:43:45 USB Superspeed Signaling support: Gen 1 Change-Id: Icd2e6f8481bb7a4e0b922460d46b831f36112738 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1728669 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb: de-dup common code from old and new PD stackJett Rink2019-08-191-1/+0
| | | | | | | | | | | | | | We still need to pull out more common code between the two stacks, but this is scaffolding with a few examples. BRANCH=none BUG=b:137493121 TEST=unit tests pass Change-Id: Ibd9dda1e544e06f02aa3dde48ca7de1539700cfa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1744655 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-14/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* dragonegg: Enable ESPI & MKBP host command configVijay Hiremath2019-01-092-2/+6
| | | | | | | | | | | | | | | | | | | | | | 1. CONFIG_HOSTCMD_ESPI - Enabled host commands over ESPI at baseboard level. 2. CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS - Enabled virtual wire sleep signals. 3. CONFIG_MKBP_EVENT - Enabled MKBP events needed for PD events. 4. CONFIG_MKBP_USE_HOST_EVENT - Trigger MKBP event from host events as there is no dedicated GPIO for it. BUG=b:119091888 BRANCH=none TEST=EC console command 'powerindebug' shows virtual wires Change-Id: Ic2e190c47e8eccbf44cce35e58be797692aebe8d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1318219 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* dragonegg: make PD interrupt use higher priority taskJett Rink2018-10-182-7/+16
| | | | | | | | | | | | | | | | | Start using the higher priority task to handle PD interrupts from C2. Remove higher priority tasks for C0 and C1 since they are handle by chip code in interrupt context method already. BRANCH=none BUG=b:112088135 TEST=dragonegg PD still works Change-Id: I90f2557b73ce6331f012057839e5de22646183c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1283243 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* DragonEgg: Add support to read board version from GPIO strappingsScott Collyer2018-10-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | In preparation for P1 boards, this CL adds support to report board version from gpio strapping pins. BUG=b:117120739 BRANCH=none TEST=Tested on DragonEgg P0 board: ver Chip: ite it8320 dx Board: 0 RO: dragonegg_v2.0.66-cd7027af7 RW: dragonegg_v2.0.66-cd7027af7 Build: dragonegg_v2.0.66-cd7027af7 2018-10-01 16:03:27 scollyer@scollyer.mtv.corp.google.com Change-Id: I62063d1c2e3dd685cc74beb42c962d112b9de4ae Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1256182 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Correct initial value of EC_PCH_RSMRST_LScott Collyer2018-10-041-1/+1
| | | | | | | | | | | | | | | | This signal had been set as GPIO_OUT_HIGH, but it should be initialized as GPIO_OUT_LOW to prevent glitching this signal. BUG=b:111901516 BRANCH=none TEST=make -j BOARD=dragonegg Change-Id: Ief5e100a7b0ecc6448c7259ee60875561d47d4a7 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1257788 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Change USB_A_HIGH_POWER to push-pullScott Collyer2018-10-042-2/+2
| | | | | | | | | | | | | | | | This signal was set to be ODR, but needed to be a push-pull output. This CL corrects this error. BUG=b:113038733 BRANCH=none TEST=make -j BOARD=dragonegg Change-Id: I8445d65bfd93a9656ae8c93e81eb68e984c889ba Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1257787 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add support for 3 color RGB ledScott Collyer2018-10-025-1/+102
| | | | | | | | | | | | | | | This CL adds support required to enable CONFIG_LED_PWM. BUG=b:116753847 BRANCH=none TEST=Verified colors using EC console command ledtest Change-Id: I9982e2d8c5208e65782bd5dfffccb43ec0e0b5fc Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1247921 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* DragonEgg: Add support for BC 1.2 detectionScott Collyer2018-10-022-0/+11
| | | | | | | | | | | | | | | | This CL adds board specific support for BC 1.2 detection. BUG=b:113267982 BRANCH=none TEST=Tested on DragonEgg with both USB DCP and SDP chargers. Verified HW ramp set charge level when attaching suzyq cable. Change-Id: Ic610d3cea62883325a02a7fc9f244764842e424d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208523 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add support for volume buttonsScott Collyer2018-09-263-3/+4
| | | | | | | | | | | | | | | | | | | | This feature wasn't added in the initial image. BUG=b:112623232 BRANCH=none TEST=Tested on DragonEgg. Event: time 1537835576.258487, type 4 (EV_MSC), code 4 (MSC_SCAN), value Event: time 1537835576.258487, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), Event: time 1537835583.549410, type 4 (EV_MSC), code 4 (MSC_SCAN), value Event: time 1537835583.549410, type 1 (EV_KEY), code 114 (KEY_VOLUMEDOWN), Change-Id: Ic4650ac1388a2ee4c5f4c47918051f3f4b1e305d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1244056 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* usb-c: add high priority tasks for interruptsJett Rink2018-09-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To all boards that have space, add the PD tasks that handle interrupts in parallel. This is the last change for go/usb-pd-slow-response-time. BRANCH=none BUG=b:112088135 TEST=buildall. This works on grunt and octopus. This CL is more of a clean up for ToT to ensure that newly copied boards use the correct paradigm. Below is the space taken up by this change: build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584) build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160) build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516) build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800) build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768) build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164) build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860) build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064) build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440) build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444) build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532) build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416) build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392) build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912) build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184) build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680) build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204) build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740) build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992) build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088) build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656) build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248) build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540) build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960) build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288) build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988) build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084) build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512) build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836) build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300) build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340) build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800) build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464) build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772) build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308) build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580) build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540) build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264) Compared 208 of 208 files. 38 files changed. Total size change: -27484 bytes. Average size change: -723 bytes. Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1220667 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* DragonEgg: Add support for port 2 Type CScott Collyer2018-09-133-3/+30
| | | | | | | | | | | | | | | | | This CL adds support for Type C port 2 which uses the TI USB422 TCPC and NX20P3481 PPC. BUG=b:111281797 BRANCH=none TEST=Verifed that port 2 works as a sink and source. Change-Id: I7ad200768d81fd95aee625e5871b2350412a4f79 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178997 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add support to Type C port 1Scott Collyer2018-09-044-2/+25
| | | | | | | | | | | | | | | | | | | | Port 1 uses the ITE builtin TCPC, Silergy SYV682A PPC, and the parade PS8818 redriver. Port 1 is intended to use the EC ADC to detect VBUS, but port 0 and 2 require different methods. The Silergy can detect VBUS (not safe0V or safe5v), so currently the PPC is being used to detect VBUS. BUG=b:111281797 BRANCH=none TEST=Verified that port 1 can attach as both a sink or source. Change-Id: Iad0c3d509961c836cd55f77cd5f276c1a3e5aacf Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159829 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Enable/disable battery learn mode based on ACScott Collyer2018-08-221-0/+43
| | | | | | | | | | | | | | | | | | | | | | This CL is a software workaround for an issue with the bq25710 charger. There is an issue with the converter control loop not being biased correctly when it starts switching. This leads to a reverse current (from battery to charger). To avoid this issue, the switching converter is turned off when AC is not present, then only enalbed 200 msec after AC presence is detected. BUG=b:112372451 BRANCH=none TEST=Veried that reverse buck/boost not present with this CL and that charger still functions as expected. Change-Id: I4d3a975e3c0e24cdf7f13fdab69da32ccd70a428 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1168597 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add config options and task for keyboard scanScott Collyer2018-08-083-5/+13
| | | | | | | | | | | | | | | | Keyboard scan was not working as the KEYSCAN task was not added and some of the keyboard config options were not defined. BUG=b:112110028 BRANCH=none TEST=Verified that keyboard inputs are received now and sent to AP Change-Id: I36c053d807e83477e044857f5087dcccdf891bfa Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159835 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Fix the interrupt associated with GPIO_ACOK_ODScott Collyer2018-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ISR associated with this signal was mistakenly set to power_button_interrupt, but it needs to be extpower_interrupt. This CL fixes the ISR association. BUG=b:111899214 BRANCH=none TEST=Manual With Type C charger connected: > chgstate state = charge ac = 1 batt_is_charging = 1 With Type C charger removed: chgstate state = discharge ac = 0 batt_is_charging = 0 Also verified that the console message [601.408160 running with no battery and no AC] no longer shows up when powering up with no battery connected. Change-Id: I9801bd6e979185824e50f90a3fd4e4efccd34b7f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159699 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add smart control for USB-A port on MLBScott Collyer2018-08-013-0/+14
| | | | | | | | | | | | | | | | | | This CL adds the config options required for USB smart power control for the Type-A port on the MLB. BUG=b:111925860 BRANCH=none TEST=Tested with a USB powered fan. Verified the fan goes off after entering 'aps' on EC console, then turns on with 'powerb' command. Change-Id: I4458fd6edce0517eedf3e0191387821e1232743c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1153473 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add support for Type C port 0, charging, and batteryScott Collyer2018-07-316-0/+102
| | | | | | | | | | | | | | BRANCH=none BUG=b:111281797 TEST=make buildall Change-Id: I2f4342f2c9ddfb4a6b2debbf94c1b0589227b58c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1135928 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add power sequencing supportScott Collyer2018-07-274-9/+45
| | | | | | | | | | | | | | | | This CL enables power sequencing for DragonEgg. BRANCH=none CQ-DEPEND=Iab4423abc9102164d4f43296a279c24355445341 BUG=b:111121615 TEST=make buildall Change-Id: Id8c48a74b7b83153dc253222edc515c2488e7af5 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126407 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: enable EC UARTDino Li2018-07-131-0/+1
| | | | | | | | | | | | | | | EC UART works with this patch. BUG=none BRANCH=none TEST=the debug messages are printed on the UART console. Change-Id: I307331439e34546516199a1f321ffb3f53c1df0a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1133615 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* DragonEgg: Change CHIP_VARIANT to it8320dxDino Li2018-07-111-1/+1
| | | | | | | | | | | | | | | To apply IT8320DX setting on DragonEgg board. BUG=none BRANCH=none TEST=make buildall Change-Id: I5a22a747f4431f2a8b17dcefca973375744ea2e4 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1133078 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add misc pins section to gpio.incScott Collyer2018-07-111-26/+56
| | | | | | | | | | | | | | | | | This CL adds pins to gpio.inc for those signals in the MISC section of the schematic. BRANCH=none BUG=b:110880394 TEST=make buildall Change-Id: I705b4dc5914bb7d174d2c1e7fc68bcea86b4c926 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1119236 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Add I2C pins/alt functions and config tableScott Collyer2018-07-031-0/+20
| | | | | | | | | | | | | | | | | | This CL adds the gpio definitions for I2C pins and the I2C configuration table. BRANCH=none BUG=b:110880394 TEST=make buildall Change-Id: I9d239573257dbd6a3a3110875b1c970721f73677 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1117361 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Rachel Nancollas <rachelsn@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board: it83xx based boards start to use CHIP_FAMILY and CHIP_VARIANTDino Li2018-07-021-0/+2
| | | | | | | | | | | | | With this patch, we can use them in code. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1116632 Reviewed-by: Jett Rink <jettrink@chromium.org>
* DragonEgg: Initial skeleton for DragonEggScott Collyer2018-06-275-0/+144
This CL adds DragonEgg in /board and /baseboard. Only minimal gpio signals are defined to allow successful build. The /baseboard files are currently empty, but the plan is to use baseboard for functions that will be common for ite EC and ILK. BRANCH=none BUG=b:110880394 TEST=make buildall Change-Id: Ia018692f277efaceef85a060b6585accc82fddfd Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1117133 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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