| Commit message (Collapse) | Author | Age | Files | Lines |
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It's simply a bad idea to describe a macro in multiple locations.
It'll make it hard to change. It'll be difficult to keep all
locations in sync.
This patch replaces the comment duplicated in all ec.tasklist with
a pointer to the CONFIG_TASK_LIST definition. The macro will be
described in a single place (just like all/most other macros).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313
Reviewed-on: https://chromium-review.googlesource.com/1551579
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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1. CONFIG_HOSTCMD_ESPI - Enabled host commands over ESPI at
baseboard level.
2. CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS - Enabled virtual wire
sleep signals.
3. CONFIG_MKBP_EVENT - Enabled MKBP events needed for PD events.
4. CONFIG_MKBP_USE_HOST_EVENT - Trigger MKBP event from host
events as there is no dedicated GPIO for it.
BUG=b:119091888
BRANCH=none
TEST=EC console command 'powerindebug' shows virtual wires
Change-Id: Ic2e190c47e8eccbf44cce35e58be797692aebe8d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1318219
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Start using the higher priority task to handle PD interrupts
from C2.
Remove higher priority tasks for C0 and C1 since they are handle by
chip code in interrupt context method already.
BRANCH=none
BUG=b:112088135
TEST=dragonegg PD still works
Change-Id: I90f2557b73ce6331f012057839e5de22646183c6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1283243
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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In preparation for P1 boards, this CL adds support to report board
version from gpio strapping pins.
BUG=b:117120739
BRANCH=none
TEST=Tested on DragonEgg P0 board:
ver
Chip: ite it8320 dx
Board: 0
RO: dragonegg_v2.0.66-cd7027af7
RW: dragonegg_v2.0.66-cd7027af7
Build: dragonegg_v2.0.66-cd7027af7
2018-10-01 16:03:27 scollyer@scollyer.mtv.corp.google.com
Change-Id: I62063d1c2e3dd685cc74beb42c962d112b9de4ae
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1256182
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This signal had been set as GPIO_OUT_HIGH, but it should be
initialized as GPIO_OUT_LOW to prevent glitching this signal.
BUG=b:111901516
BRANCH=none
TEST=make -j BOARD=dragonegg
Change-Id: Ief5e100a7b0ecc6448c7259ee60875561d47d4a7
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1257788
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This signal was set to be ODR, but needed to be a push-pull
output. This CL corrects this error.
BUG=b:113038733
BRANCH=none
TEST=make -j BOARD=dragonegg
Change-Id: I8445d65bfd93a9656ae8c93e81eb68e984c889ba
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1257787
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This CL adds support required to enable CONFIG_LED_PWM.
BUG=b:116753847
BRANCH=none
TEST=Verified colors using EC console command ledtest
Change-Id: I9982e2d8c5208e65782bd5dfffccb43ec0e0b5fc
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1247921
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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This CL adds board specific support for BC 1.2 detection.
BUG=b:113267982
BRANCH=none
TEST=Tested on DragonEgg with both USB DCP and SDP chargers. Verified
HW ramp set charge level when attaching suzyq cable.
Change-Id: Ic610d3cea62883325a02a7fc9f244764842e424d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1208523
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This feature wasn't added in the initial image.
BUG=b:112623232
BRANCH=none
TEST=Tested on DragonEgg.
Event: time 1537835576.258487, type 4 (EV_MSC), code 4 (MSC_SCAN), value
Event: time 1537835576.258487, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP),
Event: time 1537835583.549410, type 4 (EV_MSC), code 4 (MSC_SCAN), value
Event: time 1537835583.549410, type 1 (EV_KEY), code 114 (KEY_VOLUMEDOWN),
Change-Id: Ic4650ac1388a2ee4c5f4c47918051f3f4b1e305d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1244056
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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To all boards that have space, add the PD tasks that handle interrupts
in parallel. This is the last change for go/usb-pd-slow-response-time.
BRANCH=none
BUG=b:112088135
TEST=buildall. This works on grunt and octopus. This CL is more of a
clean up for ToT to ensure that newly copied boards use the correct
paradigm.
Below is the space taken up by this change:
build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584)
build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160)
build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516)
build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800)
build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768)
build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164)
build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860)
build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064)
build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440)
build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444)
build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532)
build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416)
build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392)
build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912)
build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184)
build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680)
build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204)
build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740)
build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992)
build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088)
build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656)
build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248)
build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540)
build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960)
build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288)
build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988)
build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084)
build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512)
build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836)
build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300)
build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340)
build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800)
build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464)
build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772)
build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308)
build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580)
build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540)
build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264)
Compared 208 of 208 files.
38 files changed.
Total size change: -27484 bytes.
Average size change: -723 bytes.
Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1220667
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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This CL adds support for Type C port 2 which uses the TI USB422 TCPC
and NX20P3481 PPC.
BUG=b:111281797
BRANCH=none
TEST=Verifed that port 2 works as a sink and source.
Change-Id: I7ad200768d81fd95aee625e5871b2350412a4f79
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1178997
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Port 1 uses the ITE builtin TCPC, Silergy SYV682A PPC, and the parade
PS8818 redriver.
Port 1 is intended to use the EC ADC to detect VBUS, but port 0 and 2
require different methods. The Silergy can detect VBUS (not safe0V or
safe5v), so currently the PPC is being used to detect VBUS.
BUG=b:111281797
BRANCH=none
TEST=Verified that port 1 can attach as both a sink or source.
Change-Id: Iad0c3d509961c836cd55f77cd5f276c1a3e5aacf
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1159829
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL is a software workaround for an issue with the bq25710
charger. There is an issue with the converter control loop not being
biased correctly when it starts switching. This leads to a reverse
current (from battery to charger). To avoid this issue, the switching
converter is turned off when AC is not present, then only enalbed 200
msec after AC presence is detected.
BUG=b:112372451
BRANCH=none
TEST=Veried that reverse buck/boost not present with this CL and that
charger still functions as expected.
Change-Id: I4d3a975e3c0e24cdf7f13fdab69da32ccd70a428
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1168597
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Keyboard scan was not working as the KEYSCAN task was not added and
some of the keyboard config options were not defined.
BUG=b:112110028
BRANCH=none
TEST=Verified that keyboard inputs are received now and sent to AP
Change-Id: I36c053d807e83477e044857f5087dcccdf891bfa
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1159835
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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The ISR associated with this signal was mistakenly set to
power_button_interrupt, but it needs to be extpower_interrupt. This CL
fixes the ISR association.
BUG=b:111899214
BRANCH=none
TEST=Manual
With Type C charger connected:
> chgstate
state = charge
ac = 1
batt_is_charging = 1
With Type C charger removed:
chgstate
state = discharge
ac = 0
batt_is_charging = 0
Also verified that the console message
[601.408160 running with no battery and no AC]
no longer shows up when powering up with no battery connected.
Change-Id: I9801bd6e979185824e50f90a3fd4e4efccd34b7f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1159699
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL adds the config options required for USB smart power control
for the Type-A port on the MLB.
BUG=b:111925860
BRANCH=none
TEST=Tested with a USB powered fan. Verified the fan goes off after
entering 'aps' on EC console, then turns on with 'powerb' command.
Change-Id: I4458fd6edce0517eedf3e0191387821e1232743c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1153473
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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BRANCH=none
BUG=b:111281797
TEST=make buildall
Change-Id: I2f4342f2c9ddfb4a6b2debbf94c1b0589227b58c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1135928
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL enables power sequencing for DragonEgg.
BRANCH=none
CQ-DEPEND=Iab4423abc9102164d4f43296a279c24355445341
BUG=b:111121615
TEST=make buildall
Change-Id: Id8c48a74b7b83153dc253222edc515c2488e7af5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1126407
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to
CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this
config option indicates that chipset sleep signals (SLP_S3 and SLP_S4)
are tranmitted over virtual wires instead of physical lines with eSPI.
BUG=b:111859300
BRANCH=None
TEST=make -j buildall
Change-Id: Iab4423abc9102164d4f43296a279c24355445341
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1151048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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EC UART works with this patch.
BUG=none
BRANCH=none
TEST=the debug messages are printed on the UART console.
Change-Id: I307331439e34546516199a1f321ffb3f53c1df0a
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1133615
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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To apply IT8320DX setting on DragonEgg board.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I5a22a747f4431f2a8b17dcefca973375744ea2e4
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1133078
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL adds pins to gpio.inc for those signals in the MISC section
of the schematic.
BRANCH=none
BUG=b:110880394
TEST=make buildall
Change-Id: I705b4dc5914bb7d174d2c1e7fc68bcea86b4c926
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1119236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL adds the gpio definitions for I2C pins and the I2C
configuration table.
BRANCH=none
BUG=b:110880394
TEST=make buildall
Change-Id: I9d239573257dbd6a3a3110875b1c970721f73677
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1117361
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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With this patch, we can use them in code.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1116632
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL adds DragonEgg in /board and /baseboard. Only minimal gpio
signals are defined to allow successful build. The /baseboard files
are currently empty, but the plan is to use baseboard for functions
that will be common for ite EC and ILK.
BRANCH=none
BUG=b:110880394
TEST=make buildall
Change-Id: Ia018692f277efaceef85a060b6585accc82fddfd
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1117133
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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