| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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This removes the use of adc_chip.h where adc.h is also used. In this
case, adc_chip.h is redundant.
BRANCH=none
BUG=b:181271666
TEST=buildall passes
Change-Id: Id7baf9aef949447a4d47934242f9bae97c971262
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120317
Reviewed-by: Keith Short <keithshort@chromium.org>
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Update new thermal table
BUG=b:191187610
BRANCH=endeavour
TEST=Thermal team verified thermal policy is expected.
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Change-Id: Icc0a6e49bb2d74559c7a75a981fb69ba5a39ab0f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3034799
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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Rename CONFIG_CROS_BOARD_INFO to CONFIG_CBI_EEPROM to make it clear
that the information comes from on-board EEPROM.
It sets up the groundwork for adding more options of CBI sources later.
BRANCH=None
BUG=b:186264627
TEST=make buildall -j
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I9a6feee0a8b35bbf29e445544243485507767ad8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2945792
Reviewed-by: Philip Chen <philipchen@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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Commands that are send peridically or in high number are not
reported on the console through CONFIG_SUPPRESSED_HOST_COMMANDS
variable.
Use the same set of commands throughout to avoid misses like
newer command EC_CMD_GET_UPTIME_INFO.
BUG=none
BRANCH=none
TEST=buildall
Signed-off-by: Gwendal Grignou <gwendal@google.com>
Change-Id: I0041576538a8cc659c262118b1503777b9ea8578
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2851452
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
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Today some platforms include MKBP_KEYBOARD because they use side buttons,
switches or other events that share the same driver with MKBP keyboard.
Those platforms don't enable KEYSCAN task. The CL is moving key emulation
functionality to MKBP input devices, to make a clear separation
between the real keyboard usage and emulation/buttons/switches/etc.
All boards that were selecting `CONFIG_KEYBOARD_PROTOCOL_MKBP` without
KEYSCAN task are now updated to select `CONFIG_MKBP_INPUT_DEVICES`
BUG=b:170966461
BRANCH=main,firmware-dedede-13606.B,firmware-volteer-13672.B-main
TEST=None
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I515140ebf6e175f4b29991329f92266ffca232a8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2824044
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In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used
throughout. The issue is that the units don't match. In
Zephyr the value is in KiB instead of bytes. This refactor
simply renames CONFIG_FLASH_SIZE in platform/ec to include
the unit (via _BYTES).
BRANCH=none
BUG=b:174873770
TEST=make buildall
be generated by the build instead of per board
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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BUG=b:164194406
TEST=Verified power gets toggled on a warm reboot
BRANCH=master
Change-Id: Ib1fbedcb3db42f3cfc96d4fcb6ec01ca83091e91
Signed-off-by: Pablo Ceballos <pceballos@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2551214
Reviewed-by: Joe Tessler <jrt@chromium.org>
Reviewed-by: Matthew Ziegelbaum <ziegs@chromium.org>
Commit-Queue: Pablo Ceballos <pceballos@chromium.org>
Tested-by: Pablo Ceballos <pceballos@chromium.org>
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Rename CONFIG_I2C_CONTROLLER and related comments.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This will allow userspace to turn PoE ports off and on.
BUG=b:163786867
TEST=manual
BRANCH=none
Change-Id: Ib9716c5ebc6806f79c8cf85843b93d8c1ff0cba3
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354544
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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The PSE controller is unpowered when the AP is not running so it
should be initialized whenever the AP resumes.
It can take up to 15ms after coming out of reset to respond to I2C
accesses so retry as needed.
BRANCH=endeavour
BUG=b:162311755
TEST=EC reboot with various options. Cr50 reboot. Shutdown/power on.
Change-Id: Ic4df0c2ded2c47b30e6ddea945158f664bb77efb
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2332859
Reviewed-by: Joe Tessler <jrt@chromium.org>
(cherry picked from commit 8c5e48f0c7a1d6cd6bf39ab2e6278c6a42e72a4d)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355491
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Update new thermal table
BUG=b:161156507
BRANCH=master
TEST=Thermal team verified thermal policy is expected.
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Change-Id: I144c528b65fd90cc272bbd3879e32a65ccfe693b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2297064
Reviewed-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jeff Chase <jnchase@google.com>
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The polarity signal is 1.8V so needs to be on a GPIO that supports low
voltage.
BUG=b:157236750
BRANCH=none
TEST=build
Change-Id: If125a43ad563ada348712fd6bca035d82723e830
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2265305
Reviewed-by: Joe Tessler <jrt@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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The polarity gpio is used to detect the USB-C plug orientation since
Endeavour does not have a PD controller. This will be read using
ectool by the factory test.
The PSE controller reset signal was moved from PLTRST to an EC gpio
output. Not currently used since we reset using an I2C register.
BUG=b:157236750, b:156399232
TEST=ectool gpioget USB_C0_POL_L, EC_RST_LTC4291_L
BRANCH=none
Change-Id: Ic6abec17654b8d30486f6e4bbb23f70b11d18e43
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2241183
Reviewed-by: Joe Tessler <jrt@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Endeavour has an onboard PoE PSE controller. This change initializes
the controller and sets per port maximum power.
BRANCH=none
BUG=b:155863756
TEST=build + boot, various pse commands
Change-Id: I1505917f6fac8a569f40102162b0d036e8079a36
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2189562
Reviewed-by: Joe Tessler <jrt@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Also remove dead led_alert() code since this board does not use USB-C
power.
BUG=b:151172843
BRANCH=none
TEST=various reboots, power cycles, and suspends
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I60ab17e0bfc15731005ae81682e0cde9fff3f8d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2103050
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Copy fix from puff: d34e19b1c
BUG=b:151172843
BRANCH=none
TEST=boot endeavour; ectool led commands
Change-Id: I7f0dba7a15587607882c9c9ba8f847df201190f2
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2097068
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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The action_delay_sec field hasn't actually been referenced by
any code since 2013. Removing the corresponding struct field.
BUG=None
BRANCH=None
TEST=builds
Change-Id: Ia7334c26b85d0161ff61bb51fbdda61bb921595a
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054945
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring
the benefts to Chromebooks, which are:
- Reduce RO dependency and presence. Allow more code to be updated
in the fields.
- Remove jumptag and workarounds needed for late sysjump.
Major imporvements over v1 are:
- No A/B slot required.
- No signature in RW or public key in RO.
- Rollback-attack protection.
- Verifies only RW being used instead of whole RW section.
For battery-equipped devices, additional benefts are:
- Immediate boot on drained battery.
- Support recovery mode regardless of battery condition.
- Faster charge in S5/G3.
EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm).
EFS2 is documented in go/ec-efs2.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chromium:1045217,chromium:141143112
BRANCH=none
TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode.
TEST=Wake up EC from hibernate.
TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep.
Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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We had removed the EFS config but found that the signer still
needed an EFS key due to RWSIG.
TEST=install and boot in both dev and normal modes
Change-Id: Idc57c6e6868b1d616c8f4dcef1a006e207569284
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2005649
Tested-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jeff Chase <jnchase@google.com>
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There are a number of potential callers that care if there is a battery,
but for boards that don't support batteries (chromeboxes) we can let
them skip implementing this stub.
Tests default to battery present, but they can provide their own
per-test implementation if desired.
Some PD battery presence checks have been disabled when battery support
is disabled; these are irrelevant when there is no battery, and they
cause linking failures because they depend on both the charge manager
and battery presence.
BUG=b:146504182
BRANCH=none
TEST=buildall
Change-Id: Ifad6a9e356c8ac2146b09bc83b359a7c55adc1a7
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980099
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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- Update the GPIO and USB/I2C port lists following the Endeavour schematic
- Endeavour does not use a software-controlled TCPC so remove USB PD
- Remove LED panel
- Remove CEC
- Add OEM_ID
BUG=b:143780700
TEST=emerge-endeavour chromeos/ec
Change-Id: Idb554a4f87369ea1c42de0a1532ce11d28e4da56
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902407
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jeff Chase <jnchase@google.com>
Tested-by: Jeff Chase <jnchase@google.com>
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BUG=b:143780700
TEST=emerge-endeavour chromeos-ec
Change-Id: Ib2cec6df3ab6a89a1b7bb278f231cb6b6da4f3ce
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893543
Tested-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jeff Chase <jnchase@google.com>
Auto-Submit: Jeff Chase <jnchase@google.com>
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