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* Swap system_jumped_to_this_image with system_jumped_latestabilize-quickfix-13310.91.B-masterstabilize-quickfix-13310.76.B-masterstabilize-quickfix-13310.73.B-masterstabilize-13310.99.B-masterstabilize-13310.94.B-masterstabilize-13310.83.B-masterstabilize-13310.74.B-masterstabilize-13310.72.B-masterrelease-R85-13310.B-masterDaisuke Nojiri2020-06-261-2/+2
| | | | | | | | | | | | | | | | | | | | EFS2 boards need to call system_jumped_late in HOOK_INIT to avoid running init code twice per boot. system_jumped_to_this_image and system_jumped_late are functionally equivalent for non EFS2 boards. This patch will prevent system_jumped_to_this_image from being used for EFS2 boards when code is copied from a past project. BUG=chromium:1072743 BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I73fb5cedc5325d1c80825f9346954013046ee1df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2267685 Reviewed-by: Keith Short <keithshort@chromium.org>
* PD: Remove unnecessary PDCMD taskDiana Z2020-05-201-1/+0
| | | | | | | | | | | | | | | | | | | The PDCMD task is only pulling interrupts from the TCPCs on most boards, which is unnecessary since the PD_INT tasks handle this job now. Remove it from any boards using the PD_INT command which are not using the older CONFIG_HOSTCMD_PD functionality (ex. samus, oak). Located boards using: find -name "ec.tasklist" | xargs grep -l PD_INT | xargs grep PDCMD BRANCH=None BUG=b:154959596 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I29be8ab1d7a2616603fb55236aed4329ed8654f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2208221 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd: Rename CONFIG_CMD_PD_CONTROL to CONFIG_HOSTCMD_PD_CONTROLVijay Hiremath2020-05-151-1/+1
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Various boards: Shrink UART Tx buffer to save spaceAbe Levkoy2020-05-011-0/+2
| | | | | | | | | | | | | | | | Future USB-PD discovery changes will need that space. In each case, reduce the size of the buffer by half (must be a power of 2). Note: This change is only to save shared memory space in the ToT build. It should not be picked onto release branches. BUG=b:152420269,b:152419795 TEST=make buildall BRANCH=none Change-Id: Ia26c1cdd7eb4068d410b81bb4a3335d2c9142049 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163795
* driver: Replace BMI160 to BMI in board configChing-Kang Yen2020-04-232-7/+7
| | | | | | | | | | | | | | | | | Replace some macro of BMI160 to BMI version for common function of BMI series. Make board config include the accelgyro_bmi_common.h instead of accel_gyro_bmi160.h. BRANCH=None BUG=b:146144827 TEST=make buildall -j Change-Id: I043ff8a92f15295ead3fa5c1e292319e2b4fa21a Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2156525 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common/keyboard_vivaldi: New keyboard framework for custom layoutRajat Jain2020-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vivaldi is a new keyboard that allows individual boards to have additional or different top row keys and/or to reorder those keys. The primary agenda of vivaldi is to allow customization of the top row keys. However, as a secondary objective, it also allows coreboot to send a keymap to the kernel, for only the keys that are actually present on the keyboard. As part of enabling vivaldi, another feature that get enabled is to start sending action codes instead of function codes for the top row of the keyboard. go/vivaldi-prd go/vivaldi-design go/vivaldi-fw-design With this patch, things remain unchanged for any boards that do not provide board_set_vivaldi_keybd_config(). For boards that do provide it: * EC begins to send action scancodes instead of function scancodes for the top row when top row keys are pressed. * EC responds to an EC command from the coreboot, that asks for the layout for the keyboard. Coreboot uses this to expose corresponding keycodes to the kernel. BUG=b:146501925 TEST=Check on Jinlon the (new) expected scancodes are output from EC. BRANCH=firmware-hatch-12672.B Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I1f45ce6eee138a984f8d4caef1ec76c9538dd30b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2135566
* common: Make scancode table always mutableRajat Jain2020-04-212-4/+3
| | | | | | | | | | | | | | | | Since the vivaldi requires the scancode to be mutable, and vivaldi shall be enabled by default for all boards, thus make the scancode table to be always mutable and get rid of the config option it hides behind. BUG=b:146501925 TEST=Build BRANCH=firmware-hatch-12672.B Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: Iaedcd6d84caf31c91a61854f96414bcea38f5c2a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2133825 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_mux: retimer: mux as chained mux and retimerDenis Brockus2020-02-281-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes retimers appear as generic muxes. By allowing a chain of muxes they can be stacked up to the new configurations that zork requires and will continue to work as they did before on configurations that only have a single mux. The code used to have two different arrays, 1) muxes and 2) retimers. On one of the zork configurations the processor MUX stopped being the primary mux and the retimer took its place. In a different configuration of that same platform it left the primary and secondary alone but the mux_set FLIP operation had to be ignored. Since the same interfaces needed to be available for both it stopped making sense to have two different structures and two different methods of handling them. This consolodates the two into one. The platforms that do not have retimers, this change will not make any difference. For platforms like zork, it will remove the retimers and make them chained muxes. So testing on trembyle makes sense to verify, BUG=b:147593660 BRANCH=none TEST=verify USB still works on trembyle Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMV1/2: Make the PD Config Flags more consistentSam Hurst2020-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | The current use of the PD Config Flags are a bit confusing and has been changed to the following: The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY is enabled, one of the following must be enabled: CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine CONFIG_USB_PD_TCPMV2 - current power delivery state machine BUG=b:149993808 BRANCH=none TEST=make -j buildall Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Temp sensor: Remove action_delay_sec fieldDiana Z2020-02-141-6/+6
| | | | | | | | | | | | | | The action_delay_sec field hasn't actually been referenced by any code since 2013. Removing the corresponding struct field. BUG=None BRANCH=None TEST=builds Change-Id: Ia7334c26b85d0161ff61bb51fbdda61bb921595a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054945 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Charger: Convert boards to use new driver structureDiana Z2020-02-041-0/+9
| | | | | | | | | | | | | | | This commit removes the temporary common charger chip configuration and instead puts the configuration in each board. BRANCH=none BUG=b:147672225 TEST=builds, runs on waddledoo and octopus Change-Id: If81aef31e48c65999a87e202494f286716114bbb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Charger: change get_vbus_voltage to return EC errorDiana Z2020-01-281-1/+6
| | | | | | | | | | | | | | | The other driver structure members return an ec_error_list value and fill in parameters to return data. This commit changes the get_vbus_voltage call to follow that model. BRANCH=None BUG=b:147672225 TEST=builds Change-Id: I7308502a9734274dd308b830762493c4d70d147a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015340 Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: cleanup pd_get_data_roleDenis Brockus2020-01-091-1/+2
| | | | | | | | | | | | | | | This is the second half of b/147290482 Cleaning up to use pd_data_role instead of int BUG=b:147314832 BRANCH=none TEST=make buildall -j Change-Id: I2445b06f5f5469fb1f3a968034a83e3ee792e7c7 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991845 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* board: Set Accelerometer range to 4gGwendal Grignou2019-12-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Required by Android CDD - Section 7.3.1 - Paragraph C.1.4 Modified mechanically with: for i in $(grep -lr "\.default_range" board); do sed -i '/.default_range =/s#\(.*\.default_range = \).* /\ \* g.*#\14, /* g, to meet CDD 7.3.1/C-1-4 reqs */#' $i done Manually reworked to only change the accelerometer that matters to android: The lid accelerometer or the base accelerometer if the base also hosts the gyroscope. This is only for future EC, no need to land the change on branches: mems_setup will take care to set accelerometer ranges at 4g on startup. BUG=b:144004449 BRANCH=none TEST=compile Change-Id: If8c14b2e928c9c70c0ce51451adcfcd674a9e73b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957375 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* usb_pd_policy: Make a lot of objects commonAseda Aboagye2019-12-101-307/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a board specific usb_pd_policy.c file that contains a lot of code for handling DisplayPort Alternate mode, Google Firmware Update Alternate mode, as well as some PD policy functions such as deciding to Accept or Reject a data role swap or a power role swap. Several boards simply copy/paste this code from project to project as a lot of this functionality is not actually board specific. This commit tries to refactor this by pulling the functions that are not mainly board specific into common code. The functions are made overridable such that boards that truly do require a different implementation may do so. Additionally, this consolidation changes the policy behaviour for some boards, but they should be for the better. Some examples include that data swaps are always allowed if we are a UFP (no system image requirement), power swaps are allowed to become a sink if we are no longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is not entered if the AP is off. In order to facilitate this refactor, a couple CONFIG_* options were introduced: - CONFIG_USB_PD_DP_HPD_GPIO /* HPD is sent to the GPU from the EC via a GPIO */ - CONFIG_USB_PD_CUSTOM_VDO /* * Define this if a board needs custom SNK and/or SRC PDOs. * * The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating * Dual-Role power, USB Communication Capable, and Dual-Role data. * * The default SNK PDOs are: * - Fixed 5V/500mA with the same PDO_FIXED_FLAGS * - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV, * operational current PD_MAX_CURRENT_MA, * - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power * PD_OPERATING_POWER_MW */ BUG=chromium:1021724,b:141458448 BRANCH=<as many as we can that are still supported> TEST=`make -j buildall` TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety of DP peripherals TEST=Repeat above with a nocturne TEST=Repeat above with an atlas Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Clean up double tap related definitionHeng-Ruey Hsu2019-11-131-2/+2
| | | | | | | | | | | | | | | | Fixes: commit 2f2a81079191ca "Add double tap and make motion sense wake up ap" CONFIG_GESTURE_DETECTION_MASK includes significant motion in activity list. We cannot use it for double tap. Add more flags to distinguish it. BUG=b:135575671 BRANCH=kukui TEST=AP can receive mkbp event when double tap is triggered Change-Id: I13776a01b14dc251396a615c8c97353f2d0477d4 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911263 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-014-9/+10
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-311-1/+1
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+2
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* config: Refactor CONFIG_ACCEL_FIFO to enable use of IS_ENABLEDYuval Peress2019-09-031-3/+4
| | | | | | | | | | | | | | | This change allows us to use the IS_ENABLED condition to replace the various ifdef guards around the CONFIG_ACCEL_FIFO BUG=b:137758297,chromium:981990 BRANCH=None TEST=buildall and CTS tests on Arcada Change-Id: I65d36bac19855e51c830a33e6f3812575e8d15d9 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704164 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-202-24/+24
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-192-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-132-21/+0
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-8/+10
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: motion_sense: Require CONFIG_MOTION_SENSOR_MAX_COUNTYuval Peress2019-06-051-0/+1
| | | | | | | | | | | | | | | This changes requires all boards to define the maximum number of sensors they support. This will allow us to later create static arrays with the appropriate length. BUG=chromium:966506 BRANCH=None TEST=make buildall Change-Id: I5a2fa8f0fdcaef69065dfd4c2bfea4e3f371e986 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1637414 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-04-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-14/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion: Define macros for custom eventsGwendal Grignou2019-03-201-3/+4
| | | | | | | | | | | | | | Define macros to define custom events used by sensor interrupt handlers. Remove CONFIG_ for activity events. BUG=none BRANCH=none TEST=compile, sensors work on eve. Change-Id: I08ef6ed2a004466ebc5f7650d6952a150b9de713 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1272189 Reviewed-by: Jett Rink <jettrink@chromium.org>
* eve: Set BMI160 INT2 as outputGwendal Grignou2019-02-281-0/+1
| | | | | | | | | | | | | This pin is not used, set it as output to clean FIFO messages. BUG=chromium:917868 BRANCH=eve TEST=Check fifo headers. Change-Id: Ib2b783ea65b1ecb56e831440367d043b86022e51 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1390939 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* eve: Set power state for sensors properlyGwendal Grignou2019-02-281-2/+2
| | | | | | | | | | | | | | | | | | | BMI160 and BMM150 are powered by PP3300_DSW, so they are up all the time. No need to reinitialize them when moving to S0. BUG=chromium:917868 BRANCH=eve TEST=Using ToT firmware on eve, check gyro and magnetometer are not initialized when device boots. Change-Id: I7f46b82aaf8cc92bb60c7963d04dd04043cdaadb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1390938 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* config: Add magnetometer definitionsGwendal Grignou2019-02-081-1/+1
| | | | | | | | | | | | | | | | | | | Add all possible supported or soon-to-be supported configuration of magnetometer behind accelerometers. Use a more generic variable to indicate the i2c address of the secondary device. BUG=b:110143516,b:115587004 BRANCH=none TEST=compile Change-Id: Ic00c413f2ec5fa0e6bf1c98861daa02f00769a65 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361989 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* eve: Enable support for multi-profile DPTFFurquan Shaikh2018-11-152-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | This change enables support for multi-profile DPTF on eve, which uses a hall sensor. Thus the following changes are made: 1. Select config CONFIG_DPTF_MULTI_PROFILE 2. Set profile number based on the TABLET_MODE_L GPIO state (input from the hall sensor indicating completely flipped mode). This change is being done only as a reference for future boards with hall sensors to enable multi-profile DPTF. DO NOT cherry-pick this to any eve branch. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:117844490 BRANCH=None (Do not cherry-pick to any eve branch) TEST=make -j buildall Change-Id: I71e2078d8f63cc4d5939b76ffca962f041a48e42 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313471 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* usb-c: use higher priority task for interruptsJett Rink2018-11-141-9/+12
| | | | | | | | | | | | | | | | | This should be the last step to make all boards on ToT follow go/usb-pd-slow-response-time. Theses boards all have the higher priority tasks, but they aren't being used since the tcpc interrupt wasn't scheduling calls on it. BRANCH=none BUG=b:112088135 TEST=builds Change-Id: I2c39e661e804f88edd5b34636b93e6e63a5af57f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1283452 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* dptf: Get rid of CONFIG_DPTF_DEVICE_ORIENTATIONFurquan Shaikh2018-10-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to the host to allow it to read the tablet mode flag from shared EC memory and select the right DPTF table to load (if supported). However, this config seems unnecessary because of the following reasons: 1. Host sets SCI mask to indicate to the EC which events it wants to process. Thus, even if the EC sets mode change flag, it will not be notified to the host unless it supports mode change event. 2. Additionally, if host supports mode change event, but does not support multiple DPTF tables, then EC ACPI code takes care of ensuring that there is a thermal event handler present to reload tables. 3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86 boards. BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ic4097ae047e2d559673a321da4df86514f902993 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1292359 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Keyboard: switch column and row of scancode tableDaisuke Nojiri2018-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches column and row of scancode_set2. That is, scancode_set2[ROWS][COLS] = {0x00, 0x01, 0x02, ..., 0x10, 0x11, ..., 0x20, ..., becomes scancode_set2[COLS][ROWS] = {0x00, 0x10, 0x20, ..., 0x01, 0x11, ..., 0x02, ..., This will allow us to extend the table for a keypad without losing too much readability. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona. Change-Id: I49a7c0796d5c91989f1d3686c80743fb4bcd5ba7 Reviewed-on: https://chromium-review.googlesource.com/1285291 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-2/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* usb-c: add high priority tasks for interruptsJett Rink2018-09-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To all boards that have space, add the PD tasks that handle interrupts in parallel. This is the last change for go/usb-pd-slow-response-time. BRANCH=none BUG=b:112088135 TEST=buildall. This works on grunt and octopus. This CL is more of a clean up for ToT to ensure that newly copied boards use the correct paradigm. Below is the space taken up by this change: build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584) build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160) build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516) build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800) build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768) build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164) build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860) build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064) build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440) build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444) build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532) build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416) build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392) build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912) build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184) build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680) build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204) build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740) build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992) build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088) build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656) build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248) build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540) build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960) build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288) build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988) build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084) build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512) build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836) build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300) build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340) build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800) build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464) build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772) build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308) build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580) build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540) build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264) Compared 208 of 208 files. 38 files changed. Total size change: -27484 bytes. Average size change: -723 bytes. Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1220667 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* keyboard: display keycap label in key status debug messagesNamyoon Woo2018-09-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current debug message in keyboard_8042.c displays a tuple of row, column, and press status. Additionally, this CL displays a keycap label for better readability. For keycap label mapping table can be adjustable under "CONFIG_KEYBOARD_SCANCODE_MUTABLE" condition as scancode_set2[] is. For coral board, Enabling CONFIG_KEYBOARD_DEBUG (w/o this CL) occupies 652 bytes in flash, and this CL occupies another 312 bytes. BUG=b:111060830 TEST=manually tested by pressing keyboards and check the EC console screen. BRANCH=kblog Signed-off-by: Namyoon Woo <namyoon@chromium.org> Changes to be committed: modified: board/eve/board.c modified: common/keyboard_8042.c modified: common/keyboard_8042_sharedlib.c modified: include/keyboard_8042_sharedlib.h Change-Id: Idd71a5475b1ee313f99e087be9143dcfb6f81550 Reviewed-on: https://chromium-review.googlesource.com/1214543 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* type: Rename matrix_3x3_t to mat33_fp_tYilun Lin2018-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming of many vector types and matrix types are not clear enough. For example, we have: vector_3_t, which is a vector of three int. vec3_t, which is a vector of three float. size4_t, which is a vector of four size_t. mat33_t, which is a 3x3 matrix of float. matrix_3x3_t, which is a 3x3 matrix of fixed point. Besides, we have types like int8_t, uint16_t types. To clearly distinguished types, the CL propose to, For vector types, naming should be `$type + 'v' + $num + '_t'`: vector_3_t becomes intv3_t vec3_t becomes floatv3_t vector 4 of uint16_t becomes uint16v4_t (which doesn't exist yet) For matrix types, naming should be `mat$N$N_` + $type + '_t', where $N is the matrix size: matrix_3x3_t becomes mat33_fp_t # fp: fixed point mat33_t becomes mat33_float_t TEST=make buildall -j BUG=b:114662791 Change-Id: I51d88d44252184e4b7b3564236833b0b892edc39 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1215449 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* keyboard: Keep only scan code set 2 table and do translation for set 1.Hung-Te Lin2018-08-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The 8042 scan code set 1 can be directly translated from set 2, with a 256 byte table. With this change, we can always process key stroke in scan code (set 2), and only translate in the single function `scancode_bytes`. This is very helpful when we need to do key processing, for example the buttons_8042 can now be simplified with only one scan code. And is extremely helpful if we want to do dynamic translation (i.e., to prevent something like CL:1164725). For `make BOARD=samus', the free space is also increased from 18472 to 18656 (+184) bytes. BUG=None TEST=make buildall; manually installed on Eve and tested by running 'keyboard' factory test to make sure all key scancodes are not changed. BRANCH=None Change-Id: Ieb303d84edcd4375bbeb1ea5f032d0462bbfd250 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1166742 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* eve: Delay charge port selection until VBUS is stable or 1s has passedSam Hurst2018-08-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a charge port is selected and VBUS is 5V, the inrush current causes VBUS to droop which could signal a sink disconnection. To mitigate this problem, charge port selection is delayed until VBUS is stable or 1s has passed. Before 1s has passed, PD will hopefully have negotiated a VBUS voltage of at least 9V. This CL is also a workaround for the issue outlined in b:74753447 Signed-off-by: Sam Hurst <shurst@chromium.org> BUG=b:69439094 BRANCH=None TEST=`make -j buildall` Manual tested with Belkin Express Dock and Moshi audio adapter. Test Belkin with following configuration: PORT0: PORT1: Belkin OPEN OPEN Belkin Belkin Blackcat Blackcat Belkin Belkin EC terminal output: Port 0: [654.645288 TCPC p0 Exit Low Power Mode] C0 st14 C0 st15 C0 st17 C0 st18 C0 st19 Requested 5000 V 3000 mA (for 900/900 mA) C0 st20 C0 st21 C0 st22 C0 st23 C0 st24 C0 st23 C0 st26 C0 st27 C0 st28 C0 st29 [655.375668 New chg p0] C0 st5 [655.380708 Ramp reset: st1] [655.381704 CL: p0 s8 i500 v5000] [655.392598 New chg p0] [655.393574 Ramp reset: st1] [655.394504 CL: p0 s2 i3000 v5000] C0 Req [4] 15000mV 3000mA [655.512126 New chg p0] [655.514456 Ramp reset: st1] C0 st715219 CL: p0 s0 ] C0 st8 [655.639762 Ramp reset: st1] [655.640301 CL: p0 s0 i3000 v15000] [656.688735 AC on] [657.385539 Ramp p0 st5 3000mA 3000mA] [657.471108 Battery 70% / 7h:36 to empty] [659.721858 charge_request(8800mV, 5376mA)] [660.973258 charge_request(8800mV, 3712mA)] [697.506594 Battery 71% / 1h:1 to full] Port 1: [729.384242 TCPC p1 Exit Low Power Mode] C1 st2 C1 st3 C1 st14 C1 st15 C1 st17 C1 st18 C1 st19 Requested 5000 V 3000 mA (for 900/900 mA) C1 st20 C1 st21 C1 st22 C1 st23 C1 st24 C1 st23 C1 st26 C1 st27 C1 st28 C1 st29 [730.339719 New chg p1] [730.340602 Ramp reset: st1] [C1 st5 730.341457 CL: p1 s8 i500 v5000] [730.356552 New chg p1] [730.357311 Ramp reset: st1] [730.358095 CL: p1 s2 i3000 v5000] C1 Req [4] 15000mV 3000mA [730.478577 New chg p1] [730.480986 Ramp reset: st1] [730.481829 CL:Cp1 s0 i500 v15] C1 st8 [730.607116 Ramp reset: st1] [730.607813 CL: p1 s0 i3000 v15000] [731.654877 AC on] [732.345420 Ramp p1 st5 3000mA 3000mA] [732.589802 Battery 71% / 10h:28 to empty] [734.340030 charge_request(8800mV, 5376mA)] [735.091263 charge_request(8800mV, 3712mA)] [767.879314 Battery 72% / 1h:1 to full] Tested Moshi with followint configuration: Port0: Port1: Moshi-pwr OPEN OPEN Moshi-pwr Moshi-pwr Blackcat Blackcat Moshi-pwr Moshi-audio OPEN OPEN Moshi-audio Moshi-audio Blackcat Blackcat Moshi-pwr Moshi-pwr-audio OPEN OPEN Moshi-pwr-audio Moshi-pwr-audio Blackcat Blackcat Moshi-pwr-audio Moshi EC terminal output: [2330.883267 TCPC p0 Low Power Mode] [2330.883664 TCPC p0 reset!] [2330.916049 TCPC p0 Low Power Mode] [2330.916475 TCPC p0 reset!] [2330.934010 TCPC p0 Exit Low Power Mode] C0 st14 C0 st15 C0 st17 C0 st18 C0 st19 Requested 5000 V 3000 mA (for 3000/3000 mA) C0 st20 C0 st21 C0 st22 C0 st23 C0 st24 C0 st23 C0 st26 C0 st23 C0 st27 C0 st28 C0 st29 [2332.398132 New chg p0] [2332.398883 Ramp reset: st1] [2332.399745 CL: p0 s8 i500 v5000] C0 st5 [2332.476132 New chg p0] [2332.476933 Ramp reset: st1] [2332.477705 CL: p0 s2 i3000 v5000] C0 Req [4] 15000mV 2970mA [2332.493597 New cCg p0C0 st7 ] [2332[2332.5001C0 st8 [2332.674727 Ramp reset: st1] [2332.675510 CL: p0 s0 i2970 v15000] [2333.668216 AC on] [2334.403481 Ramp p0 st5 2970mA 2970mA] [2334.450155 Battery 80% / 11h:18 to empty] [2335.448877 charge_request(8800mV, 5376mA)] [2336.699875 charge_request(8800mV, 3712mA)] [2356.466385 Battery 81% / 1h:1 to full] Change-Id: Iba909c252094c0e5ca4cf974aabcfe1eaf002efd Reviewed-on: https://chromium-review.googlesource.com/1130000 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver: bmi160: Rename secondary i2c device addressGwendal Grignou2018-06-151-1/+1
| | | | | | | | | | | | Make it more generic, to support other magnetometer. BUG=b:110143516 BRANCH=none TEST=Compile Change-Id: I94cbbe6daf598680a2decde12d703650dfb7c04c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1101548
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/npcx: Increase default stack size for tasksNicolas Boichat2018-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | Usually, we enable CONFIG_FPU on NPCX, which requires larger stack size. Also, NPCX has very deep call patch in I2C transactions (in particular, I2C recovery path), so it generally requires larger stack. To make the code fit, however, we need to reduce the accelerometer fifo depth from 1024 to 512, on a few boards. BRANCH=none BUG=b:75234824 TEST=make buildall -j, stackanalyzer result on poppy looks a little better. Change-Id: I37b5a2a97a760dc4fd225253c23962d74e25605a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967963 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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