| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch sets the max PD power to 100W. It means if all devices
(chager, cable, Fizz) agree, the system can draw upto 100W from
a type-c charger.
BUG=b:70239357
BRANCH=none
TEST=Boot Fizz with Apple 87W charger and verify chgsup comamnd
prints 86W (20V, 4.3A). Boot Fizz with Zinger and verify chgsup
command prints 60W (20V, 3.0A).
Change-Id: I74885c5655f570a91eea49660d537d4f9338356c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/810004
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Fizz EC doesn't have IADP_ACMON_BMON. So, this ADC channel can't
be used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I13a4fd4cbb638af731d5bbe3404bfa6a97a2950d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/803895
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Usually, the max current and supply voltage of dedicated chargers
are not known to the EC.
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
allows the host to change the max current and supply voltage of the
dedicated charge port.
BUG=b:64442692
BRANCH=none
TEST=make runtests && buildall. Boot Fizz and let coreboot set
the adapter current and voltage.
Change-Id: I29b3f5762f8b316ca363c23e230530cdf4ca207a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/769152
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Nearly every board had a buttons array defined in which its contents had
the standard volume buttons. This commit creates a single common
buttons array that can contain the standard volume buttons and recovery
buttons. If a board has volume up and down buttons, they can simply
define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with
the standard definition. The buttons are active low and have a 30 ms
debounce period. Similiarly, if a board has a dedicated recovery
button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the
buttons array with a recovery button.
BUG=chromium:783371
BRANCH=None
TEST=make -j buildall.
TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume
buttons still work.
Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/773794
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch allows Fizz to switch the power source from a type-c
charger to a barrel jack adapter if the system is in S5.
BUG=b:38321259
BRANCH=none
TEST=Verify the following with 45W and 60W type-c chargers:
1. Boot Fizz with a type-c charger
2. Go to S5 if not already.
3. Plug in a BJ adapter. Fizz boots to S0 using BJ power.
Also verified other boot modes are not affected:
1. Auto boot on BJ insert
2. Auto boot on Type-C insert
3. Recovery boot on BJ
4. Recovery boot on Type-C
5. Stay off if it's previously S5
Change-Id: I86aa0fe6e403bcbacfe396997d897111ffcf8e74
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/706251
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Fizz blinks the power LED to alert a user when power supply isn't
enough. This patch makes the blinking speed twice as fast (on:1sec,
off:1sec).
BUG=b:37646390
BRANCH=none
TEST=Verify the LED blinks as intended.
Change-Id: I017eaf36b91d987f4b03308b1e9ac8781e5f217d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/757557
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Fizz has no battery, so any port / ILIM selection logic that could lead
to de-powering the device should be relaxed.
BUG=b:68953563
BRANCH=None
TEST=Boot fizz with both zinger and barrel charger, verify no panic /
brownout occurs.
Change-Id: I3bf353f5a26fe6210c67f8ee3f785012d4c063f0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/756924
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Modify thermal table for Fizz
reference patches: 627542, 288256, 329359
on off RPM
step0 0
step1 16 2 2800
step2 27 18 3200
step3 35 29 3400
step4 43 37 4200
step5 54 45 4800
step6 64 56 5200
step7 97 83 5600
Prochot degree:
active when t >= 88C
release when t <= 85C
Shutdown degree: when t >= 90C
BUG=b:67487721, b:64439568
BRANCH=master
TEST=fan target speed follows table, make -j buildall pass
Change-Id: I3378668a560b8ddc568fe9cbf2703613fad8e4b6
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/729606
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Charge port / current selection often needs to be significantly altered
when a battery cannot provide sufficient charge, so have charge_manager
initially enter safe mode. After a battery with sufficient capacity has
been identified, charge manager will leave safe mode, and port / current
selection will return to standard rules.
BUG=chromium:777596
BRANCH=None
TEST=Pass charge_manager unit tests. On kevin, remove battery, attach
Apple PD charger, verify safe mode is not exited and device does not
brown out. Hot-plug battery and verify safe mode is exited. Next,
remove battery, attach to Samus, verify safe mode is not exited and
device doesn't brown out. Hot-plug battery, verify that safe mode is
exited and no active charge port, due to dual-role exclusion.
Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/733954
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The registers seem to be the same for the TPS650930, therefore, this
commit just renames the register map to have a more generic name.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: Ib1c604b29e7f0e47cc036e042fe597f644d7ad36
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736311
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch makes EC notify the host of BJ plug or unplug event
by triggering EC_HOST_EVENT_PD_MCU. The host can then use
EC_CMD_PD_HOST_EVENT_STATUS to get event details.
BUG=b:67060237
BRANCH=none
TEST=Boot Fizz on Type-C. Plug/unplug BJ adapter. Verify host event
is set by hostevent. Verify available_charge is set by hacking
chgsup command.
Change-Id: I1831bec9715e0191cb9610e05d08bbc08347b513
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/692848
Reviewed-by: Shawn N <shawnn@chromium.org>
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According to the USB-C spec, when a debug accessory is identified, we may
optionally establish USB PD communication over CC. Some DTS partners
(eg. servo_v4) expect us to speak PD, so let's make it so. There is no
need for special ACCESSORY states, these do not exist in the PD spec.
BRANCH=servo
BUG=chromium:737755,b:65837068
TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify
EC and cr50 consoles are available through servo_v4.
Change-Id: I59d1ca50b4766509eccf38562cdf926578138585
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/693294
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This patch is to enable fan through PWM4 output and TACH feedback
from TA2 GPIOA6, and move EC_PLATFORM_RST to GPIO45.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz chromeos-ec and use fanduty and faninfo from EC
console to control and check fan status. Probed oscilloscope
on PWM output and checked the duty as expected. Made sure the
fan was stopped when DUT entered S3 and was running when DUT
resumed from S3.
Change-Id: I09f3ac43d2e4170b2aff3830f832bc5fd46a15c0
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/627542
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Fizz allocates 15W to the type-c port. This patch allows the port
to use it.
BUG=b:67682343
BRANCH=none
TEST=Verify 5V 3A PDO is offered.
Change-Id: I1560c0c7cb04379f5e4c9893753afe4a7f0cefe4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/713583
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This patch undefines CONFIG_SYSTEM_UNLOCKED, which forces the system
to be unlocked, and defines CONFIG_USB_PD_COMM_LOCKED, which enables
PD only if EC is in RW. With this change, if SW write-protect is
enabled, the system will stay in G3 until 50W or more power is
supplied.
BUG=b:38462249
BRANCH=none
TEST=Lock Fizz and boot it on type-c adapter. Verify RW image is
successfully verified and executed.
Change-Id: Id8255c5c8e6af93bda3fd4de079008561f46e14c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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On proto3, PMIC isn't powered on POR, thus board_pmic_init fails.
With this change, EC waits until AP power is ready before it
notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized.
When AP power is ready, PMIC should be ready as well.
BUG=b:65839247,b:64944394
BRANCH=none
TEST=Run reboot [/cold/ap-off] command on BJ and Type-C.
Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b
Reviewed-on: https://chromium-review.googlesource.com/672152
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Fizz EC verifies RW by itself and jumps to RW before AP boots.
If this fails, the system needs recovery. Since EC isn't
capable of showing any info on a display, we use the power
LED to inform the user.
BUG=b:66914368
BRANCH=none
TEST=Make Fizz fail RW verification. Observe LED illuminates
in red.
Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683218
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This patch makes the LED blink to alert the user when there is
not enough power to boot the system.
This patch also changes minimum boot power to 50W. It's common
for all SKUs.
BUG=b:37646390
BRANCH=none
TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as
expected.
Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/682876
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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If BC1.2 isn't supported, don't waste space + time checking for inputs
that don't exist.
BUG=chromium:759880
BRANCH=None
TEST=`make buildall -j`
Change-Id: I47e81451abd79a67a666d1859faf2610ee5c941a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/663838
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch raises the max power for a type-c adapter to 60W (20V @3A).
We can't go above the regular cable capacity (3A) until we add e-marked
cable detection.
BUG=none
BRANCH=none
TEST=Boot Proto3 on Zinger. Observe 60W (20V @3A) is selected.
Change-Id: I9670d710e363c7db1136a7ce7a7f8401b0ad8240
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679210
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Fizz has an over current control system. There are two FETs
connected to two registers: PR257 & PR258. They control
the max input current as follows:
PR257, PR258
For 4.62A (90W BJ adapter), on, off
For 3.33A (65W BJ adapter), off, on
For 3.00A (Type-C adapter), off, off
BJ adapters are distinguished by reading GPIO71.
This patch also removes ISL9238 driver and ramping code. The
charger chip has been removed from the board since proto2.
BUG=b:65013352
BRANCH=none
TEST=Boot Fizz Proto3 on BJ and Type-C.
Change-Id: I32c2467f4ab23adf3f9313a03914d74d64a722df
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/668119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch makes LED pulse using deferred call to save RAM and
CPU cycles.
This patch also adds led_alert API. It blinks LED as a warning.
BUG=b:37646390
BRANCH=none
TEST=Verify LED on in S0, pulse in S3, and off in S5.
Run 'led alert' command.
Change-Id: I8c61f91f095eed562d2ee9582868879241df626f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This is used for factory test with following command
1. ectool command
ectool led power query
ectool led power green=100
ectool led power red=100
ectool led power amber=100
ectool led power off
ectool led power auto
2. console command
led debug >> enter debug mode
led green
led red
led amber
led off
led debug >> exit debug mode
BUG=b:65651340
BRANCH=master
TEST=`ectool ...` works good
Change-Id: Icb87e479075d90f509d60121a3e1df0afe66d41f
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/666418
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This change makes the power LEDs pulse using PWM.
S0: solid green.
S3: pulsing amber (= mix of green and red)
S5: off
BUG=b:64975836
BRANCH=none
TEST=Verify LED behavior described above on Proto3
Change-Id: I696cf8279dd762236b7b7f000a316820d58916bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669773
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:37646390
BRANCH=none
TEST=Verify green LED blink in S3 on Fizz proto3.
Change-Id: I055a271e2bb8fd8454d9940c90d5f71cc9025e50
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669772
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Proto2 board has the line ADP_IN, which is raised to 2.5 V when a BJ
adapter is plugged. This patch makes EC running on proto2 and above
use this line to detect the power source at boot (as opposed to proto1
guessing a BJ adapter is plugged if PPVAR_BOOSTIN_SENSE is 19v).
BUG=b:37573548
BRANCH=none
TEST=Boot proto3 Fizz on BJ and Type-C.
Change-Id: I4052a73729d62694ce154bfb33255974dc110841
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/626879
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This patch gives the highest priority to dedicated chargers. It
means if a dedicated power supply is being connected, other power
supplies such as USB-C adapters will not be recognized as a new
charger.
BUG=b:65059574
BRANCH=none
TEST=Boot Fizz on BJ adapter. Verify plugging in Type-C adapter
doesn't shut down the system.
Change-Id: Ie49b128ae64f917a227f9081148565a3f5356212
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655638
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch makes EC refuse PR swap when the system is powered
through the USB-C port because switching from SNK to SRC will
cause the system to shut down.
BUG=b:65481832
BRANCH=none
TEST=Boot Fizz on USB-C and BJ.
Change-Id: I52c5813adc1ea9b4e69e65599c1794ae43192a1e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655643
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Reworked suzy-q and suzy-qable all provide Rp, so there is no need for
special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS
is no longer relevant, since we no longer take special action when VBUS
is seen without Rp.
BUG=chromium:737755
BRANCH=None
TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5.
Also, verify zinger works in S5 on reef.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec
Reviewed-on: https://chromium-review.googlesource.com/656067
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy.
This change makes EC treat it also as a RW copy.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also
adds the macro to config.h.
BUG=none
BRANCH=none
TEST=make buidlall
Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/639955
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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the ps8xxx family of TCPCs (ps8751, ps8805) have historically used the
generic tcpci_tcpm_drv functions, but we need to override some of
these entry points because the parade parts need to be woken up before
accessing registers.
in most cases, this doesn't matter because we access the chip in quick
succession where we can "safely" assume the chip is awake -- and the
code is structured to implicitly keep the chip awake. the new case we
need to address here is where we need to suspend the pd_task and TCPC
at an arbitrary point in time. the driver's .release method is called
to shut down the chip, and that involves first waking up the chip to
be able to access its regs to mask off interrupts, etc.
BUG=b:35586896
BRANCH=none
TEST=tested from depthcharge - we no longer get errors in the EC
console logs about TCPC "release" failed.
Change-Id: Ic2a90b71050b3f68c697b1cef48d736ed88b3f41
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616460
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch disables PECI so that GPIO81 can be used for PROCHOT.
BUG=b:62092359
BRANCH=NONE
TEST=Boot i7 and Celeron Fizz.
Change-Id: I57f7ece6aa23f1f84a05d2570d71a44e43e7e1ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/526035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We can re-use our pd_log FIFO for other purposes, such as TPM logging.
Carve out event_log, a generic logging module which pd_log is compatible
with.
BUG=b:63760920
TEST=On kevin, verify PD logging is still functional and entries are
seen in dmesg.
BRANCH=None
Change-Id: I8e6ad6f93e9eebc676aca64652c60f81da471a94
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/597314
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Board rev0 will lose VBAT on power cycle and therefore
cannot successfully save the reset flag state.
Implement workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:63889675
BRANCH=None
TEST=None
Change-Id: Ie79053e2e52a3a9efd9cd864808af7214989602e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579666
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch gives EC the capability of verifying and jumping to
RW_A or RW_B. EC tries the slot stored in a persistent storage
(e.g. BBRAM). If verification fails due to invalid contents, EC
tries the other slot. AP's expectation and its reaction to the
state of the slots and the currently running image are summarized
below.
Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC
won't try to verify or jump to RW yet.
| AP expects X
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X' | reboot to B
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X' | reboot to A
----------+---------------------------
SLOT_A=X' | write X to B, reboot to B
SLOT_B=X' | write X to A, reboot to A
BUG=b:38462249
BRANCH=none
TEST=Lock the system and boot Fizz on barrel-jack and type-c.
Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/556286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch allows a board to include another RW image in ec.bin.
The size of each copy is a quarter of the flash size on Fizz.
BUG=b:38462249
BRANCH=none
CQ-DEPEND=CL:568297
TEST=Run sysjump RW/A/B. Verify there is no size change by running
make savesizes/newsizes. Run objdump -h build/fizz/ec.obj:
Idx Name Size VMA LMA File off Algn
0 .image.RO 0001700c 10088000 10088000 00008000 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .image.RO.key 00000340 1009f00c 100a7c40 0001f00c 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .image.RW 00016ddc 1009f34c 100c8000 0001f34c 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .image.RW.sign 000001b8 100b6128 100e7c00 00036128 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
4 .image.RW_B 00016ddc 100b62e0 100e8000 000362e0 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
5 .image.RW_B.sign 000001b8 100cd0bc 10107c00 0004d0bc 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
6 .padding 00000001 100cd274 10107fff 0004d274 2**0
CONTENTS, ALLOC, LOAD, DATA
7 .ARM.attributes 00000014 00000000 00000000 0004d275 2**0
CONTENTS, READONLY
Change-Id: Iaa687c1d7d704fec4cccfa127376c8db102267fa
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/557305
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This commit adds support for the PS8805, another Parade Tech TCPC with
integrated superspeed muxes. This also creates a generic Parade Tech
TCPC driver which supports the PS8xxx series.
The current supported TCPCs are:
- PS8751
- PS8805
BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I78383af414996e0e8d6220985d286f95267136f8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564799
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch enables vboot ec for Fizz.
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz
Change-Id: Ie20f7bab92e45849171a2db545459b40fe7b1c88
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517274
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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On a keyboard-less, volume-button-less board, we support simplified
sysrq handling.
For Fizz, we use the recovery button to trigger sysrq event and
holding it down to trigger warm reset.
BUG=b:38418116,b:38417391
BRANCH=none
TEST=On Fizz, try
1. Press recovery button and release -> sysrq sent
2. Press and hold recovery button -> warm reset
3. Press recovery button and power button -> enter recovery mode
Change-Id: If8760319dba3df4545e9805b396ac89c241dae80
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/537817
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:37316498
BRANCH=none
TEST=Boot Fizz
Change-Id: Iaceb64bcf5d54145c26e86ce62a14d5732a22e78
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517406
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch adds wait between DSW_PWROK and PWRBTN assert. It is
required to be 95 msec or longer for Kaby Lake and Sky Lake.
Refer to the timing diagram for G3 to S0 on Sky Lake or Kaby Lake
platform design guide for details.
BUG=b:62584658
BRANCH=none
TEST=On Fizz, measured time between DSW_PWROK high and PWRBTN assert
for 1:AC plug-in, 2:recovery+power press, 3: reboot ec command.
Change-Id: I89a14ac9a49e20a332bd662d90be62f8ea23b003
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/534901
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BUG=b:62076222
BRANCH=None
TEST=make -j buildall
Change-Id: Id1482cc959233b41b0d917e8650866651d9a61fe
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/530137
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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The system power monitor function, aka. PSYS, of the ISL9238 chip
is disabled by default, this patch enables PSYS monitor in the
EC driver.
BUG=b:62041842
BRANCH=none
TEST=Able to read non-zero value at the MSR of
MSR_PLATFORM_ENERGY_STATUS (0x64D) by iotools;
Also, kernel powercap driver probes PSYS domain correctly;
Such that the kernel exports the sysfs node of intel-rapl:1
Change-Id: I7a533032815e873ae74dca42ec07041be0d0f975
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/520549
Tested-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This patch sets GPIO_LAN_PWR_EN to output/high to power on
the ethernet port at start.
BUG=b:37646105
BRANCH=none
TEST=Measured V3P3A_LAN is 3.3V.
Change-Id: I9629a72d1ffefd1ca2aeb8d2d1f5d74a953d7e58
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514622
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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Fizz needs to set available power on type-c/pd before PD task starts.
PD task tries to reset available power at start-up. This patch prevents
those reset attempts from disabling already initialized power sources.
BUG=b:37316498
BRANCH=none
TEST=Boot Fizz on barrel jack and type-c adapters
Change-Id: I807f9d5ae4b4530fa80479b4e1a669569be841c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513582
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This change adds CONFIG_POWER_BUTTON_INIT_IDLE. When it's set,
the system starts with the power button state idle. It means
when the board boots from power-off, it stays at G3.
BUG=b:37536389
BRANCH=none
TEST=Power on Fizz. Verify it stays at G3. Verify it boots
by pressing power button.
Change-Id: I09a62a69d9f201b2dc261838cc9b4425fe3a8dc1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486945
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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