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* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-192-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cleanup: refactor CPRINTF("[%T ...]\n") to CPRINTSJack Rosenthal2019-07-171-1/+1
| | | | | | | | | | | | | | | | Looking at where the non-standard %T printf modifier is used in EC codebase, the majority is cases where CPRINTS could have been used instead of CPRINTF. This is a somewhat-mechanical refactor of these cases, which will make implementing a standard printf easier. BUG=chromium:984041 BRANCH=none TEST=buildall Change-Id: I75ea0be261bfbfa50fb850a0a37fe2ca6ab67cb9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703128 Reviewed-by: Evan Green <evgreen@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-132-26/+0
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-04-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-14/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Apply VR1 fix for all variantsDaisuke Nojiri2019-03-301-10/+8
| | | | | | | | | | | | | | | | | | | CL:1529983 was applied to only Teemo. This patch applies the same fix to the rest. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/128960577 BRANCH=firmware-fizz-10139.B TEST=make buildall -j Change-Id: I675327aa5682ab94ce6d41d82d006f3cdf749e54 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1535173 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1544251 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Teemo PMIC TPS650830 VR1 setting for hang up issueSue Chen2019-03-301-0/+11
| | | | | | | | | | | | | | | | | | | | | Set PMIC register V100ACNT (0x37) to 0x1B [1:0] : 11b Forced PWM Operation. [5:4] : 01b Output Voltage Selet Vnom (1V) To improve +V1P00A ripple around 18mV. BUG=b:128960577 BRANCH=firmware-fizz-10139.B TEST=make buildall -j Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I1e620a6c2eebcf2dec8c66989f1469072621ba92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1529983 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 4d510cbb5c27314b11bb92c4e9af361501605ad7) Reviewed-on: https://chromium-review.googlesource.com/1529982 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Set initial fan speed to 50%Daisuke Nojiri2018-11-191-0/+2
| | | | | | | | | | | | | | | | | This patch sets initial fan speed to 50% to reduce fan noise at start-up and resume. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:118701592 BRANCH=none TEST=Verify fan starts spinning on Fizz at 50% speed. Change-Id: I230eb2b6c33499f96d0583b5d75f2674960a35ff Reviewed-on: https://chromium-review.googlesource.com/1309036 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Add Jax supportDaisuke Nojiri2018-11-192-19/+26
| | | | | | | | | | | | | | | | | | | If OEM_ID is equal to 8 (Jax), the EC works as follows: - Set barrel jack adapter spec to (19V, 3.42A). - Set fan_count to zero Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:116588924 BRANCH=none TEST=Boot Fizz with OEM=8. Change-Id: Id6489b65a0bb71cd56d4fcf5e2fdbacb630aa99a Reviewed-on: https://chromium-review.googlesource.com/1308258 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb-c: use higher priority task for interruptsJett Rink2018-11-141-7/+1
| | | | | | | | | | | | | | | | | This should be the last step to make all boards on ToT follow go/usb-pd-slow-response-time. Theses boards all have the higher priority tasks, but they aren't being used since the tcpc interrupt wasn't scheduling calls on it. BRANCH=none BUG=b:112088135 TEST=builds Change-Id: I2c39e661e804f88edd5b34636b93e6e63a5af57f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1283452 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Fizz: Remove remote temp sensor 2Daisuke Nojiri2018-09-202-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fizz has been shipped with TMP431, which has only one remote sensor. This patch removes the one which doesn't exist on the boards. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:880705 BRANCH=none TEST=Verify local and remote sensor report expected temperatures. Verify the fan spins as expected. > temps TMP431_Internal : 304 K = 31 C 37% TMP431_Sensor_1 : 301 K = 28 C $ ectool temps all 0: 304 K 1: 301 K Change-Id: I2346444f1331faaf32b407a18ba96302b7a166e6 Reviewed-on: https://chromium-review.googlesource.com/1234735 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit d8de510aa7bdfb7c43621c7d48b7ca3ab372e3c7) Reviewed-on: https://chromium-review.googlesource.com/1234746 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chgmgr: Allow charge_manager_update_charge to accept NULLDaisuke Nojiri2018-09-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, charge_manager_update_charge does not handle NULL pointer for struct charge_port_info any differently. It's not sanity-checked either (thus memory access violation can occur). This patch will make charge_manager_update_charge accept NULL pointer and set available current and voltage to zero. This also helps callers' intentions be clear because callers can explicitly specify NULL (instead of passing a pointer to chg = {0}, which is initialized somewhere else). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I518662ab6a3a07f93da5d34cf62a6f856884f67d Reviewed-on: https://chromium-review.googlesource.com/1226125 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-1/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* usb-c: add high priority tasks for interruptsJett Rink2018-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To all boards that have space, add the PD tasks that handle interrupts in parallel. This is the last change for go/usb-pd-slow-response-time. BRANCH=none BUG=b:112088135 TEST=buildall. This works on grunt and octopus. This CL is more of a clean up for ToT to ensure that newly copied boards use the correct paradigm. Below is the space taken up by this change: build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584) build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160) build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516) build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800) build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768) build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164) build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860) build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064) build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440) build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444) build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532) build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416) build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392) build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912) build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184) build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680) build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204) build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740) build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992) build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088) build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656) build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248) build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540) build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960) build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288) build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988) build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084) build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512) build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836) build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300) build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340) build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800) build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464) build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772) build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308) build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580) build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540) build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264) Compared 208 of 208 files. 38 files changed. Total size change: -27484 bytes. Average size change: -723 bytes. Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1220667 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* ss-mux: update semantics for TCPC/MUX only used as MUXJett Rink2018-09-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | This converts the compile time option of CONFIG_USB_PD_TCPM_TCPCI_MUX_ONLY into a runtime option to better support draggon egg designs and reduce CONFIG complexity in general. Introduce new mux_read/write to read from tcpc_config_t or mux driver depending on new flag setting. Audited all mux drivers for any use of tcpc_read/write and updated to mux_read/write. BRANCH=none BUG=b:110937880 TEST=On Bip with CL stack: Verified by connecting DP monitor at boot; Verified plug / unplug of DP cable works; Change-Id: I968893b886ff0ccc4074beae5ec42973814ae77c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200062 Commit-Ready: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-273-5/+5
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Add Wukong for BJ configurationDaisuke Nojiri2018-06-142-5/+9
| | | | | | | | | | | | | | | | | | Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:71524814 BRANCH=none TEST=None Change-Id: I70deadb6f8c01c36d13f186e95244dc7a317fcbb Reviewed-on: https://chromium-review.googlesource.com/1090326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 77997e8422b1ef5d511019a8a1e38fa743eab082) Reviewed-on: https://chromium-review.googlesource.com/1098716 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Add Bleemo for BJ configurationDaisuke Nojiri2018-06-131-0/+1
| | | | | | | | | | | | | | | | | | | Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:80482240 BRANCH=none TEST=None Change-Id: I50187f58346fe4e6fa88d6a1e07e1dcf72214f07 Reviewed-on: https://chromium-review.googlesource.com/1089329 Reviewed-by: Daniel Johansson <dajo@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Daniel Johansson <dajo@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit eb92965cce47fe0acd95440a6cefaf07666bf98d) Reviewed-on: https://chromium-review.googlesource.com/1093458 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Add fan table for BleemoDaisuke Nojiri2018-06-122-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:80482240 BRANCH=none TEST=Verify fan speed follow temperature change on Teemo. Change-Id: Ie8ae7febc1a1c1753a4ce26b6c8ff119e277852b Reviewed-on: https://chromium-review.googlesource.com/1083934 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 72dad0df6815d476360e085104af61bdd9dec449) Reviewed-on: https://chromium-review.googlesource.com/1098176 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Move BJ adapter spec table to ECDaisuke Nojiri2018-06-082-43/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the BIOS carries the table which maps (OEM,SKU) to barrel jack adapter spec. This patch moves this table to the EC. Then, the EC will independently manage the max voltage and current for BJ. This would remove the dependency on AP-EC communication, thus improves the stability This patch also corrects the mapping between SKUs and BJ wattages. SKU BJ(W) * KBL-R i7 8550U 4 90 * KBL-R i5 8250U 5 90 * KBL-R i3 8130U 6 90 * KBL-U i7 7600 3 65 * KBL-U i5 7500 2 65 * KBL-U i3 7100 1 65 * KBL-U Celeron 3965 7 65 * KBL-U Celeron 3865 0 65 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:109762580 CQ-DEPEND=CL:1089370 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I70c8987670e7495a32fdcbc572779fdc9362e22f Reviewed-on: https://chromium-review.googlesource.com/1089328 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 270e3240fab531d15cddc7c50202e5820e90bb53) Reviewed-on: https://chromium-review.googlesource.com/1091975 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Add fan for WukongRyan.Zhang2018-06-072-34/+82
| | | | | | | | | | | | | | | | | | | | This patch also makes EC print board version, OEM ID, SKU ID on console. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:70294260 BRANCH=none TEST=Verify fan speed follows temperature changes on Teemo. Verify CBI is read correctly on start-up. Change-Id: I45a767adbb437005b0f18ff34b4e9d6b0450a0e0 Reviewed-on: https://chromium-review.googlesource.com/1083933 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089036 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: add CONFIG_BOARD_HAS_RTC_RESETRyan Zhang2018-06-072-0/+9
| | | | | | | | | | | | | | | | | | | | | This patch resets the RTC of the SoC when the system doesn't leave S5. If it fails 5 times, the system will go back to and stay in G3. BUG=b:79323716 BRANCH=fizz TEST=Boot Fizz differently: 1. AC plug-in 2. Power button press 3. reboot EC command 4. servo reset button 5. Recovery mode Change-Id: I728c99c342fb888600599acbe25f72a478ccf948 Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020583 Reviewed-on: https://chromium-review.googlesource.com/1089035 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* Fizz: Increase VR3 voltage to avoid boot failureDaisuke Nojiri2018-05-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | When V3P3A_EC is higher than V3P3A_DSW + 0.07V, system 3.3V rail is powered by V3P3A_EC. V3P3A_EC LDO will shut down when PU27 triggers OTP. This patch increases VR3 voltage by 3%, which gives us 3.399. This is more than the maximum voltage PU27 can provide, thus, V3P3A_DSW will win the voltage race (against V3P3A_EC). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:80114849 BRANCH=Fizz TEST=Boot Fizz Change-Id: Ieb6fbc4ad056a79dc1eef5eae7a91385575bac0b Reviewed-on: https://chromium-review.googlesource.com/1069594 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit d674a0e3cb15ee7f542c16f5930f0ef4a5f000ea) Reviewed-on: https://chromium-review.googlesource.com/1076707 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* fizz: Enable optimized SHA256/RSA in RO onlyNicolas Boichat2018-05-291-0/+6
| | | | | | | | | | | | | | | | Decreases verification time from 923ms to 785ms. Optimized version do not really help in RW, as they just increase the image size (which also increases verification time). BRANCH=fizz BUG=b:77608104 TEST=make BOARD=fizz -j, flash fizz, check timing. Change-Id: Ia8c36c35c0321c1995dc1cede7b27f7636037795 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1075908 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-233-5/+8
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: CEC: Event-handling for incoming messagesStefan Adolfsson2018-05-111-1/+2
| | | | | | | | | | | | | | | | | | | | | When an incoming message is complete, store it in a internal circular buffer and notify the AP so the message can be read out. Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:76467407 BRANCH=none TEST=Write different type of messages from one EC to another EC using ectool. Also use ectool on the second EC to verify that they are received correctly. CQ-DEPEND=CL:1030226 Change-Id: Ie4370b0c954befe81a055cd5dff7d7f13dbefbd0 Reviewed-on: https://chromium-review.googlesource.com/1030227 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: CEC: Add stub implementation of CECStefan Adolfsson2018-05-111-0/+1
| | | | | | | | | | | | | | | | | | | Add CEC stub implementation and enable it for Fizz. All it does is print a message when the driver is initialized. Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:76467407 BRANCH=none TEST=Check that "CEC initialized" is printed on the console when the EC boots. CQ-DEPEND=CL:1030219 Change-Id: I1cf674e664e091354e344e0c08a69bd09f415904 Reviewed-on: https://chromium-review.googlesource.com/1030220 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Add GPIOs used for CECStefan Adolfsson2018-05-102-0/+7
| | | | | | | | | | | | | | | | | | | The Fizz hardware has three pins for CEC. One GPIO is used as a pull-up. It is always an output and always high. The second GPIO is a data output. The third GPIO is the data input that can also be configured as a timer input (TA1). Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:76467407 BRANCH=none TEST=Read and write the newly added GPIOs using ectool Change-Id: Ia33b36a0cdaa40fd1a4f7aa66a092b5833bf5cf8 Reviewed-on: https://chromium-review.googlesource.com/1030219 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* fizz/nami: Use chipset_pre_init_callbackFurquan Shaikh2018-04-192-2/+2
| | | | | | | | | | | | | | | | This change updates fizz/nami boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=make -j buildall Change-Id: Ib09c033c2f0c2c3d324c90776f7bbd8365a71f52 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018735 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-3/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chgstv2: Check charger power in prevent_power_on.Aseda Aboagye2018-04-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | charge_prevent_power_on() had sections which were gated on the following CONFIG_* option: CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT However, the block of code that this gated didn't even take the battery percentage into account and made it very confusing as to why. This commit simply changes the CONFIG_* option used to gate to be the following: CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON This better reflects the checks that were actually being made. Additionally, this CONFIG_* option is defined by default for boards that have a chipset task and is initialized to 15W, which is the power that indicates that the charger is likely to speak USB PD. BUG=b:76174140 BRANCH=None TEST=make -j buildall Change-Id: Ic9158dd7109ce6082c6d00157ff266842363b295 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/977431 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Log DP mode entry and exitDaisuke Nojiri2018-03-201-0/+4
| | | | | | | | | | | | | | | This helps us tell whether a monitor lost picture because the EC exited the DisplayPort mode or other reason. BUG=b:75288273 BRANCH=none TEST=boot Fizz Change-Id: I2da6a27c66f03ef780a0ed6f60a597a01f248942 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/966993 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* fan: Allow board to configure fans at run timeDaisuke Nojiri2018-03-061-11/+16
| | | | | | | | | | | | | | | This patch splits struct fan_t into two parts: base configuration and RPM configuration. RPMs are expected to be different from model to model while a base configuration is most likely shared. BUG=b:73720175 BRANCH=none TEST=make buildall Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host_command: Count suppressed host commands individuallyDaisuke Nojiri2018-02-162-8/+2
| | | | | | | | | | | BUG=chromium:803955 BRANCH=none TEST=Verify counters are printed every hour and before sysjump as follows: [12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0] Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912150
* CBI: Make data offset and size variableDaisuke Nojiri2018-02-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CBI data offset and size are fixed. This patch makes them variable. Each data item consists of <tag><size><value> where <tag> is a numeric value assigned to each data item, <size> is the number of bytes used for <value>. BUG=b:70294260 BRANCH=none TEST=Use 'ectool cbi set' to set board version, oem, sku. Verify the contents by cbi console command and ectool cbi get. 1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2) 2. ectool cbi set 1 1 1 (write oem id of size 1) 3. ectool cbi set 2 2 1 (write sku id of size 1) 4. ectool cbi get 0 514 (0x202) 5. ectool cbi get 1 1 (0x1) 6. ectool cbi get 2 2 (0x2) 7. Run cbi console command: CBI_VERSION: 0x0000 TOTAL_SIZE: 18 BOARD_VERSION: 514 (0x202) OEM_ID: 1 (0x1) SKU_ID: 2 (0x2) 43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02 01 02 Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/920905 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fizz/CBI: Buid cbi-util as host-utilDaisuke Nojiri2018-02-161-27/+0
| | | | | | | | | | | | | | | This patch also removes make rules to stop producing CBI blobs. CBI blobs will be produced by another protage package. BUG=b:73123025,chromium:809250 BRANCH=none TEST=emerge-fizz chromeos-firmware-fizz and verify /build/fizz/firmware/cbi contains EEPROM images. Verify emerge ec-utils ec-devutils succeeds. Change-Id: I13744b0ab97675afa0247046bffa3edac3e62ceb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/909692
* Fizz: Update thermal table by projectRyan Zhang2018-02-081-14/+44
| | | | | | | | | | | | | | | | | | | | | | | | | 1. Prochot/Shutdown Point a. Prochot on: >=81C, off: <=77C b. Shutodwn: >=82C 2. custom fan table There are three projects sharing two tables, and use Kench & Teemo's table before getting correct OEM ID because it raises fan speed quicker than the other one. a. Kench & Teemo & default b. Sion BUG=b:70294260 BRANCH=master TEST=EC can get two fan tables with different cbi value. Change-Id: Ie1bffbcf5c353a9aae5806f6c2b41554eed22b7d Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/886121 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Monitor input current (version 2.0)Daisuke Nojiri2018-02-083-82/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fizz has three FETs connected to three registers: PR257, PR258, PR7824. These control the thresholds of the current monitoring system. PR257 PR7824 PR258 For BJ (65W or 90W) off off off For 4.35A (87W) on off off For 3.25A (65W) off off on For 3.00A (60W) off on off The system power consumption is capped by PR259, which is stuffed differently depending on the SKU (65W v.s. 90W or U42 v.s. U22). So, we only need to monitor type-c adapters. For example: a 90W system powered by 65W type-c charger b 65W system powered by 60W type-c charger c 65W system powered by 87W type-c charger In a case such as (c), we actually do not need to monitor the current because the max is capped by PR259. AP is expected to read type-c adapter wattage from EC and control power consumption to avoid over-current or system browns out. The current monitoring system doesn't support less than 3A (e.g. 2.25A, 2.00A). These currents most likely won't be enough to power the system. However, if they're needed, EC can monitor PMON_PSYS and trigger H_PROCHOT by itself. BUG=b:72883633,b:64442692,b:72710630 BRANCH=none TEST=Boot Fizz on 60W/87W/BJ charger. Verify GPIOs are set as expected. Change-Id: Ic4c0e599f94b24b5e6c02bbf1998b0b89ecad7bf Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/900491 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fizz: Uprev board version to 2.2Daisuke Nojiri2018-02-081-1/+1
| | | | | | | | | | | | | | This patch sets the board version for CBI blob to 2.2. BUG=none BRANCH=none TEST=Boot Fizz. Change-Id: Ibbb4083b82af3803d06bbdd157b16b369f7f6784 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/905403 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz/CBI: Create CBI blobsDaisuke Nojiri2018-02-061-0/+27
| | | | | | | | | | | | | This patch makes make create EEPROM blobs which contain Cros Board Info. BUG=b:72949522 BRANCH=none TEST=make buildall. make BOARD=fizz cbi_kench. Change-Id: Ie4c50f4707285b44c13afc7410a5ea823a26d98e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/902822 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Enable PD communication in RO for external displayDaisuke Nojiri2018-02-032-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes EC enable PD communication if it's running in manual recovery mode. This is required to show recovery screen on a type-c monitor. This patch also makes EC-EFS ignore power availability. It will make EC verify & jump to RW even if power is sourced by a barrel jack adapter. This should allow depthcharge to show screens (e.g. broken, warning) on a type-c monitor. BUG=b:72387533 BRANCH=none TEST=On Fizz with type-c monitor, verify - Recovery screen is displayed in manual recovery mode. - Critical update screen is displayed in normal mode. - Warning screen is displayed in developer mode. Monitors tested: Dingdong, Dell S2718D Change-Id: Ib53e02d1e5c0f5b2d96d9a02fd33022f92e52b04 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/898346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz: Suppress EC_CMD_PD_GET_LOG_ENTR debug logDaisuke Nojiri2018-02-031-0/+1
| | | | | | | | | | | | | | | | Host command handler prints every single host command except when commands are repeated back-to-back. Some commands do not provide useful info when studying feedback reports or what is worse they may hide critical info by flooding the EC log. BUG=chromium:803955 BRANCH=none TEST=Observe 'HC 0x115' is not printed. Change-Id: I4901b27bbfedd54dc0d364b16c49d4ed0dea0fc4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/896694 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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