| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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This renames the MODULE_SPI_MASTER to MODULE_SPI_CONTROLLER.
BRANCH=none
BUG=b:181607131
TEST=make buildall passes;
"compare_build.sh -b all" shows no difference
Change-Id: I4d33f57fd82c5b57f111c12387113dc82cebe60b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932466
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Craig Hesling <hesling@chromium.org>
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marked as MODULE_ADC
In the ADC initialization function, we should use the function
of gpio_config_module to set alternate function and declare
corresponding alternate function pins in gpio.inc. So we are
able to enable extra flag if needed.
BUG=none
BRANCH=none
TEST=testing the alternate function pins are normal
on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb
and reef_it8320.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The development board of it83xx and it8xxx2 have common code
and config options which are moved to baseboard ite_evb.
And we create another board for PD EVB based on baseboard ite_evb.
BUG=none
BRANCH=none
TEST=on baseboard ite_evb:
1.test board it83xx_evb and it8xxx2_evb:
successfully Flash EC image and boot on chip it8320 and
it83202.
2.flashrom by ite_spi test:
$ sudo ./util/flash_ec --board=it8xxx2_evb --verbose
INFO: Using servo_v2.
INFO: Using ec image : /mnt/host/source/src/platform/ec/build/
it8xxx2_evb/ec.bin
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
INFO: Flashing chip ite_spi.
dut-control --port=9999 cold_reset:on
dut-control --port=9999 fw_up:on
dut-control --port=9999 cold_reset:off
dut-control --port=9999 fw_up:off
dut-control --port=9999 spi1_vref:pp1800 spi1_buf_en:on
dut-control --port=9999 spi1_buf_on_flex_en:on
INFO: Running flashrom:
sudo /usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012 --flash-size
flashrom v0.9.9 : : on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9 : : on Linux 4.15.0-76-generic (x86_64)
INFO: Programming EC firmware image.
INFO: Running flashrom:
/usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012 -w /tmp/flash_spi_6163
flashrom v0.9.9 : : on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9 : : on Linux 4.15.0-76-generic (x86_64)
Calibrating delay loop... OK.
Erasing and writing flash chip... Verifying flash... VERIFIED.
SUCCESS
INFO: Flashing done.
INFO: Restoring servo settings...
dut-control --port=9999 cold_reset:off
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
dut-control --port=9999 spi1_vref:off
dut-control --port=9999 spi1_buf_en:off
dut-control --port=9999 spi1_buf_on_flex_en:off
dut-control --port=9999 cold_reset:on
dut-control --port=9999 cold_reset:off
3.test board it8xxx2_pdevb:
successfully Flash EC image and boot on chip it83202.
Connection with adapter and dongle are able to ready state.
Change-Id: Ib6371b61c27980eb9977548177efb8c896e72d47
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2071551
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The current use of the PD Config Flags are a bit confusing and
has been changed to the following:
The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable
the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY
is enabled, one of the following must be enabled:
CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine
CONFIG_USB_PD_TCPMV2 - current power delivery state machine
BUG=b:149993808
BRANCH=none
TEST=make -j buildall
Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238
Signed-off-by: Sam Hurst <shurst@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519
Reviewed-by: Diana Z <dzigterman@chromium.org>
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The DAC module has four channels. We can
set output voltage when DAC channel is
enabled by this driver.
BUG=b:149094279
BRANCH=none
TEST=The console command #dac set as follows:
read: dac [ch]
write: dac [ch] [voltage]
[ch]:2-5, [voltage]:0(disable)-3300
Change-Id: I8e815cb5bc749467581d5f771fd6f9e0995fca3b
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2046685
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Add PD driver for chip it8xxx1/8xxx2 series.
BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
(set cc toggle by console cmd):
1.pin configuration
console cmd "gpioget" check gpio settings.
memory dump check cc pin alternate settings.
2.Tx data error handle
Message discard, No GoodCRC, Tx not enable, Timeout
errors happen, corresponding INT will be triggered
then do properly handle.
3.basic pd connection
SNK:connect with adaptor, request max power (15V,3A),
state SNK_READY.
SRC:enable DRP role,
connect with dongle, provide power (5V,1.5A),
source Vconn 5v, get ack of cable discover id,
state SRC_READY.
4.pd module disable
SNK:connect with adapter.
console cmd "hibernate sec", driver disable pd module,
check still connection with adapter via dead battery rd.
And when resume from hibernate, pd init can re-enable
pd module, re-connect with adapter.
SRC:connect with dongle.
console cmd "hibernate sec", driver disable pd module,
check cc pin (not Vconn source pin) volt power down
to ~0v. And when resume from hibernate, pd init can
re-enable pd module, re-connect with dongle.
5.Tx hard reset
console cmd "pd port hard", check hard reset message by
lecroy analyzer.
6.Tx cable reset
check cable reset message by lecroy analyzer.
7.SOP' enable
SRC:connects to SNK via E-mark cable.
Source Vconn successfully, and receives cable's ack
of discover id request.
Not source Vconn to cable, and receives nothing
of discover id request (this isn't effect on
request SNK flow).
8.power role swap
console cmd "pd port swap power", check pd protocol
by lecroy.
Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This was changed in PD 2.0 years ago (via ECN authored by our own David
Schneider), but our codebase still refers to BIT 27 of the Fixed PDO as
"Externally powered" instead of "Unconstrained Power".
This will search and replace all instances of "Externally powered" when it
refers to BIT 27, as well as function names, other internal representations
of that property, strings, and comments.
seds:
s/PD_FLAGS_PARTNER_EXTPOWER/PD_FLAGS_PARTNER_UNCONSTR/g
s/partner_extpower/partner_unconstrained/g
s/externally powered/unconstrained/g
Some others too.
Signed-off-by: Benson Leung <bleung@chromium.org>
BUG=chromium:1030990
TEST=Codebase builds clean. No functional change, except for the property shows
up in ectool as "Unconstrained power" now.
Change-Id: I5ececa03f29eb31057be3d0ad5311117093bc6da
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956147
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Benson Leung <bleung@google.com>
Tested-by: Benson Leung <bleung@google.com>
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There is a board specific usb_pd_policy.c file that contains a lot of
code for handling DisplayPort Alternate mode, Google Firmware Update
Alternate mode, as well as some PD policy functions such as deciding to
Accept or Reject a data role swap or a power role swap. Several boards
simply copy/paste this code from project to project as a lot of this
functionality is not actually board specific.
This commit tries to refactor this by pulling the functions that are not
mainly board specific into common code. The functions are made
overridable such that boards that truly do require a different
implementation may do so.
Additionally, this consolidation changes the policy behaviour for some
boards, but they should be for the better. Some examples include that
data swaps are always allowed if we are a UFP (no system image
requirement), power swaps are allowed to become a sink if we are no
longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is
not entered if the AP is off.
In order to facilitate this refactor, a couple CONFIG_* options were
introduced:
- CONFIG_USB_PD_DP_HPD_GPIO
/* HPD is sent to the GPU from the EC via a GPIO */
- CONFIG_USB_PD_CUSTOM_VDO
/*
* Define this if a board needs custom SNK and/or SRC PDOs.
*
* The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating
* Dual-Role power, USB Communication Capable, and Dual-Role data.
*
* The default SNK PDOs are:
* - Fixed 5V/500mA with the same PDO_FIXED_FLAGS
* - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV,
* operational current PD_MAX_CURRENT_MA,
* - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power
* PD_OPERATING_POWER_MW
*/
BUG=chromium:1021724,b:141458448
BRANCH=<as many as we can that are still supported>
TEST=`make -j buildall`
TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety
of DP peripherals
TEST=Repeat above with a nocturne
TEST=Repeat above with an atlas
Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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The module ID in alternate function setting for spi
master should be corrected as MODULE_SPI_MASTER.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133
Reviewed-by: Jett Rink <jettrink@chromium.org>
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It was pointed out to me that the fans config list was non-const, but
there is only 2 boards that require non-const configuration, so
by default make it const, but allow an override.
BRANCH=none
BUG=None
TEST=EC compiles, make tests, buildall
Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Tested-by: Andrew McRae <amcrae@chromium.org>
Commit-Queue: Andrew McRae <amcrae@chromium.org>
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Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because
that is the configuration option used to enable to use of the the GPIO
signal name thus defined. Remove the now unused
CONFIG_HOSTCMD_PLTRST_IS_VWIRE option.
BUG=b:139553375,b:143288478
TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite
BRANCH=none
Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Added GPIOs pin config to support VCONN on tglrvp. Also added
power switch function to enable/disable VCONN according to the
cc lines.
BRANCH=None
BUG=b:139763031
TEST=Able to get characteristics of an E-marked cable
Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591
Reviewed-by: Keith Short <keithshort@chromium.org>
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Enable TCPC receive SOP' for communication with cable, when
we are Vconn source role.
BUG=None
BRANCH=None
TEST=test on board: ampton and reef_it8320
1.SRC connects to SNK via E-mark cable, sources Vconn successfully,
and receives cable's ack of discover id request.
2.SRC connects to SNK via E-mark cable, but not source Vconn to
cable, and receives nothing of discover id request
(this isn't effect on request SNK flow).
3.console cmd pdcable 0
2019-07-30 11:43:40 > pdcable 0
2019-07-30 11:43:45 Cable Type: Passive
2019-07-30 11:43:45 Connector Type: Type C
2019-07-30 11:43:45 Cable Current: 5A
2019-07-30 11:43:45 USB Superspeed Signaling support: Gen 1
Change-Id: Icd2e6f8481bb7a4e0b922460d46b831f36112738
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1728669
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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We still need to pull out more common code between the two stacks, but
this is scaffolding with a few examples.
BRANCH=none
BUG=b:137493121
TEST=unit tests pass
Change-Id: Ibd9dda1e544e06f02aa3dde48ca7de1539700cfa
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1744655
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The Platform Environment Control Interface (PECI) is a thermal management
standard with one-wire bus interface that provides a communication channel
between Intel processor and chipset components to external monitoring or
control devices.
As we can read the CPU temperature over PECI more accurately than the
thermistors, we can eliminate usage of thermistors for reading CPU
temperature.
BUG=b:128666114
BRANCH=none
TEST=Manually tested on Dragonegg, able read CPU temperature.
Change-Id: Ie0845ca776e6a7e14511dc9315d6d83cdd5f09a6
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1622740
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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It's simply a bad idea to describe a macro in multiple locations.
It'll make it hard to change. It'll be difficult to keep all
locations in sync.
This patch replaces the comment duplicated in all ec.tasklist with
a pointer to the CONFIG_TASK_LIST definition. The macro will be
described in a single place (just like all/most other macros).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313
Reviewed-on: https://chromium-review.googlesource.com/1551579
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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In it83xx chip, the file of spi.c is renamed
to spi_master.c, and the related config is
renamed too.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia696e62afa2ff06da68a3e4af685615b1dbcc8e9
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1372870
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This adds support to configure dualrole setting
per port, so that servo v4 can adjust charge and
dut port separately.
servo will detect charge capability on CHG port
and choose source or sink as appropriate.
Fix null dereference bug in genvif duel to dynamic src_pdo.
"cc" command allows src, snk, srcdts, snkdts configurations.
BRANCH=None
BUG=b:72557427
TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub.
TEST=make buildall -j
Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096654
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to
CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this
config option indicates that chipset sleep signals (SLP_S3 and SLP_S4)
are tranmitted over virtual wires instead of physical lines with eSPI.
BUG=b:111859300
BRANCH=None
TEST=make -j buildall
Change-Id: Iab4423abc9102164d4f43296a279c24355445341
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1151048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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With this patch, we can use them in code.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1116632
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Not all boards using ITE83XX use mouse LDN. This change adds a config
option to allow boards to explicity enable this device. Currently,
this device is enabled only for glkrvp_ite and it83xx_evb. It is
disabled for reef_ite and bip.
Change-Id: I7149fd0cb35cc9f49f2b7b80f6c2deefe2edda55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1070785
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com>
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Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The ITE eval board relied on the chip's define for LPC. Since the ITE
chip supports both LPC and eSPI, we want to define LPC here to be
explicit.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ic477277543c1f24999070dc408052c7266df22e6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067501
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Now that board version can come from CBI, we can have a real error
reading it. We should pass that error to the console or to the
AP on the host command and let the AP firmware (or user) decided how to
handle that error case
Also update the CONFIG_BOARD_VERSION to be derived instead of needed
in most cases.
BRANCH=none
BUG=b:77972120
TEST=Error reported on EC console and AP console when CBI is
invalid on yorp
Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1015776
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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With this change, we don't need to declare pnpcfg_settings[]
for each it83xx based board.
BUG=b:76022972
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1009544
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The pd_custom_vdm is called in common/usb_pd_protocol no
matter you have this defined or not. No where else I see
pd_vdm being used. So we should not have to deal with this
CONFIG_USB_PD_CUSTOM_VDM.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/998520
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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We let board-level code to enable them if needed.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I9369e33ee1821125cf8719a0c3526afaf294da80
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/985346
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This patch splits struct fan_t into two parts: base configuration
and RPM configuration. RPMs are expected to be different from
model to model while a base configuration is most likely shared.
BUG=b:73720175
BRANCH=none
TEST=make buildall
Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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IT8320 can support extra four ADC channels (ADC13-16).
BRANCH=none
BUG=none
TEST=Run console command 'adc' and check the results.
Change-Id: Ia9a259f54fa28d43dc0050c6e20885c0b3914f9c
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/808125
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add espi control module for it83xx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell.
2. console command "kbpress 1 4" to test keyboard data.
(board code for espi module test on CL:392587)
Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d
Reviewed-on: https://chromium-review.googlesource.com/394471
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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With this change, we can keep a PWM channel active during
low-power idle (EC deep doze).
BRANCH=none
BUG=none
TEST=The pwm channel is function normally in deep doze mode.
And tested pwm frequency setting are:
300, 250, 200, 150, 100, 50, and 10 (Hz)
Change-Id: Ie94cd96e819c869bdde6d7675d8f1a6cfc627f3b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/752702
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This enum can be included in common.
BUG=none
BRANCH=none
TEST=build boards: it83xx_evb and reef_it8320
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Id7014b7de170cb3324c45d43fbf04ebe48a69f5e
Reviewed-on: https://chromium-review.googlesource.com/505864
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Servo_v4 requires the ability to have a different default state per
port. In previous devices, the assumption was that each supported port
had the same default usb pd state and power role. This CL moves the
by the default power role which in turn is derived from
CONFIG_USB_PD_DUAL_ROLE. In addiiton to moving the location, it now
uses 'port' as argument so it can be port specific if required.
PD_DEFAULT_STATE was a board.h specific config, but in practice each
instance used to date was set to PD_STATE_SNK_DISCONNECTED if
CONFIG_USB_PD_DUAL_ROLE was defined and set to
PD_STATE_SRC_DISCONNECTED otherwise.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual run 'make -j buildall' to verify that all instances of
PD_DEFAULT_STATE were removed.
Change-Id: Iaf40718668732f525485ed7942ee7fc246d3f75d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431787
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The typical power consumption in sleep mode is 65uA.
IT83xx uses deep doze mode for low power idle task. The typical power
consumption in this state is 280uA (depends on EC tasks, it should be more)
and the wake up time is in microsecond. We are using deep doze mode for
low power idle task instead of sleep mode is because the wake up time
will be 6ms more.
While in system hibernate (EC sleep mode), EC won't wake up frequently so
we can keep the power consumption at 65uA.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=- hibernate 0 [1|999999]
- hibernate [1|5|10|600]
- hibernate then press power button.
- hibernate then lid open.
Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d
Reviewed-on: https://chromium-review.googlesource.com/383332
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Fix error: CC_USBPD undeclared
BRANCH=None
BUG=None
TEST=Do check by "make BOARD=it83xx_evb -j"
Change-Id: Idc2e8e608c767bcea1221204a0d66417e82ff216
Signed-off-by: ite01580 <yanis.wang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/371019
Commit-Ready: Yanis Wang <yanis.wang@ite.com.tw>
Tested-by: Yanis Wang <yanis.wang@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.
Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The change is made to combine EC & PD's board code.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=We can verify PD module on PD EVB and run this board code
on EC EVB as well.
Change-Id: I92f6ad41643b0536fd78d24026374265cfcf37ea
Reviewed-on: https://chromium-review.googlesource.com/342489
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Unified board name for IT83-series.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST="make BOARD=it83xx_evb -j" and "make buildall -j"
Change-Id: Ic96d0132fb31fcc8715d0dd810f8bd340035a640
Reviewed-on: https://chromium-review.googlesource.com/341843
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Shawn N <shawnn@chromium.org>
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