summaryrefslogtreecommitdiff
path: root/board/jslrvp_ite
Commit message (Collapse)AuthorAgeFilesLines
* genvif: Use VIF overrides by defaultAbe Levkoy2021-03-301-0/+3
| | | | | | | | | | | | | | Use board-specific override files when generating VIFs for boards. BUG=b:172276715 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I197365018ceb8197c22d631cebf4cbce1c0119f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785506 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* config: Fix inconsistent VBUS measurement configAbe Levkoy2021-01-221-0/+1
| | | | | | | | | | | | | | | | | | Remove CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT from boards that define CONFIG_USB_PD_VBUS_MEASURE_CHARGER. This change is a no-op, because charge_manager.c is the only place where CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT is checked, and it is only checked if CONFIG_USB_PD_VBUS_MEASURE_CHARGER is not defined. BUG=b:178102402 TEST=make buildall TEST=Build sizes before and after change are the same BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ia3caa57a8531a5cba549b64c9087c337996af9c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2642892 Reviewed-by: Diana Z <dzigterman@chromium.org>
* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp:Separate battery configuration into board specific filesAyushee Shah2020-11-253-0/+85
| | | | | | | | | | | | | | | | | | This CL adds the battery configuration from interlrvp baseboard to board specific file for Alderlake, Tigerlake and jasperlake platform so that same manufacturer battery but with different config params can be used on intended platforms. BUG=b:174129818 BRANCH=None TEST=Able to see correct battery configuration in "battery" EC command and can see the battery charging and discharging. Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: I639eb4466c49dbdc01d31feb4ace8844a6b1ac87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557763 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* intelrvp: update usb_pd files to indicate MECC version complianceName2020-10-131-0/+3
| | | | | | | | | | | | | | | | | Add new configuration for MECC-0.9 version and update JSL,TGL RVP boards to use this config option. Support for new version of MECC-1.0 will be required for ADL-RVP. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: Ic1118c460a7052ffd0141a45c9153dbdac421d1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435175 Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: Poornima Tom <poornima.tom@intel.com>
* intelrvp: Move board specific changes to respective board filesName2020-10-072-0/+46
| | | | | | | | | | | | | | | | | Move board specific GPIO definitions and TCPC configuration from baseboard to JSL/TGL boards to accommodate changes in MECC spec 0.9 vs 1.0. BRANCH=None BUG=b:169551130 TEST=make buildall -j Signed-off-by: pandeyan <anshuman.pandey@intel.com> Change-Id: I53a0545674f22e6cba05f777a4095909c231cfd2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435174 Commit-Queue: Poornima Tom <poornima.tom@intel.com> Tested-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Intelrvp: Enable TCPMv2Ayushee2020-08-272-4/+5
| | | | | | | | | | | | | | | | This patch enables support for TCPMv2 for Intelrvp BUG=b:142340399 BRANCH=none TEST=TCPMv2/PD3.0 works properly on tglrvp. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: If15fc23efbcd9716c322ad06bc78a8e16f957d8e Signed-off-by: ravindr1 <ravindra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2299841 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Charger: Add dynamic charger chip countDiana Z2020-07-111-2/+0
| | | | | | | | | | | | | | | | Different DB options may cause different numbers of charger chips to be present on the system. Remove constant count for charger chips, and instead always call into the overridable function to query the count. BRANCH=None BUG=b:155963446 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0e65b8af351ecabe6f7b823e0e56f1932cc280a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2277833 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* intelrvp: Increase the PD stack sizeVijay Hiremath2020-07-081-2/+2
| | | | | | | | | | | | | | | | JSLRVP & TGLRVP are on TCPMv1 and the PD task stack size is overflowing for these boards hence increased the PD stack size. BUG=none BRANCH=none TEST=USB, DP, TBT & USB4 are detected without stack overflow Change-Id: I85be645f12e07b47182dde428e90c73e7b441750 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2286194 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Madhusudanarao Amara <madhusudanarao.amara@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* jslrvp_ite: increase the chipset task stackSooraj Govindan2020-05-271-1/+1
| | | | | | | | | | | | | | | | | | Overflow happens when chipset_task calls CPRINTS("PD:S3->S0") in pd_chipset_resume(). Increase the stack size of CHIPSET task, to fix this. BUG=b:157452300 BRANCH=none TEST=no more overflow after increasing the stack on jslrvp Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I96cb2482a4951dbc6422ee4400b9469007922321 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2216092 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLakeKeith Short2020-04-092-8/+13
| | | | | | | | | | | | | | | | | | | | | Configure PWROK generation related signals for Ice Lake, Tiger Lake, and Jasper Lake SoCs. The array driven sequencing provides better flexibility for the PWROK signals, some of which may be automatically handled by the platform and some require EC control. BUG=b:150726713 BRANCH=none TEST=make buildall TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and verify signals are deasserted when exiting S0. TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK, verified JPL sequences to S0. Change-Id: Iceae29c65398643839b31f6cd757352282849fda Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* waddledoo:Handle EC_AP_PCH_PWROK_OD and ALL_SYS_PWRGDSooraj Govindan2020-02-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | As per Waddledoo power sequencing requirements, 1. ALL_SYS_PWRGD should be driven based on DRAM power good and the PP1050_ST power good. 2. the EC needs to assert EC_AP_PCH_PWROK_OD, with a 2ms minimum delay after receiving the DRAM power good and the PP1050_ST power good. 3. Enable CONFIG_BACKLIGHT_LID BUG=b:147257114 BRANCH=None TEST=make -j BOARD=waddledoo; flash waddledoo, verify that DUT can boot to S0. Change-Id: I5ad226faa15cfe8ae569524decf405bbd378a28c Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044250 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* intelrvp: Correct build assert array size comparisonVijay Hiremath2020-02-141-1/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I8eab72a146dd410af4f5e5c056f3393766284c5e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055884 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* power/icelake: JSL: Handle EC_AP_VCCST_PWRGDAseda Aboagye2020-02-051-0/+1
| | | | | | | | | | | | | | | | | For Jasperlake, the EC needs to assert EC_AP_VCCST power good with a 2ms minimum delay after receiving the DRAM power good and the PP1050_ST power good. BUG=b:148688874 BRANCH=None TEST=`make -j buildall` Change-Id: Ieedabf5a8a7af3951910118504dc702f7f8058bc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036453 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* power/icelake: JSL: Drive VCCIO_EXT from SLP_S3_LAseda Aboagye2020-02-051-0/+1
| | | | | | | | | | | | | | | | | Per the power sequencing requirements, VCCIO_EXT, new for JSL, should be driven based off of SLP_S3_L deassertion/assertion. BUG=b:148630993 BRANCH=None TEST=Build and flash waddledoo, boot to S0, verify that VCCIO_EXT is enabled. Shutdown, verify it's disabled. Change-Id: I2a25b29ebbde94eabf6b71c5c02252ebbd6ad1d9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032728 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Charger: Convert boards to use new driver structureDiana Z2020-02-041-0/+13
| | | | | | | | | | | | | | | This commit removes the temporary common charger chip configuration and instead puts the configuration in each board. BRANCH=none BUG=b:147672225 TEST=builds, runs on waddledoo and octopus Change-Id: If81aef31e48c65999a87e202494f286716114bbb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* jslrvp: add Jasperlake RVP supportDivagar Mohandass2019-12-265-0/+419
Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. Battery 4. Charger 5. USB TYPE-C MUX, DP/HDMI, USB2/3 6. TPM-SOC communication 7. LED 8. Keyboard BRANCH=none BUG=b:146693933 TEST=Build, flash and boot the Jasperlake RVP platform to OS make BOARD=jslrvp_ite; sudo util/flash_ec --board=jslrvp_ite Change-Id: I80227833fcfca5636ac8f30abc099db5717bfa05 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980091 Reviewed-by: Justin TerAvest <teravest@chromium.org>
View Lorry Controller Status