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* drop unnecessary boards, chips and cts testsVadim Bendebury2020-01-079-2211/+0
| | | | | | | | | | | | | | | | | | | | The only board which would be built from this branch is Cr50. bds, fizz and host boards are necessary for proper make infrastructure operation and tests. lm4 and npcx are chips used by the bds and fizz boards, so they are also kept around. BRANCH=cr50, cr50-mp BUG=b:145912698 TEST='make buildall -j' succeeds Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-013-9/+10
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-311-1/+1
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-302-2/+5
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* tablet_mode: Renaming for GMR sensorPhilip Chen2019-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GMR sensors can be used to (1) detect clamshell/tablet mode (2) detect lid open/closed But hall sensors can only do (2). Therefore the naming related to "hall sensor" for tablet mode application is incorrect. This patch performs the following renaming to better reflect the reality: config: CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR -> CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR GPIO: HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L functions: hall_sensor_disable() -> gmr_tablet_switch_disable() hall_sensor_isr() -> gmr_tablet_switch_isr() hall_sensor_int() -> gmr_tablet_switch_init() variable: hall_sensor_at_360 -> gmr_sensor_at_360 BUG=b:139378190 BRANCH=none TEST=make buildall Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* config: Refactor CONFIG_ACCEL_FIFO to enable use of IS_ENABLEDYuval Peress2019-09-031-3/+4
| | | | | | | | | | | | | | | This change allows us to use the IS_ENABLED condition to replace the various ifdef guards around the CONFIG_ACCEL_FIFO BUG=b:137758297,chromium:981990 BRANCH=None TEST=buildall and CTS tests on Arcada Change-Id: I65d36bac19855e51c830a33e6f3812575e8d15d9 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704164 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* power: Replace weak attr with __overridableYilun Lin2019-08-221-1/+2
| | | | | | | | | | | | | | | | | This CL annotates __overridable to the following functions: board_system_is_idle power_chipset_handle_host_sleep_event power_board_handle_host_sleep_event TEST=make buildall BUG=none BRANCH=none Change-Id: I0168b69c49fab5672238711d4f3a6a5517cdd8b3 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1761759 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-202-30/+30
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-192-30/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-132-32/+0
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-8/+10
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: motion_sense: Require CONFIG_MOTION_SENSOR_MAX_COUNTYuval Peress2019-06-051-0/+1
| | | | | | | | | | | | | | | This changes requires all boards to define the maximum number of sensors they support. This will allow us to later create static arrays with the appropriate length. BUG=chromium:966506 BRANCH=None TEST=make buildall Change-Id: I5a2fa8f0fdcaef69065dfd4c2bfea4e3f371e986 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1637414 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: Refactor tcpc_config to include a flags fieldScott Collyer2019-04-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | tcpc_config contained a field for both the alert polarity and open drain/push pull configuration. There is also a possible difference in TCPC reset polarity. Instead of adding yet another field to describe this configuration, it would be better to convert alert polairty, open drain and reset polarity into a single flags field. This CL modifies the tcpc_config struct to use a single flags field and adds defines for what existing flag options can be. BUG=b:130194031 BRANCH=none TEST=make -j buildall Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e Signed-off-by: Scott Collyer <scollyer@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551581 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-14/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-262-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion: Define macros for custom eventsGwendal Grignou2019-03-201-1/+2
| | | | | | | | | | | | | | Define macros to define custom events used by sensor interrupt handlers. Remove CONFIG_ for activity events. BUG=none BRANCH=none TEST=compile, sensors work on eve. Change-Id: I08ef6ed2a004466ebc5f7650d6952a150b9de713 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1272189 Reviewed-by: Jett Rink <jettrink@chromium.org>
* nautilus,reef_mchp: Remove board_is_ramp_allowedDaisuke Nojiri2018-12-141-15/+0
| | | | | | | | | | | | | | | | | board_is_ramp_allowed is replaced by chg_ramp_allowed and no longer called. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Iedf760567b4034ce7317a0d2479eb7ee937b4680 Reviewed-on: https://chromium-review.googlesource.com/1377342 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* motion_lid: Use CONFIG_TABLET_MODEFurquan Shaikh2018-11-291-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | This change updates motion_lid driver to use CONFIG_TABLET_MODE to decide if device requires reporting of tablet mode. This basically makes the config options CONFIG_LID_ANGLE_INVALID_CHECK and CONFIG_LID_ANGLE_TABLET_MODE obsolete. Now that EC will always report tablet mode aligned with Chrome (at 180 degree), any device that supports tablet mode and uses motion lid driver will require this by default and should not require boards to individually select any special config options. Thus, it also gets rid of unused CONFIG_LID_ANGLE_TABLET_MODE and CONFIG_LID_ANGLE_INVALID_CHECK. BUG=b:120050761 BRANCH=octopus TEST=make -j buildall Change-Id: Ib73af66ca1c17d4033cf54f0b4b86bf41793f3a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1350470 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nautilus: Enable multi-profile DPTFFurquan Shaikh2018-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | This change enables multi-profile DPTF by selecting the following config options: 1. CONFIG_DPTF_MULTI_PROFILE: Set appropriate profile number based on mode. 2. CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR: Indicate board does not have a hall sensor and hence profile numbers are updated by motion_lid driver. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ib6f146d4465e815f7f008cc3e2682e412acc32bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313469 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* dptf: Get rid of CONFIG_DPTF_DEVICE_ORIENTATIONFurquan Shaikh2018-10-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to the host to allow it to read the tablet mode flag from shared EC memory and select the right DPTF table to load (if supported). However, this config seems unnecessary because of the following reasons: 1. Host sets SCI mask to indicate to the EC which events it wants to process. Thus, even if the EC sets mode change flag, it will not be notified to the host unless it supports mode change event. 2. Additionally, if host supports mode change event, but does not support multiple DPTF tables, then EC ACPI code takes care of ensuring that there is a thermal event handler present to reload tables. 3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86 boards. BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ic4097ae047e2d559673a321da4df86514f902993 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1292359 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-2/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* type: Rename matrix_3x3_t to mat33_fp_tYilun Lin2018-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming of many vector types and matrix types are not clear enough. For example, we have: vector_3_t, which is a vector of three int. vec3_t, which is a vector of three float. size4_t, which is a vector of four size_t. mat33_t, which is a 3x3 matrix of float. matrix_3x3_t, which is a 3x3 matrix of fixed point. Besides, we have types like int8_t, uint16_t types. To clearly distinguished types, the CL propose to, For vector types, naming should be `$type + 'v' + $num + '_t'`: vector_3_t becomes intv3_t vec3_t becomes floatv3_t vector 4 of uint16_t becomes uint16v4_t (which doesn't exist yet) For matrix types, naming should be `mat$N$N_` + $type + '_t', where $N is the matrix size: matrix_3x3_t becomes mat33_fp_t # fp: fixed point mat33_t becomes mat33_float_t TEST=make buildall -j BUG=b:114662791 Change-Id: I51d88d44252184e4b7b3564236833b0b892edc39 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1215449 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus: decrease UART bufferJett Rink2018-08-301-1/+1
| | | | | | | | | | | | | | | | We are running out of RAM space for nautilus and the UART buffer does not need to be 4KB. 1KB is almost enough, so 2KB should be plenty. In the long term chromium:826592 will allow us to use even smaller buffers. BRANCH=none BUG=chromium:826592,b:112088135 TEST=builds and links with child CL stack Change-Id: I054f884fea5761de26888a5b4fe26ded6c2ffbd9 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194082 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-273-3/+3
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nautilus: Remove the unused GPIO USB_POWERON_LPhilip Chen2018-07-172-6/+1
| | | | | | | | | | | | | BUG=b:111433611 BRANCH=poppy TEST=manually confirm USB-A port still works Change-Id: I70146f696056e526df08831847650710dea4a8ae Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1139400 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-233-3/+3
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nautilus: Move PMIC init to a deferred functionFurquan Shaikh2018-05-011-1/+4
| | | | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to nautilus board file) BUG=b:77336348 BRANCH=poppy TEST=None Change-Id: Id9eec4333c6f04141e475b61e5aea7b838dcedf7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1033614 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus: Enable usb device modeFurquan Shaikh2018-05-011-1/+8
| | | | | | | | | | | | | | | | BUG=b:78649985 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: I10addb4936eab169655c1d11f115740da139a14e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1031109 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nautilus: Shrink accelerometer FIFO to 512 entriesNicolas Boichat2018-04-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that the shared memory buffer on Nautilus starts at 200c7720 D __shared_mem_buf That's 29.78 kb into the RAM. Software sync needs 1kb, so we should be fine, expect that the last 2kb of RAM are supposed to be reserved for the "booter" (NPCX_BTRAM_SIZE). We shrink the accelerometer FIFO to 512 entries, freeing up 4kb of RAM, and increase the UART TX buffer to 4kb, to make use of 3kb of that freed up space: 200c7320 D __shared_mem_buf That's 28.78 kb into the RAM. BRANCH=poppy BUG=chromium:739771 TEST=make BOARD=nautilus -j, check that shared_mem_buf offset is < 29 kb. Change-Id: I361a439b847d31d3415f2ee66229bd32f8816e2d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1002712 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nautilus: Support tristate board id strapping pinPhilip Chen2018-04-092-0/+29
| | | | | | | | | | | | | | | | | | | | | With 3 binary strapping pins, we only have 7 available board ids: 000, 001, 010, 011, 100, 101, 110, 111. Let's make the MSB of board id tristate. So we can have 4 more board ids to use: Z00, Z01, Z10, Z11. BUG=b:77731277 BRANCH=poppy TEST=build nautilus Change-Id: I7aebb89437d2ccb9eea6c477155b25d964983232 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1000875 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus: Lower VCCIO from 0.975V to 0.850VFurquan Shaikh2018-04-041-4/+4
| | | | | | | | | | | | | | CQ-DEPEND=CL:*602341 BUG=b:77496214 BRANCH=poppy TEST=None Change-Id: If04161615343f573d0de0881667564f7384c2605 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/996804 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usbc: add default I2C addressesJett Rink2018-03-281-2/+12
| | | | | | | | | | | | | Add hard coded I2C addresses as defined by datasheet. BRANCH=none BUG=none TEST=none Change-Id: Ia69cc4da7474a9c1f8a994d33db88e0a405f02b7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982561 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nautilus: enable accel force mode mask on nautilusJongpil Jung2018-03-261-0/+3
| | | | | | | | | | | | | | | | | | | With change(938146), we need to define CONFIG_ACCEL_FORCE_MODE_MASK so that ec report sensor value to host. BUG=b:76134274 BRANCH=master TEST=compile, flash ec on DUT. check ectool motionsense, ectool motionsense lid_angle check if screen rotaion work or not. Change-Id: Ib8985d1865baf7373d02e235d3ad32d4d0535398 Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/979749 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Remove the unnecessary words of "Disable touchpad" in the commentsKaiyen Chang2018-03-261-1/+2
| | | | | | | | | | | | | | | The control of trackpad from EC was entirely removed by CL:421275. So remove the unnecessary words of disabling touchpad in the comment of lid_angle_peripheral_enable(). BUG=none BRANCH=poppy TEST=none Change-Id: Ie688d9dc98c5f6f60a9d3908945495f4b6fdb00d Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/979572 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=b:76232539 BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nautilus: Use I2C callbacks to ensure minimum bus free time for batteryFurquan Shaikh2018-03-212-0/+36
| | | | | | | | | | | | | | | | | | Battery on nautilus requires a minimum bus free time of 5ms between I2C transactions. Use I2C_XFER_CALLBACK mechanism to ensure that this time is guaranteed before starting a new i2c transaction. BUG=b:73147310 BRANCH=None TEST=make -j BOARD=nautilus. Verified on nautilus that no issue is observed while charging the battery. Change-Id: Ieba168835190b5d1334e413dc4f74e0248bf5a15 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/957966 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus: Increase task stack sizes, add stack analysis annotationsNicolas Boichat2018-03-192-14/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On cros/firmware-poppy-10431.B, plus the patches on this branch: make BOARD=nautilus SECTION=RW analyzestack | grep Task Task: HOOKS, Max size: 728 (504 + 224), Allocated size: 800 Task: USB_CHG_P0, Max size: 672 (448 + 224), Allocated size: 720 Task: USB_CHG_P1, Max size: 672 (448 + 224), Allocated size: 720 Task: CHARGER, Max size: 712 (488 + 224), Allocated size: 800 Task: MOTIONSENSE, Max size: 720 (496 + 224), Allocated size: 768 Task: CHIPSET, Max size: 744 (520 + 224), Allocated size: 800 Task: KEYPROTO, Max size: 516 (292 + 224), Allocated size: 600 Task: PDCMD, Max size: 776 (552 + 224), Allocated size: 800 Task: HOSTCMD, Max size: 792 (568 + 224), Allocated size: 840 Task: CONSOLE, Max size: 840 (616 + 224), Allocated size: 880 Task: POWERBTN, Max size: 696 (472 + 224), Allocated size: 800 Task: KEYSCAN, Max size: 584 (360 + 224), Allocated size: 600 Task: PD_C0, Max size: 896 (672 + 224), Allocated size: 1000 Task: PD_C1, Max size: 896 (672 + 224), Allocated size: 1000 RO is identical 200c7720 D __shared_mem_buf There is still 2272 bytes of shared memory. BRANCH=poppy BUG=b:75234825 TEST=See above, software sync still works Change-Id: Ia98b27a924d0023a5fb3bfef5280e9365e6ddf4b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/965706 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* nautilus : system enter hibernation on reliability testYB.Ha2018-03-191-1/+1
| | | | | | | | | | | | | | | | | | The temperature of test chamber is 55'C. Battery temperature is over 60'c when system runs on test chamber. The system turns off and enter hibernation because discharging_max_c is set to 60'C. BUG=b:74414822 BRANCH=none TEST=Build, flash and check system in test chamber. Change-Id: Ibfe05f0f31a0ebd9f72926ff7efa8faacca08153 Signed-off-by: YB.Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/958802 Commit-Ready: YongBeum Ha <ybha@samsung.com> Tested-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* driver: bma2x2: Add perform_calibGwendal Grignou2018-03-161-1/+1
| | | | | | | | | | | | | | | | | | Add fast compensation automatic calibration, like bmi160. Use timestamp_expired for timeout measurement for both perform_calib functions. Remove driver offset field, remove private bma2x2 structure. BUG=b:73205042 BRANCH=master TEST=echo 1 > calibrate perform calibration. Reading in_accel_*_calibbias is within range. Check on Lami for both bma2x2 and bmi160. Change-Id: I3472865287fa4769a05e6f872b92d7c3f933cb4e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/957872 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* board: In motion sensor array, remove assignment to 0Gwendal Grignou2018-03-141-45/+0
| | | | | | | | | | | | Assignment to 0 are no necessary. BUG=none TEST=compile, check nami. BRANCH=none Change-Id: I1bc11efcff31cbfe2947580e7b8db0d5ba72d444 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/959502
* nautilus: Customize charging algorithmPhilip Chen2018-03-121-16/+63
| | | | | | | | | | | | | | | | | | | | | | According to the battery datasheet, the battery requires different voltage/current in different operating temperature. But this battery doesn't smart enough to ask for the proper voltage/current as the datasheet states. So let's override the charging voltage/current based on the datasheet. BUG=b:70906362 BRANCH=none TEST=none Change-Id: I5d6607a41970f6a1b62e6e410ae85f1f69a63a7c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/935204 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nautilus: Disable sensor in S5Furquan Shaikh2018-02-232-4/+5
| | | | | | | | | | | | BUG=b:73292704 BRANCH=None TEST=None Change-Id: I6f2f09232daed87fcd54a356ee13e69bfeda994c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/918381 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Jerry Parson <jwp@chromium.org>
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