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* CHERRY-PICK: nocturne: Add internal pull-ups to unused strap pinsDivya Sasidharan2020-05-051-0/+4
| | | | | | | | | | | | | | | | | | | | This change prevents leakage current on strap pins and saves around 1mW on nocturne. BUG=b:117139495 BRANCH=firmware-nocturne-10984.B TEST=On Nocturne, saved EC power by 1mW Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1275136 Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Roy Mingi Park <roy.mingi.park@intel.com> Tested-by: Roy Mingi Park <roy.mingi.park@intel.com> Change-Id: I419402fa67e2497c25dad974b9e3d5a5984681bb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160870 Tested-by: Patryk Duda <pdk@semihalf.com> Commit-Queue: Patryk Duda <pdk@semihalf.com>
* CHERRY-PICK: nocturne: Add internal pull-downs to unused NVME pinsRoy Mingi Park2020-05-051-3/+3
| | | | | | | | | | | | | | | | | | | This change prevents leakage current on NVME pins and saves around ~0.33mW on nocturne. BRANCH=nocturne BUG=b:117139495 TEST=Check npcx EC power to see power improvement Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1275126 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: I546dd7100698181ea1549752565fb2f01cff0289 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160867 Tested-by: Patryk Duda <pdk@semihalf.com> Commit-Queue: Patryk Duda <pdk@semihalf.com>
* CHERRY-PICK: nocturne: Set I2C5 to 1.8V if possible.Puthikorn Voravootivat2020-05-051-3/+3
| | | | | | | | | | | | | | | | | We shouldn't make GPIO pins stay at 3.3V mode when we can use 1.8V mode to lower power consumption. BUG=b:117139495, b:112037915 TEST=Lower power in S0ix. ALS works fine. Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1257660 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: I87d07c8b0d6d8714c0d257b5ba234518b41ffd9c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160865 Tested-by: Patryk Duda <pdk@semihalf.com> Commit-Queue: Patryk Duda <pdk@semihalf.com>
* nocturne: Set up SBU FETs properly.Aseda Aboagye2019-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SBU FET control should be tied to entering/exiting DP Alt Mode and not the USB MUX position as the previous commit had. However, the SBU lines are also used for CCD and the older boards don't have the necessary hardware. BUG=b:114340064 BRANCH=firmware-nocturne-10984.B TEST=Flash nocturne; verify that external display works after a reboot. Verify that cr50 is enumerated using SuzyQable. TEST=Repeat above test on board rev 1. Change-Id: I5ab9123816fa6ef946dde95b421c5b89bd9719a4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1250028 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1405611 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nocturne: enable GPIO-based MKBP event notificationEnrico Granata2018-10-121-1/+1
| | | | | | | | | | | | | | | | | | | This commit configures nocturne to send MKBP events over GPIO for boards with ID >= 2, as well as over the existing host event path. This latter notification is sent for legacy compatibility purposes, largely with existing depthcharge behavior. BUG=b:112366846, b:112112483, b:112111610 TEST=physical buttons work in depthcharge + MKBP events come in on Nocturne via GPIO interrupt with no significant jitter change BRANCH=none Change-Id: I95668ab1140f1c1e6397fae42f5dc6103b404956 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1247343 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* nocturne: Turn on UHALL_PWR_EN by default.Aseda Aboagye2018-08-181-1/+1
| | | | | | | | | | | | | | | | UHALL_PWR_EN needs to be enabled when the EC comes out of reset so that the top hall sensor is active when the EC boots. BUG=b:112110598 BRANCH=None TEST=Verify after EC reset that UHALL_PWR_EN is high. Change-Id: If0370dc462cb74b3f1b9bfb67aff7b9bc9c6e261 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180493 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Control UHALL_PWR_EN based on lid state.Aseda Aboagye2018-08-171-1/+0
| | | | | | | | | | | | | | | BUG=b:112110598 BRANCH=None TEST=Flash nocturne; verify board still boots. Check that the logic would do the right thing if the board version matched. Change-Id: I39bd7eb6f3d73dde4c42b3abfbb38d0de424dcf5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179314 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne: Change RCAM_VSYNC to rising edge.Aseda Aboagye2018-08-151-1/+1
| | | | | | | | | | | | | BUG=b:111282744 BRANCH=None TEST=`make -j BOARD=nocturne` Change-Id: I2588291e4daf336ad9365bc21faef0761386c989 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1175542 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* nocturne: Support new base USB fault protection IC.Aseda Aboagye2018-06-211-0/+1
| | | | | | | | | | | | | | | | | | There is a new protection IC being introduced that will indicate a fault on the data lines. This commit adds support for that new fault pin which will follow the same behaviour as the other base power fault pin. The EC should disable pogo power when this goes off. BUG=b:110204244 BRANCH=None TEST=make -j BOARD=nocturne Change-Id: Ia29bbe7109abf22a372e4d50870d870b8bbde4c7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1110940 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Fix CPU_PROCHOT polarity.Aseda Aboagye2018-06-081-1/+1
| | | | | | | | | | | | | | | | | Nocturne's CPU_PROCHOT is active low. Additionally, it's a 1V signal, so enable 1.8V GPIO logic to give it a chance of reporting the right thing. BUG=b:109882953 BRANCH=poppy TEST=Flash nocturne; verify that PROCHOT isn't asserted by default. Change-Id: I90126b3e495fa6e83b03c893cc3090cad90e1d5a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1092151 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* nocturne: Change SYS_RST_L to open drain.Aseda Aboagye2018-06-071-1/+1
| | | | | | | | | | | | | BUG=b:80500449 BRANCH=poppy TEST=flash nocturne; verify that AP boots and chipset can be reset. Change-Id: Icd195b6323bb4e94eb4184231860e755d40c0675 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1087547 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Add pull ups on PD INTs.Aseda Aboagye2018-05-291-2/+2
| | | | | | | | | | | | | | | | | BUG=b:79619258 BRANCH=master TEST=Source on C0, verify can Sink on C1. Change-Id: Ic03a99d10cb207db0f8e892289575450809fce05 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1056867 Reviewed-by: Benson Leung <bleung@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 6aef8f22b4dfc2a7427bc3d8a2c5375323ca03ed) Reviewed-on: https://chromium-review.googlesource.com/1058889 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Fix PWM0 alternate pin definition.Aseda Aboagye2018-05-291-1/+1
| | | | | | | | | | | | | | | | | | | The pin was not configured correctly. BUG=None BRANCH=None TEST=Flash nocturne, verify PWM0 is functional. Change-Id: I7cd6c9b541af6df42d5c6a07bff3557ca4fd53c4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1055909 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 39751b29e4e0f30416ea70c58f21d0bd9d1c4e3b) Reviewed-on: https://chromium-review.googlesource.com/1058888 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Fix EC hibernate.Aseda Aboagye2018-05-221-2/+2
| | | | | | | | | | | | | | | | | | | | This commit adds the appropriate hibernate flags to the hibernate wake pins. It additionally, adds a board specific hibernate function which sets up the PSL pins for wake as well as writing to the ROP PMIC to disable all the power rails. BUG=b:79713379 BRANCH=poppy TEST=Enter `hibernate` on EC console, verify that system can wake from AC insertion, power button press, and lid switch. Change-Id: I5b197c3c4d54cfc9c0b00c19815faa019f8b8cae Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1067892 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* nocturne: Add PMIC init.Aseda Aboagye2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | The 5V power good needs to be masked in the ROP PMIC otherwise the PMIC resets the EC rails after about ~4s. Additionally, changed EC_PLATFORM_RST to an output. BUG=None BRANCH=poppy TEST=Check that 5V PG is masked in the PMIC. Change-Id: Id06c85d1cea9a35d9e7418de5c0e9d0abd620607 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1055908 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> (cherry picked from commit 9ebdc6c252d8d55c51ccc954e9957c908b4e1a60) Reviewed-on: https://chromium-review.googlesource.com/1058887 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board: Add initial nocturne support.Aseda Aboagye2018-05-011-0/+117
BUG=b:78539498 BRANCH=None TEST=make -j BOARD=nocturne Change-Id: I830ff6739fb648625536ba248eeb383797c850e2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1032094 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
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