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* audio_codec: npcx: deprecate legacy option CONFIG_WAKE_ON_VOICETzung-Bi Shih2020-01-142-2/+4
| | | | | | | | | | | | | | | | | | | | | CONFIG_WAKE_ON_VOICE consists 3 features in NPCX: - DMIC - I2S_RX - WOV These features has broken down into smaller CONFIG options. Deprecates CONFIG_WAKE_ON_VOICE and prepares to separate smaller features in NPCX. BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ieaa123299ea687644f19066cf95ef150a18bf252 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986687 Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* ec-fans: Make fans configuration const by default.Andrew McRae2019-11-021-1/+1
| | | | | | | | | | | | | | | | It was pointed out to me that the fans config list was non-const, but there is only 2 boards that require non-const configuration, so by default make it const, but allow an override. BRANCH=none BUG=None TEST=EC compiles, make tests, buildall Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025 Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+2
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-11/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx7_evb: illustrate the flash configuration of npcx7m7wcCHLin2019-04-042-3/+5
| | | | | | | | | | | | | | | | | | | | | There are only 512 Kbytes of internal flash in Rev.C of npcx7m7w (i.e. npcx7m7wc.) It is different from the Rev.B of npcx7m7w (i.e. npcx7m7wb.) This CL illustrates how to set the flash type and flash size when chip variant is npcx7m7wc. BRANCH=none BUG=none TEST=pass "make buildall". TEST=with related CLs, switch to different chip variant in build.mk; build and flash the image; make sure each EC image can boot up on EVB or internal testing board of different chip variant. Change-Id: I2b50c7a023b1634ed4a200cb826532174baae117 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1543063 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx7_evb: illustrate the flash configuration of npcx7m6fcCHLin2018-12-042-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | There are only 512 Kbytes of internal flash in npcx7m6fc, which is different from previous npcx7 chips with internal flash. This CL illustrates how to set the flash type and flash size when chip variant is npcx7m6fc. This CL also sets the BOARD_VERSION number according to the chip variant. Manually changing the BORAD_VERSION number is no longer need when we want to build the npcx7_evb board image of different chip variants. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Switch to different chip variant in build.mk; build and flash the image; make sure each EC image can boot up on EVB of different chip variant. Change-Id: I430a39fae8c9516c0f22b0fe9868403a60b80d4a Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1351918 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: uart: Add driver support for the second UARTCHLin2018-07-052-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nuvoton NPCX79nxB serie chips include two UART ports. In this CL, we add the driver support for these two UART modules. Develoers can select one of the UART ports as EC console by configuring "CONFIG_CONSOLE_UART" in board.h BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB; check EC console working via J21. TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB; check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3 must be connected together.) TEST=build images of board npcx_evb, poppy, and grunt, make sure EC console is functional on these boards. TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write function still works by using the console command like: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1113269 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: change chip variants of npcx7 series for better clarification.Mulin Chao2018-04-272-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w to npcx7m7wb for better clafiication since it introduced new parameter "b" for chip generation in the same family series. In new npcx7 series naming rule, it follows: Format: NPCX7(M)(N)(G/K/F)(B/C) param M: 8: 128-pins package, 9: 144-pins package param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size param G/K/F/W: Google EC depends on specific features. param B/C: Chip generation in npcx7. (Generation A is ignored. It follows nameing rule in npcx5.) The all chip variants of npcx7 used in boards are also listed below: npcx7m6g - for npcx7 ec without internal flash on npcx_evb. npcx7m6f - for npcx7 ec with internal flash. npcx7m6fb - for npcx7 ec with internal flash, enhanced features. npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV. BRANCH=none BUG=none TEST=No build errors for npcx7 series. Change-Id: I896ee33209efa5d7157c90515005db5f36318c76 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1025471 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-1/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* fan: Allow board to configure fans at run timeDaisuke Nojiri2018-03-061-10/+15
| | | | | | | | | | | | | | | This patch splits struct fan_t into two parts: base configuration and RPM configuration. RPMs are expected to be different from model to model while a base configuration is most likely shared. BUG=b:73720175 BRANCH=none TEST=make buildall Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx7_evb: Define BOARD_VERSION for different npcx7 EVBsCHLin2018-01-242-5/+27
| | | | | | | | | | | | | | | | | | | | | There are two versions of npcx7 EVB. This CL adds the definition BOARD_VERSION (default is 2) in board.h. So we can include different features or set CONFIG_* flags based on the value of BOARD_VERSION to meet the default HW configuration of npcx7 EVBs. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change BOARD_VERSION to 1/2; "BOARD=npcx7_evb make"; Flash the image on EVB 1/2; make sure the EVBs bootup. Change-Id: Id4556f702af8c26778a649addde7cf490b5301fc Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/873510 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx7_evb: change the default setting of npcx7 evbCHLin2017-09-262-1/+7
| | | | | | | | | | | | | | | | | | | | | In this CL, we add the follow changes for npcx7 evb board: 1. Add comments in the build.mk to indicate how to set CHIP_VARIANT for EVBs which use different npcx7 ec. - npcx7m6f : 144 pins (default) - npcx7m6g : 128 pins 2. Turn on the eSPI host interface as default in board.h BRANCH=none BUG=none TEST=No build errors for "make buildall". Change-Id: Ib926e8596a09a28f547c35a0256be2aa394f9a36 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/674887 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7_evb: fix typos in the declaration of ADC3/4 channelsCHLin2017-07-161-2/+2
| | | | | | | | | | | | | | | | | | This CL fixes the typos of the enumeration values of ADC3 and ADC4 in the declaration of adc_channels[]. BRANCH=none BUG=none TEST=No build errors for make buildall. Test the image of npcx7_evb board on EVB. Change-Id: I510ad08f1dbc5ef668e28934d63cf73c7e5f5b5c Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/569498 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: clock: Add support for external 32kHz crystal osc.Mulin Chao2017-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | In this CL, we add selecting LFCLK sources functionality for npcx7 ec series. (Please notice not all of npcx7 ec series support this feature.) Beside internal LFCLK source, ec also can choose the external 32kHz crystal oscillator as LFCLK source for the specific application. We also introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this feature in the board level driver. This CL also adds: 1. LFCG register definitions in registers.h. 2. Change the order of each npcx modules by memory address. BRANCH=none BUG=none TEST=Output LFCLK source through GPIO75. Compare with external 32kHz crystal osc. on npcx7_evb and make sure the sources are the same. Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/520745 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7_evb: Add initial board driver of npcx7 ec evb.Mulin Chao2017-05-185-0/+360
Add the evaluation board driver of npcx7 series ec for testing. If you received the evb which ec is 128-pins package, please notice it has the following limitations. a. No GPIOD7/E0 pins. b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports. c. No ADC7, ADC8 and ADC9 channels. d. No JTAG port 1. e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb. This CL also includes: 1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg. Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ. 2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl. 3. Add npcx7_evb support in flash_ec. BRANCH=none BUG=none TEST=Passed all npcx7 drivers verification on the evb no matter which ec's package is 128 or 144 pins package. Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/505832 Reviewed-by: Randall Spangler <rspangler@chromium.org>