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* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-195-5/+5
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-11/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc: convert LPC only boards to use CONFIG_HOSTCMD_LPCJett Rink2018-05-221-1/+1
| | | | | | | | | | | BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I4a70e10c34d79361ceada1ff40b8912b8a6fdaa7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067500 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-1/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-0/+1
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* fan: Allow board to configure fans at run timeDaisuke Nojiri2018-03-061-19/+29
| | | | | | | | | | | | | | | This patch splits struct fan_t into two parts: base configuration and RPM configuration. RPMs are expected to be different from model to model while a base configuration is most likely shared. BUG=b:73720175 BRANCH=none TEST=make buildall Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7_evb: Add initial board driver of npcx7 ec evb.Mulin Chao2017-05-182-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the evaluation board driver of npcx7 series ec for testing. If you received the evb which ec is 128-pins package, please notice it has the following limitations. a. No GPIOD7/E0 pins. b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports. c. No ADC7, ADC8 and ADC9 channels. d. No JTAG port 1. e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb. This CL also includes: 1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg. Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ. 2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl. 3. Add npcx7_evb support in flash_ec. BRANCH=none BUG=none TEST=Passed all npcx7 drivers verification on the evb no matter which ec's package is 128 or 144 pins package. Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/505832 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Change second tachometer source from TB2 to TA2.Mulin Chao2017-04-183-6/+40
| | | | | | | | | | | | | | | | | | | | | | | | In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's input. Choosing TB2 as the second tachometer source is not correct since we didn't initialize the registers for TB2. This patch modified the second tachometer's input from TB2 to TA2 and passed the verification by following changes. 1. Add the second fan settings in pwm_channels, fans, and mft_channels arraies. 2. Modified ALTERNATE marco for pwm-type fans. 3. Set CONFIG_FAN from 1 to 2. 4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6) BRANCH=none BUG=none TEST=test dual fans with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx_evb: npcx_evb_arm: kahlee: Change pwm frequency of fan.Mulin Chao2017-04-161-1/+1
| | | | | | | | | | | | | | | | | | | Change pwm freq of fan from 100 to 25kHz. Normally, the operating freq of pwm fan is around 25kHz. The inappropriate pwm freq will cause the response time of fan spped is too long. Please notice the source clock of pwm is apb2 now. The clock will be gating if ec enters deep sleep. It should not enalbe CONFIG_LOW_POWER_S0 in board-level driver if fan is used. BRANCH=none BUG=none TEST=test fan used in kahlee and Sunon fan with fanset command on npcx_evb and use faninfo for verifying. Change-Id: Ic0e7509d9cdb2758bc6e674c207ac3dfbdc59dbe Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472647 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Move pwm open-drain functionality from gpio to pwm driver.Mulin Chao2017-03-242-5/+5
| | | | | | | | | | | | | | | | Setting PWM IO type in gpio driver seems not a proper way. This CL moves this functionality to pwm driver and introduces a new flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it in board driver. BRANCH=none BUG=none TEST=test pwm functionality on npcx_evb. Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: flash: Use common code for SPI flash protect reg translationShawn Nematbakhsh2016-12-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | Common code is more flexible and supports more parts, so delete the npcx-only register translation code. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28 gets written to SR1, which matches our desired 'protect botton 128KB', according to the datasheet. Also run 'flashrom -p ec --erase' then read back EC SPI contents, verify ROM is erased except for first 128KB region. Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/413228 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365) Reviewed-on: https://chromium-review.googlesource.com/415498 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* Remove Makefile symlinks under board directoryDaisuke Nojiri2016-07-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This feature is inconsistent. Not all boards have such a symlink (for a obvious reason). This feature is fragile. It's most likely not tested and going to be broken if not already. Developers won't like it if they have to test two different ways to build boards before submitting patches. This feature is not necessary. If you build EC in the standard way (e.g. make BOARD=samus), these symlinks are not needed. This feature is wasteful. Extra disk spaces are used and extra lines are added to Makefile (increasing code complexity slightly). BUG=chromium:626776 BRANCH=none TEST=make buildall Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359321 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-271-1/+1
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* npcx: Add CHIP_VARIANT variant for different versions of npcx ec.Mulin Chao2016-03-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT variant to distinguish which verson ec is. In config_chip.h, we use CHIP_VARIANT to specify the size and start address of program memory. Ecst tool also needs a chip parameter to make sure the address range checking of entry pointer won't fail. Modified sources: 1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec of npcx ec. 2. config_flash_layout.h: Replace constant value with CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE. 3. build.mk: Add -chip parameter for ecst tool to check entry address. 4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g). BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330072 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Add 1.8V IO support for some GPIOs and I2C pins.Mulin Chao2016-03-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 1.8V IO support for some GPIOs and I2C pins. We use a array (gpio_lvol_table) to confine which IO pins can switch to 1.8V. Before setting it to support low voltage level, FW should set IO pin's type to open-drain and disable internal pulling up or down. We also add examples in gpio.inc of npcx_evb and npcx_evb_arm to indicate how to set GPIO & I2C pins to 1.8V if user adds CONFIG_TEST_1P8V definition in board.h. In i2c.c driver, this version removes the internal pull-up feature of i2c ports since the driving force is too weak. (about 30K ohm) Modified sources: 1. gpio.c: Add 1.8V IO support for some GPIOs and I2C pins. 2. i2c.c: Remove internal pull-ups feature for i2c pins and move 1.8V support to gpio.c. 3. register.h: Modified NPCX_LV_GPIO_CTL register & bits definitions. 4. npcx_evb\gpio.inc: Add examples of 1.8V IO. 5. npcx_evb_arm\gpio.inc: Add examples of 1.8V IO. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I73a840ae321820212e50d609dab17576117a7d64 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330037 Reviewed-by: Shawn N <shawnn@chromium.org>
* NPCX: Convert keyboard pins to use ALTERNATE macroAnton Staaf2016-03-021-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously the keyboard row and column pins could not use the GPIO alternate function mechanism because their DEVALT bits were inverted with respect to all of the others, making it impossible to correctly configure them. With the refactor of the GPIO driver we can now add the keyboard DEVALT entries to the gpio_alt_table, and use the ALTERNATE macro and associated APIs to control the keyboard pin states. The Wheatley RO firmware image is still 320 bytes smaller than before the GPIO refactor. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Ran on Wheatley, manually verified keyboard functionality Change-Id: Id04bc010834b5d95050b03ace6b0e1c5690757bf Reviewed-on: https://chromium-review.googlesource.com/329762 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Add warning comment to gpio.inc filesBill Richardson2016-02-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | With commit e9883124ff16, a GPIO_INT macro was added. That change also required that all instances of GPIO_INT in a board's gpio.inc file come before any GPIO macros, or the interrupt handler wouldn't work properly. This CL just adds a warning comment about requirement to all gpio.inc files. BUG=chromium:471331 BRANCH=none TEST=make buildall, test image on Cr50 This is a change to comments only. There is no new behavior to verify, although I did run try out one new image just to be sure nothing stupid happened. Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329334 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Support hibernate_wake_pins on wheatley, npcx_evb and npcx_evb_arm.Mulin Chao2016-01-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb and npcx_evb_arm. For better power consumption, we disable ADC, tri-state spi pins, all inputs of wake-ups to prevent leakage current caused by input floating and set necessary GPIOs' states in hibernate function. Modified drivers: 1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate. 2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate. 3. wheatley/board.c: Add hibernate_wake_pins array for hibernate. 4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting GPIOs' status related to board for better power consumption. 5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt will disable before it is called. 6. register.h: Add WKINEN definition and declarations used for hibernate. 7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs' state and wake-up inputs before entering hibernate. 8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field. 9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/321466 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Support rpm mode for fan control.Mulin Chao2016-01-061-5/+5
| | | | | | | | | | | | | | | | | | | | | | | In order to support rpm mode, we use a TICK function (fan_tick_func) to monitor tacho value and adjust PWM duty. In this version, fan driver always enables clock source of MFT to make sure it can present real-time tacho value. For better performance, the feedback value to adjust PWM duty is various. We also change fan & pwm settings for SUNUN 4-pins pwm-type fan. Modified drivers: 1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec. 2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec. 3. fan_chip.h: Remove unnecessary default_count field of mft_t structure 4. fan.c: Add support for rpm mode BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320510 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pwm: Add common initialization for PWM pinsShawn Nematbakhsh2015-12-041-4/+4
| | | | | | | | | | | | | | | | | | | Rather than having various PWM module groups initialized from various HOOK_INIT functions, group them all into a single module and initialize them all from a common function in pwm.c. BUG=chromium:563708 TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that samus fan + KB backlight control is functional and samus_pd correctly sets PWM output. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941 Reviewed-on: https://chromium-review.googlesource.com/314882 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-031-0/+2
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* nuc: Simplify adc/pwm/fan drivers and related structures in boardsMulin Chao2015-09-293-45/+10
| | | | | | | | | | | | | | | | | | | Modified drivers: 1. register.h: Add marco field operation funcs for muti-bits field of register. 2. adc.c/fan.c/pwm.c: Simplify field operations by marco funcs. 3. adc.c: Add support for ADC_CH3/4 4. pwm.c: Add PWM_CONFIG_DSLEEP_CLK flag 6. fan.c: Support multi-fans mechanism BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Iaaeb6c4ae8d55b4245a1cefb9c20feae4c0fdec2 Reviewed-on: https://chromium-review.googlesource.com/300673 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc:Mulin Chao2015-08-193-11/+18
| | | | | | | | | | | | | | | | | | | | | Modified i2c driver into controllers and ports to support I2C0 port 0/1 at the same time. Modified drivers: 1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions used by i2c_wedge and i2c_unwedge. 2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func. 3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should replace GLUE_SDP0/1 with DP80BUF. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/294015 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-302-0/+9
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* nuc:Ian Chao2015-07-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-264-11/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Simplify GPIO listsSteven Jian2015-05-271-24/+24
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* gpio: Refactor IRQ handler pointer out of gpio_listAseda Aboagye2015-04-101-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the gpio_info struct, we had a irq_handler pointer defined even though a majority of the GPIOs did not have irq handlers associated. By removing the irq_handler pointer out of the struct, we can save some space with some targets saving more than others. (For example, ~260 bytes for samus_pd). This change also brings about a new define: GPIO_INT(name, port, pin, flags, signal) And the existing GPIO macro has had the signal parameter removed since they were just NULL. GPIO(name, port, pin, flags) In each of the gpio.inc files, all the GPIOs with irq handlers must be defined at the top of the file. This is because their enum values from gpio_signal are used as the index to the gpio_irq_handlers table. BUG=chromium:471331 BRANCH=none TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power button, keyboard, charging, all still working. TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build fail. TEST=make -j BOARD=peppy tests TEST=make -j BOARD=auron tests TEST=make -j BOARD=link tests Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263973 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* spi_flash: Add protect support for W25X40Shawn Nematbakhsh2015-03-111-1/+2
| | | | | | | | | | | | | | | | W25X40 uses a different protection register encoding than our existing W25Q64 code. Move the SPI ROM option to a config, and add support for the new part. BUG=chrome-os-partner:37688 TEST=`make buildall -j`. W25X40 protection code tested in a subsequent commit. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaaeabf42c6c62c20debc91afd2cf8671c14244c8 Reviewed-on: https://chromium-review.googlesource.com/258440 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Use SPI status register instead of pstateRandall Spangler2015-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npcx chip and evb use a SPI flash chip to hold the EC image. They don't need pstate, and should use the SPI flash status register directly. 1. Remove CONFIG_FLASH_PSTATE from npcx_evb. 2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect line to the SPI flash chip). 3. Change the npcx flash driver so that it directly reads/writes the SPI status register instead of mucking with pstate. BUG=chrome-os-partner:34346 BRANCH=none TEST=manual Add a switch or jumper to the EVB so R1 can be closed. Toggle the switch and see that WP_L state changes. Leave enabled. flashinfo -> nothing is protected, WP_L is enabled (=0) (also do this after each flashwp command to check the protection status) flashwp enable -> RO is protected now and at boot. reboot flashwp enable -> RO is still protected. flashwp disable -> RO is still protected. (because WP switch is enabled). Toggle the switch so WP_L is disabled (=1) flashwp disable -> Succeeds, flash is not protected Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253633 Reviewed-by: Shawn N <shawnn@chromium.org>
* WIP - Nuvoton 30-Jan patchRandall Spangler2015-02-253-16/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues fixed on 0216: 1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c 2.Modified warm_reset checking in gpio.c 3.Modified system_get_chip_name in system.c for package info. 4.Modified fan.c and pwm.c for: ● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low. ● Fan stall condition event: If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called. 5. Change cycle_pluses to 480 in board.c Issues fixed: 1. Jump data at top of RAM is getting corrupted. Changed the flag to RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST issue. 2. Hibernate wake need to report whether wake reason was GPIO or RTC 3. Hibernate wake must be distinguishable from watchdog reset. The booter will log reset reason in Code RAM. I copy the log data to battery-backup RAM in little FW. And system driver will refer this data to distinguish if it's watchdog reset or not. 4. Watchdog reset flag is not set. Same fix as 3. 5. Should return error if unable to clear SPI flash status register. 6. Remove chip_temp_sensor.c 7. Remove use of pstate from flash driver 8. Remove support for watchdog warm reset 9. Keyboard raw driver must support COL2 inverted 10. LPC memory mapped data must be read-only from host 11. LPC should support PLTRST# signal 12. Problems reading chip type/version. Use core registers and ROM data to read IDs. 13. When chip type/version is unknown, report hex value. 14. Watchdog does not consistently print panic information. 15. Remove console force enable logic. 16. Enable only the peripheral clocks that are needed. Please notice user should add bit mask in CGC_XXX_MASK if they want to enable additional module. For example, if user wants to enable PWM3, he must add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK. Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions. If I turn off all I2C modules in system_pre_init and turn on the modules I need in i2c_init, I found its freq is not correct. The root cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in clock_init) before i2c_init. At this time, i2c modules are power-down and writing to freq register is useless. I re-execute freq-changed hook function after turning on modules again. 17. MPU properly configured to prevent code execution from data RAM 18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM. Additional items we also modified: 1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func array to support it) 2. ec_npcxflash.c: Use definition to replace constant value. Stop watchdog during flash programing. 3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock MPU commands for Data RAM. BUG=chrome-os-partner:34346 BRANCH=none TEST=manually verify changes Change-Id: I722a77d29e7543b054819480c7b7477af4263119 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248670
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-145-0/+290
Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
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