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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-264/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* system: Clean up system_get_board_version()Philip Chen2021-07-091-1/+0
| | | | | | | | | | | | | | | | | | | Refactor system_get_board_version() a bit so that we can remove CONFIG_BOARD_VERSION_CUSTOM and CONFIG_BOARD_VERSION from config.h. BRANCH=None BUG=b:186264627 TEST=make buildall -j TEST=zmake testall Cq-Depend: chromium:3015243 Change-Id: Id5ab809493c297b7d330ea13dcd6934ec00042a6 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004112 Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chgstv2: Unify power-on and shutdown battery thresholdsDaisuke Nojiri2021-06-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, power-on battery SoC and shutdown battery SoC are independently configured by each board. This patch will unify the setting as follows: CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%) CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%) BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%) CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed) CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1 This allows us to show the low battery alert whenever we can because EC doesn't inhibit power-on even if it knows the host would immediately shut down. With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery threshold (and the SoC will be agreed between the EC and Powerd). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the same threshold. This is for avoiding degrading the UX by increasing the power-on threshold (even though a question that 1% may not be enough for soft sync to finish consistently remains to be answered). Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a lower threshold but we think 2% is enough to finish the software sync. A lower threshold also improves the UX by showing the low battery alert in the situation where otherwise the system would leave the user uninformed by not responding to a power button press. BUG=b:191837893 BRANCH=None TEST=buildall Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mkbp: Move key simulation to input devicesBoris Mittelberg2021-05-101-1/+1
| | | | | | | | | | | | | | | | | | Today some platforms include MKBP_KEYBOARD because they use side buttons, switches or other events that share the same driver with MKBP keyboard. Those platforms don't enable KEYSCAN task. The CL is moving key emulation functionality to MKBP input devices, to make a clear separation between the real keyboard usage and emulation/buttons/switches/etc. All boards that were selecting `CONFIG_KEYBOARD_PROTOCOL_MKBP` without KEYSCAN task are now updated to select `CONFIG_MKBP_INPUT_DEVICES` BUG=b:170966461 BRANCH=main,firmware-dedede-13606.B,firmware-volteer-13672.B-main TEST=None Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I515140ebf6e175f4b29991329f92266ffca232a8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2824044
* config: Provide default VCONN Swap delayAbe Levkoy2021-01-221-1/+0
| | | | | | | | | | | | | | | | | Almost every relevant board copy-pastes 5000 us. Make that the default and get rid of the redundant definitions. This is the approximate result of this command: find . -type f -name *.h | xargs sed -i -E \ '/#define CONFIG_USBC_VCONN_SWAP_DELAY_US[[:space:]]+5000[[:space:]]/d' BUG=b:144165680 TEST=make buildall BRANCH=none Change-Id: Ife86f9752971abcd7ab5ad5a5e607eb2ccbde2ba Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* config: Make VCONN Swap delay a documented optionAbe Levkoy2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This is the approximate result of the following command, run from platform/ec: find . -type f -\( -name '*.c' -o -name '*.h' -\) | \ xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g' Fix some latent formatting errors in usb_pd_protocol.c, because they were preventing pre-upload hooks from passing. BUG=b:144165680 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* COIL: Rename EC-EC comm config to be inclusiveDossym Nurmukhanov2020-12-121-1/+1
| | | | | | | | | | | | | Use server/client nomenclature instead BUG=none TEST=build and run on volteer BRANCH=none Signed-off-by: dossym@chromium.org Change-Id: I2cf4a82291134378ed21bbc068361f1be25e8176 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587574 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-051-1/+1
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_pd: Rename CONFIG_CMD_PD_CONTROL to CONFIG_HOSTCMD_PD_CONTROLVijay Hiremath2020-05-151-1/+1
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946 Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Various boards: Shrink UART Tx buffer to save spaceAbe Levkoy2020-05-011-1/+1
| | | | | | | | | | | | | | | | Future USB-PD discovery changes will need that space. In each case, reduce the size of the buffer by half (must be a power of 2). Note: This change is only to save shared memory space in the ToT build. It should not be picked onto release branches. BUG=b:152420269,b:152419795 TEST=make buildall BRANCH=none Change-Id: Ia26c1cdd7eb4068d410b81bb4a3335d2c9142049 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163795
* driver: Replace BMI160 to BMI in board configChing-Kang Yen2020-04-231-1/+1
| | | | | | | | | | | | | | | | | Replace some macro of BMI160 to BMI version for common function of BMI series. Make board config include the accelgyro_bmi_common.h instead of accel_gyro_bmi160.h. BRANCH=None BUG=b:146144827 TEST=make buildall -j Change-Id: I043ff8a92f15295ead3fa5c1e292319e2b4fa21a Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2156525 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* TCPMV1/2: Make the PD Config Flags more consistentSam Hurst2020-02-221-0/+1
| | | | | | | | | | | | | | | | | | | | The current use of the PD Config Flags are a bit confusing and has been changed to the following: The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY is enabled, one of the following must be enabled: CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine CONFIG_USB_PD_TCPMV2 - current power delivery state machine BUG=b:149993808 BRANCH=none TEST=make -j buildall Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-011-1/+1
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+2
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* config: Refactor CONFIG_ACCEL_FIFO to enable use of IS_ENABLEDYuval Peress2019-09-031-3/+4
| | | | | | | | | | | | | | | This change allows us to use the IS_ENABLED condition to replace the various ifdef guards around the CONFIG_ACCEL_FIFO BUG=b:137758297,chromium:981990 BRANCH=None TEST=buildall and CTS tests on Arcada Change-Id: I65d36bac19855e51c830a33e6f3812575e8d15d9 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704164 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-4/+4
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-12/+0
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: motion_sense: Require CONFIG_MOTION_SENSOR_MAX_COUNTYuval Peress2019-06-051-0/+1
| | | | | | | | | | | | | | | This changes requires all boards to define the maximum number of sensors they support. This will allow us to later create static arrays with the appropriate length. BUG=chromium:966506 BRANCH=None TEST=make buildall Change-Id: I5a2fa8f0fdcaef69065dfd4c2bfea4e3f371e986 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1637414 Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion: Define macros for custom eventsGwendal Grignou2019-03-201-1/+2
| | | | | | | | | | | | | | Define macros to define custom events used by sensor interrupt handlers. Remove CONFIG_ for activity events. BUG=none BRANCH=none TEST=compile, sensors work on eve. Change-Id: I08ef6ed2a004466ebc5f7650d6952a150b9de713 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1272189 Reviewed-by: Jett Rink <jettrink@chromium.org>
* config: Add magnetometer definitionsGwendal Grignou2019-02-081-1/+1
| | | | | | | | | | | | | | | | | | | Add all possible supported or soon-to-be supported configuration of magnetometer behind accelerometers. Use a more generic variable to indicate the i2c address of the secondary device. BUG=b:110143516,b:115587004 BRANCH=none TEST=compile Change-Id: Ic00c413f2ec5fa0e6bf1c98861daa02f00769a65 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361989 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* soraka: Enable multi-profile DPTFFurquan Shaikh2018-11-151-0/+3
| | | | | | | | | | | | | | | | | | This change enables multi profile DPTF for soraka by selecting CONFIG_DPTF_MULTI_PROFILE and setting appropriate profile numbers based on base attach/detach state. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:17844490 BRANCH=None TEST=make -j buildall Change-Id: I7b48025f8eeca9fd585099dc5dce011963780117 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313470 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* dptf: Get rid of CONFIG_DPTF_DEVICE_ORIENTATIONFurquan Shaikh2018-10-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to the host to allow it to read the tablet mode flag from shared EC memory and select the right DPTF table to load (if supported). However, this config seems unnecessary because of the following reasons: 1. Host sets SCI mask to indicate to the EC which events it wants to process. Thus, even if the EC sets mode change flag, it will not be notified to the host unless it supports mode change event. 2. Additionally, if host supports mode change event, but does not support multiple DPTF tables, then EC ACPI code takes care of ensuring that there is a thermal event handler present to reload tables. 3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86 boards. BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ic4097ae047e2d559673a321da4df86514f902993 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1292359 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* base_detect: Expose console command to force state.RaviChandra Sadineni2018-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an effort to test wake sources on any given platform, this CL exposes console command to set the base state. This console command can then be invoked by autottests from the uart interface. We have two implementations for managing base status. One is interrupt driven while the other is a polling via a task. Boards current implementations then are: interrupts: lux, soraka, cheza polling task: nocturne, zoombini For forcing base connect and disconnect, interrupts: Disable interrupts and set forced base state. polling task: Stop periodic task and set forced base state. On reset, interrupts: Schedule deferred task immediately and enable interrupts. polling task: Clear forced base state and begin rescheduling periodic task. Signed-off-by: RaviChandra Sadineni <ravisadineni@google.com> BRANCH=poppy,nocturne BUG=chromium:820668, b:37223093 TEST=Tested on lux, soraka and nocturne basestate a : attaches the lid, reflected in ui. basestate d : detaches the lid, reflected in ui. basestate r : resets to the correct state. Wakes the device up on lux and nocturne and soraka. Change-Id: Iab698e103a50b8d22bf216a6f816998cb158e38a Reviewed-on: https://chromium-review.googlesource.com/1184172 Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver: bmi160: Rename secondary i2c device addressGwendal Grignou2018-06-151-1/+1
| | | | | | | | | | | | Make it more generic, to support other magnetometer. BUG=b:110143516 BRANCH=none TEST=Compile Change-Id: I94cbbe6daf598680a2decde12d703650dfb7c04c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1101548
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* poppy: Enable usb device modeFurquan Shaikh2018-04-261-1/+0
| | | | | | | | | | | | | | | | | BUG=b:78577893 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: Ie1130eba3da4352e2a3e09eaad20886a1bea81a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029539 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* FIXUP: board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-04-071-1/+1
| | | | | | | | | | | | | | Enabled forced mode for BMI160 accelerometer on soraka by mistake. BUG=b:67112751,b:75533383 BRANCH=poppy TEST=Compile Change-Id: I429a1d527a56c371351f8248912c580f8680447f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000726 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Increase console buffer size to 4096 bytesNicolas Boichat2018-04-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | Increase the size from 1024 to 4096 to reduce the likelihood of overflows. To make space for the larger buffer, we reduce CONFIG_ACCEL_FIFO to 512 entries (from 1024 entries: saves 4096 bytes of RAM). grep shared_mem_buf build/lux/RW/ec.RW.smap Before this patch: 200c74e0 D __shared_mem_buf After this patch: 200c70e0 D __shared_mem_buf (we saved 1024 bytes of RAM) BRANCH=poppy BUG=b:77159941 TEST=Flash lux, see that we do not lose EC logs in /var/log/cros_ec.log. Change-Id: I320c370369364b280e59f490a86f057fbb502da3 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/983080 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=b:76232539 BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* tcpc: rename CONFIG_USB_PD_TCPM_ANX74XX to CONFIG_USB_PD_TCPM_ANX3429Jett Rink2018-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for ANX3429, rename the option especially since the ANX7447 driver will not reuse the ANX74XX driver which is being introduced in CL:956790. Also adding the CONFIG_USB_PD_TCPM_ANX740X and CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the ANX chip the anx74xx.c driver applies to. BRANCH=none BUG=chromium:824208 TEST=build all Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/973558 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-03-221-0/+3
| | | | | | | | | | | | | | | | Some board did not configured the ALS in force mode. We were lucky that their data was collected while scanning other sensors, but that's not true anymore since CL:959112 BUG=b:75533383 TEST=Compile BRANCH=poppy Change-Id: I4c6f744756a90dd9f2d142bb56826e91b806d5dd Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969627 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Removing unnecessary CONFIG_USB_PD_DISCHARGE defineJett Rink2018-02-011-1/+0
| | | | | | | | | | | | | | CONFIG_USB_PD_DISCHARGE is now defined automatically if you specify one of the specified options such as CONFIG_USB_PD_DISCHARGE_TCPC BRANCH=none BUG=none TEST=grunt still discharges using PPC Change-Id: I94086cfc58bebce9c62ad6aa52b7740b25276d89 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/894676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy: Enable dptf device orientationFurquan Shaikh2018-01-291-0/+1
| | | | | | | | | | | | | | | | This is required to support mode-aware DPTF. Also, there is no need to send mode change event in board specific code as that is already done by dptf common code. BUG=b:65467566 BRANCH=None TEST=Verified that trip point temperatures get updated in the OS depending upon the device mode. Change-Id: I854628bcde755bdb1c6c1b73fbfa0948e1d7e420 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/887725 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* lux: Add lux boardNicolas Boichat2018-01-101-0/+15
| | | | | | | | | | | | | lux is a dual-battery poppy derivative. BRANCH=none BUG=b:67029560 TEST=make BOARD=lux -j Change-Id: I01fdb1e5e2b4803cdf7f03f9e6ee73603f84a7b8 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/845542 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver/charger/isl923x: Make sure CONFIG_CHARGER_NARROW_VDC is setNicolas Boichat2018-01-101-1/+0
| | | | | | | | | | | | | | | | | | Without this, the battery will discharge if we disallow battery charging (e.g. calling charge_request with either voltage == 0 or current == 0, either by policy, or when the battery is full). Also update config.h to set the option whenever isl923x is used. BRANCH=none BUG=b:66575472 BUG=b:35585464 TEST=make buildall -j Change-Id: Id5515d5ea82a393a3693a3da44cbdc2778296a95 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856538 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy: Move base detection logic to separate fileNicolas Boichat2018-01-051-0/+2
| | | | | | | | | | | | | | | wand will have a very different detection logic: moving this to a separate file will make it easier and cleaner to implement. BRANCH=none BUG=b:67029560 TEST=make buildall -j TEST=soraka: Base detection still works, power is cut in S5. Change-Id: Ibc4ad0d9f5ad9a0df7834c712145035f7c62f335 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/851554 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy/soraka: Remove charger profile override functionsNicolas Boichat2018-01-051-1/+0
| | | | | | | | | | | | | | | | | | The battery gas gauge is configured properly, and we do not need these hacks. BRANCH=none BUG=b:70816727 TEST=On soraka, check that we can recover from dead battery TEST=On soraka, check that we can recover from battery cut-off (both HW and SW) TEST=Check that battery stops requesting power when over or under set temperature (done by ODM/battery vendor, see bug) Change-Id: I0b9d605632d86a3c39d07676d62374602ba068b4 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/835728 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nautilus/poppy: Drop comment about thermistorNicolas Boichat2017-12-241-1/+0
| | | | | | | | | | | | NCP15WB is actually the correct thermistor, let's drop that copy-pasted comment. BRANCH=none BUG=b:35585396 TEST=make buildall -j Change-Id: I5577bb70e354a6f2ef6338894793b808fe4b0e9a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
* config: Add CONFIG_BUTTON_TRIGGERED_RECOVERY.Aseda Aboagye2017-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_BUTTON_RECOVERY option was a little confusing especially when we have the CONFIG_DEDICATED_RECOVERY_BUTTON option. This commit renames CONFIG_BUTTON_RECOVERY to CONFIG_BUTTON_TRIGGERED_RECOVERY to help make things a little clearer. Additionally, to avoid copy paste, defining CONFIG_BUTTON_TRIGGERED_RECOVERY will populate the recovery_buttons table with either the volume buttons or a dedicated recovery button depending what the board is configured for. Lastly, if CONFIG_DEDICATED_RECOVERY_BUTTON is defined, CONFIG_BUTTON_TRIGGERED_RECOVERY is defined as well since it's implicit. BUG=chromium:783371 BRANCH=None TEST=make -j buildall Change-Id: Idccaa4d049ace0df3b98b35bdd38ac9dbd843200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/830917 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nautilus/poppy/soraka: Add support for dumping PMIC fault registersFurquan Shaikh2017-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If during PMIC initialization, it is identified that there was a VR fault, then dump fault registers 0x16 and 0x17 to EC console. This information is very useful during debugging sudden power losses in field and so it is printed out to EC console. Additionally, add panic reason with these register values as panic data so that OS can provide this information in cros ec panicinfo. This helps in retaining the information even if EC console logs overflow. BUG=b:65732924,b:69334392 BRANCH=None TEST=Verified that on the failing Lux system, PMIC VR fault is reported:"PMIC VRFAULT: PWRSTAT1=0x00 PWRSTAT2=0x01". Also, verified that pmic fault register info is reported correctly in panicinfo: cat /sys/kernel/debug/cros_ec/panicinfo > /tmp/panicinfo hexdump -n 1 -s 0x14 -e '"0x""%02X""\n"' /tmp/panicinfo 0x00 hexdump -n 1 -s 0x15 -e '"0x""%02X""\n"' /tmp/panicinfo 0x01 Change-Id: Ic6096887cd66046d11a5eb1d942b635b3e48a236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/674033 Reviewed-by: Shawn N <shawnn@chromium.org>
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