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* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-273-4/+4
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver: bmi160: Rename secondary i2c device addressGwendal Grignou2018-06-151-1/+1
| | | | | | | | | | | | Make it more generic, to support other magnetometer. BUG=b:110143516 BRANCH=none TEST=Compile Change-Id: I94cbbe6daf598680a2decde12d703650dfb7c04c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1101548
* espi: rename remaining eSPI optionsJett Rink2018-05-233-4/+4
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* poppy: Enable usb device modeFurquan Shaikh2018-04-263-3/+9
| | | | | | | | | | | | | | | | | BUG=b:78577893 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: Ie1130eba3da4352e2a3e09eaad20886a1bea81a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029539 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy: Prevent base detection from falling into reverse detection trapNicolas Boichat2018-04-131-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem here is that both normal detection range (120-300mV) and reverse connection detection range (450-500mV) are on the same side of the interrupt pin TTL level. So if we accidentally sample the ADC at the wrong time (either on connection, or after a side-band wake signal from base), we may fall into a trap where we assume that the base is connected in reverse, while the value may just be a transient. We have seen this case in the field, due to side-band wake pulse from base EC, but this could potentially happen on attach as well. The code debounces the reverse detection signal a little longer (this has no impact as the base is not functional anyway), so that we only consider that the base is connected in reverse if the ADC value is within the range twice in a row. BRANCH=poppy BUG=b:77828249 TEST=With HACK CL to emulate bug: - Press a few keys, hammer gets disconnected - Connect/disconnect hammer a few times, sometimes it does not get disconnected. TEST=Base connection, normal and reverse, still works properly. Change-Id: I2ccb911472dd591146e3b0e68400c8bd55368dba Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1010044 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy: Move PMIC init to a deferred functionNicolas Boichat2018-04-111-1/+4
| | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to poppy board file) BUG=b:77336348 BRANCH=poppy TEST=while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done for 24 hours Change-Id: Icd9c2096ca026da6308b74582144886b30ea965f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1003436 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* FIXUP: board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-04-071-1/+1
| | | | | | | | | | | | | | Enabled forced mode for BMI160 accelerometer on soraka by mistake. BUG=b:67112751,b:75533383 BRANCH=poppy TEST=Compile Change-Id: I429a1d527a56c371351f8248912c580f8680447f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000726 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Increase console buffer size to 4096 bytesNicolas Boichat2018-04-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | Increase the size from 1024 to 4096 to reduce the likelihood of overflows. To make space for the larger buffer, we reduce CONFIG_ACCEL_FIFO to 512 entries (from 1024 entries: saves 4096 bytes of RAM). grep shared_mem_buf build/lux/RW/ec.RW.smap Before this patch: 200c74e0 D __shared_mem_buf After this patch: 200c70e0 D __shared_mem_buf (we saved 1024 bytes of RAM) BRANCH=poppy BUG=b:77159941 TEST=Flash lux, see that we do not lose EC logs in /var/log/cros_ec.log. Change-Id: I320c370369364b280e59f490a86f057fbb502da3 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/983080 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* charge_state_v2: Hibernate base in S5 with no ACNicolas Boichat2018-03-281-0/+8
| | | | | | | | | | | | | | | | | | Tell the base to hibernate when we are in S5, and no AC is connected. Also, wake the base when AC status changes (S5), and when the system transistions out of S5. BRANCH=none BUG=b:71874971 TEST=1. Lid EC console: apshutdown => Check that Base EC hibernates 2.a. Lid EC console: powerb; => Check that base reconnects 2.b. Connect/disconnect adapter: check that base disconnects and reconnects Change-Id: I5e9a4afc64a07ad92f37d171a78a914d26f07c8e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/958814 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usbc: add default I2C addressesJett Rink2018-03-281-2/+12
| | | | | | | | | | | | | Add hard coded I2C addresses as defined by datasheet. BRANCH=none BUG=none TEST=none Change-Id: Ia69cc4da7474a9c1f8a994d33db88e0a405f02b7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982561 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=b:76232539 BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* tcpc: rename CONFIG_USB_PD_TCPM_ANX74XX to CONFIG_USB_PD_TCPM_ANX3429Jett Rink2018-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for ANX3429, rename the option especially since the ANX7447 driver will not reuse the ANX74XX driver which is being introduced in CL:956790. Also adding the CONFIG_USB_PD_TCPM_ANX740X and CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the ANX chip the anx74xx.c driver applies to. BRANCH=none BUG=chromium:824208 TEST=build all Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/973558 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-03-221-0/+3
| | | | | | | | | | | | | | | | Some board did not configured the ALS in force mode. We were lucky that their data was collected while scanning other sensors, but that's not true anymore since CL:959112 BUG=b:75533383 TEST=Compile BRANCH=poppy Change-Id: I4c6f744756a90dd9f2d142bb56826e91b806d5dd Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969627 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy: Lower VCCIO from 0.975V to 0.850VFurquan Shaikh2018-03-201-4/+4
| | | | | | | | | | | | | | CQ-DEPEND=CL:*591042 BUG=b:75978856 BRANCH=poppy TEST=No regressions observed. Change-Id: I3c481ac46bd9005df05f7be13bee8799959fb282 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/969786 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Increase task stack sizes, add stack analysis annotationsNicolas Boichat2018-03-192-12/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On cros/firmware-poppy-10431.B, plus the patches on this branch: make BOARD=soraka SECTION=RO analyzestack | grep Task Task: HOOKS, Max size: 776 (552 + 224), Allocated size: 800 Task: USB_CHG_P0, Max size: 696 (472 + 224), Allocated size: 800 Task: USB_CHG_P1, Max size: 696 (472 + 224), Allocated size: 800 Task: CHARGER, Max size: 776 (552 + 224), Allocated size: 800 Task: MOTIONSENSE, Max size: 664 (440 + 224), Allocated size: 768 Task: CHIPSET, Max size: 760 (536 + 224), Allocated size: 800 Task: PDCMD, Max size: 784 (560 + 224), Allocated size: 880 Task: HOSTCMD, Max size: 808 (584 + 224), Allocated size: 840 Task: CONSOLE, Max size: 856 (632 + 224), Allocated size: 960 Task: POWERBTN, Max size: 728 (504 + 224), Allocated size: 800 Task: PD_C0, Max size: 912 (688 + 224), Allocated size: 1000 Task: PD_C1, Max size: 912 (688 + 224), Allocated size: 1000 (RW returns identical values) All tasks have a good amount of slack (some have even more, as poppy board requires even more stack size than soraka). Shared_mem_buf at: 200c7400 D __shared_mem_buf (so there is still 3072 bytes of available RAM) BRANCH=none BUG=b:75234824 TEST=See line above, EC software sync still works Change-Id: I60d8574c827c1102f0968766b1e6c4a50f56071a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/966044 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy/soraka: Disable power button shutdown timer on the PMICFurquan Shaikh2018-03-151-0/+3
| | | | | | | | | | | | | | | | | | Similar to eve, disable power button shutdown by PMIC on long press of power button. Using Vup+Pwr is the still the best way to do a PMIC reset. BUG=b:74866345 BRANCH=poppy TEST=Verified that holding power button for >80 seconds did not trigger PMIC shutdown. Change-Id: I6a844b1b5d68a9e28daaf0452e461233057e1869 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/964889 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* board: In motion sensor array, remove assignment to 0Gwendal Grignou2018-03-141-75/+0
| | | | | | | | | | | | Assignment to 0 are no necessary. BUG=none TEST=compile, check nami. BRANCH=none Change-Id: I1bc11efcff31cbfe2947580e7b8db0d5ba72d444 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/959502
* base_detect_lux: Only allow enabling power if base is connectedNicolas Boichat2018-03-091-2/+7
| | | | | | | | | | | | | | | | | | | Since we only enable power to the base in the charger task (we can't enable power before OTG/power allocation is setup properly), there is a potential race when we quickly plug/unplug the base. Fix this by only allowing the enable power when the detection code knows that the base is actually connected. BRANCH=none BUG=b:74403503 TEST=Plug/unplug wand several times with charger attached, PPVAR_VAR_BASE is always 0 whenever the base is disconnected. Change-Id: I96da9ed39ddbbbe7aea54ad96c62fde6115538c0 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/956204 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "poppy/soraka: Enable VR decay for runtime and suspend S0ix"Haridhar Kalvala2018-03-011-1/+48
| | | | | | | | | | | | | | | | | Because of instability(corner case) occured in couple of boards, its better to enable VR_decay at SLP_S0 and disable it in S0 system state. BUG=b:70881268 BRANCH=None This reverts commit fac65e668c2b02d0af419c6a48f33a44f8e4ba11. Change-Id: I7dff9983befc68c33052fffcb058ac01579c5a47 Reviewed-on: https://chromium-review.googlesource.com/939225 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy/soraka: Enable VR decay for runtime and suspend S0ixFurquan Shaikh2018-02-201-48/+1
| | | | | | | | | | | | | | | | We have been using upstart script to force VR decay in runtime S0ix for a while now and haven't seen any issues. This change pushes the fix in EC so that we don't need the upstart script hack any more. BUG=b:70881268 BRANCH=None TEST=Verified by reverting upstart script that PMIC registers are programmed as required to enable VR decay in S0 and S0ix. Change-Id: I19729e907d2ae065758e69933d0b1d3e5b43d5e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856856 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* charge_state_v2: Safer power transfer between lid and baseNicolas Boichat2018-02-022-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid issues where adapter would drive against OTG of lid or base, and to make sure that we do not over-current the adapter, we disconnect the base/lid power transfer whenever a new adapter is connected. We reenable power transfer as needed. We also separate out base current control as a new function, that allows us to record the previous base current only when the base charge control command is successful, and ignore errors until the base is responsive for the first time. Finally, we make sure that charge_allocate_input_current_limit is only called from a single location in charger_task. BRANCH=none BUG=b:71881017 TEST=Plug/unplug base, reset lux EC, connect charger. Base is detected, power allocation works as expected. Change-Id: I8b206d5b0fbcf0fe868b56a0336745aebe2a6dc2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/880021 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Removing unnecessary CONFIG_USB_PD_DISCHARGE defineJett Rink2018-02-011-1/+0
| | | | | | | | | | | | | | CONFIG_USB_PD_DISCHARGE is now defined automatically if you specify one of the specified options such as CONFIG_USB_PD_DISCHARGE_TCPC BRANCH=none BUG=none TEST=grunt still discharges using PPC Change-Id: I94086cfc58bebce9c62ad6aa52b7740b25276d89 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/894676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy / soraka: Decrease input current limit to prevent OCShawn Nematbakhsh2018-02-011-2/+10
| | | | | | | | | | | | | | | | | | | | | | | Based on measurements, Soraka can pull more current than desired. Decrease the programmed current limit by an additional factor, determined by taking the worst-case power measurements across several different Soraka devices, to ensure that Soraka never pulls more current than desired. BRANCH=None BUG=b:67944740 TEST=Verify with `charger` that input current limit becomes 472mA when a 5V / 500mA charger is plugged, and 2896mA when a 5V / 3000mA charger is plugged. Change-Id: I2b2cb6f445533476d173cd7f5fb825d8b11d1405 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/890102 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Enable dptf device orientationFurquan Shaikh2018-01-294-4/+1
| | | | | | | | | | | | | | | | This is required to support mode-aware DPTF. Also, there is no need to send mode change event in board specific code as that is already done by dptf common code. BUG=b:65467566 BRANCH=None TEST=Verified that trip point temperatures get updated in the OS depending upon the device mode. Change-Id: I854628bcde755bdb1c6c1b73fbfa0948e1d7e420 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/887725 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* charge_state_v2: Basic dual-battery charging algorithmNicolas Boichat2018-01-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | First version of the algorithm, some TODOs are left in the code but this, generally, works reasonably well. When charging, we allocate input current in this general order: - Base system (fixed, low, number) - Lid system (based on PSYS) - Lid battery (estimating how much current the battery actually requires) - Base battery (similar estimation) - Provide everything else to lid When discharging, we generally: - First discharge the base battery - Then discharge the lid battery BRANCH=none BUG=b:71881017 TEST=Flash lux and wand, EC-EC communication works, adapter power is split in a sensible way, and discharging works fine. Change-Id: I8a4f87963962fc5466b2fedf1347eb4dadd35740 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/659460 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lux: Base detection codeNicolas Boichat2018-01-261-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | Lux base detection is a little trickier than previous bases, as the detection levels switch around when GPIO_EC_COMM_PD gets enabled: - When disconnected, low levels (~550mV) mean base got connected, and high levels (~3300mV) mean base is still disconnected. - When connected, low levels (~43mV) mean base got disconnected, and high levels (~2346mV) mean base is still connected. On reset, when base_status is unknown, we enable GPIO_EC_COMM_PD, to be able to differentiate between connected and disconnected. BRANCH=none BUG=b:67029560 TEST=Connect lux/wand, check that base gets detected correctly. TEST=Type reboot in EC console, base gets detected as well. Change-Id: I742def8e378a93c08e2dcc155b06cbca814e7fd8 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/845543 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy/nautilus: Enable ACCELGYRO3_INT_L BMI160 interruptsNicolas Boichat2018-01-211-0/+3
| | | | | | | | | | | BRANCH=none BUG=b:69656838 TEST=Flash soraka, AIDA64 works fine Change-Id: I98443f3aee8605fbc9b5080cda83ac2b42ba8cd8 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/869550 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* lux: Add lux boardNicolas Boichat2018-01-106-9/+84
| | | | | | | | | | | | | lux is a dual-battery poppy derivative. BRANCH=none BUG=b:67029560 TEST=make BOARD=lux -j Change-Id: I01fdb1e5e2b4803cdf7f03f9e6ee73603f84a7b8 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/845542 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver/charger/isl923x: Make sure CONFIG_CHARGER_NARROW_VDC is setNicolas Boichat2018-01-101-1/+0
| | | | | | | | | | | | | | | | | | Without this, the battery will discharge if we disallow battery charging (e.g. calling charge_request with either voltage == 0 or current == 0, either by policy, or when the battery is full). Also update config.h to set the option whenever isl923x is used. BRANCH=none BUG=b:66575472 BUG=b:35585464 TEST=make buildall -j Change-Id: Id5515d5ea82a393a3693a3da44cbdc2778296a95 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856538 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* poppy: Move base detection logic to separate fileNicolas Boichat2018-01-054-202/+223
| | | | | | | | | | | | | | | wand will have a very different detection logic: moving this to a separate file will make it easier and cleaner to implement. BRANCH=none BUG=b:67029560 TEST=make buildall -j TEST=soraka: Base detection still works, power is cut in S5. Change-Id: Ibc4ad0d9f5ad9a0df7834c712145035f7c62f335 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/851554 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy/soraka: Remove charger profile override functionsNicolas Boichat2018-01-052-43/+0
| | | | | | | | | | | | | | | | | | The battery gas gauge is configured properly, and we do not need these hacks. BRANCH=none BUG=b:70816727 TEST=On soraka, check that we can recover from dead battery TEST=On soraka, check that we can recover from battery cut-off (both HW and SW) TEST=Check that battery stops requesting power when over or under set temperature (done by ODM/battery vendor, see bug) Change-Id: I0b9d605632d86a3c39d07676d62374602ba068b4 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/835728 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy: Disable PULL_UP on BOARD_VERSION4Nicolas Boichat2018-01-031-1/+1
| | | | | | | | | | | | | | | | | All shipping products will have board ID >= 8, so the board ID strap 3 will never be left floating. In particular, board ID 8-15 will have an external pull-down on that pin, so leaving the internal pull-up enabled is detrimental to power. BUG=b:64503543 BRANCH=none TEST=Boot poppy rev6. Change-Id: I810b2a68ab8d35e9cea6fa18f1eeafa10e7039ea Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/845240 Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* nautilus/poppy: Drop comment about thermistorNicolas Boichat2017-12-241-1/+0
| | | | | | | | | | | | NCP15WB is actually the correct thermistor, let's drop that copy-pasted comment. BRANCH=none BUG=b:35585396 TEST=make buildall -j Change-Id: I5577bb70e354a6f2ef6338894793b808fe4b0e9a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Do not print base detection value if base stays connectedNicolas Boichat2017-12-211-2/+10
| | | | | | | | | | | | | Reduces amount of spam during EC-EC communication. BRANCH=none BUG=b:65697962 TEST=Flash lux and wand, less spam on console Change-Id: Ie66a3d0f4711741bf3d605f13e7595373c5246f5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/725124 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config: Add CONFIG_BUTTON_TRIGGERED_RECOVERY.Aseda Aboagye2017-12-182-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_BUTTON_RECOVERY option was a little confusing especially when we have the CONFIG_DEDICATED_RECOVERY_BUTTON option. This commit renames CONFIG_BUTTON_RECOVERY to CONFIG_BUTTON_TRIGGERED_RECOVERY to help make things a little clearer. Additionally, to avoid copy paste, defining CONFIG_BUTTON_TRIGGERED_RECOVERY will populate the recovery_buttons table with either the volume buttons or a dedicated recovery button depending what the board is configured for. Lastly, if CONFIG_DEDICATED_RECOVERY_BUTTON is defined, CONFIG_BUTTON_TRIGGERED_RECOVERY is defined as well since it's implicit. BUG=chromium:783371 BRANCH=None TEST=make -j buildall Change-Id: Idccaa4d049ace0df3b98b35bdd38ac9dbd843200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/830917 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Re-configure GPIO02 to be INPUT | PULL_UP for power savingayowu2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO02 (EC_HAVEN_RESET_ODL) is now configured to GPIO_ODR_HIGH, designed for EC to reset H1. And it's no longer used with just the HW path reserved (DNS R267 on schematic). Tests showed that INPUT | PULL_UP has lower EC power consumption so reconfiguring here. BUG=b:64503543 BRANCH=none TEST=manual (on chroot) $ make BOARD=soraka -j $ ./util/flash_ec --board soraka (on DUT) $ powerd_dbus_suspend (on chroot) $ dut-control -p $PORT pp3300_dsw_ec_ma -t 10 | grep @@ > @@ NAME COUNT AVERAGE STDDEV MAX MIN > @@ pp3300_dsw_ec_ma 5629 1.25 0.71 16.60 1.12 Without the change, the original setting gives: > @@ NAME COUNT AVERAGE STDDEV MAX MIN > @@ pp3300_dsw_ec_ma 4674 2.69 1.98 12.00 2.00 Change-Id: I4e2268612109155f57fdd236088cadaaba54bb3f Signed-off-by: Ayo Wu <ayowu@google.com> Reviewed-on: https://chromium-review.googlesource.com/786951 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus/poppy/soraka: Add support for dumping PMIC fault registersFurquan Shaikh2017-11-302-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If during PMIC initialization, it is identified that there was a VR fault, then dump fault registers 0x16 and 0x17 to EC console. This information is very useful during debugging sudden power losses in field and so it is printed out to EC console. Additionally, add panic reason with these register values as panic data so that OS can provide this information in cros ec panicinfo. This helps in retaining the information even if EC console logs overflow. BUG=b:65732924,b:69334392 BRANCH=None TEST=Verified that on the failing Lux system, PMIC VR fault is reported:"PMIC VRFAULT: PWRSTAT1=0x00 PWRSTAT2=0x01". Also, verified that pmic fault register info is reported correctly in panicinfo: cat /sys/kernel/debug/cros_ec/panicinfo > /tmp/panicinfo hexdump -n 1 -s 0x14 -e '"0x""%02X""\n"' /tmp/panicinfo 0x00 hexdump -n 1 -s 0x15 -e '"0x""%02X""\n"' /tmp/panicinfo 0x01 Change-Id: Ic6096887cd66046d11a5eb1d942b635b3e48a236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/674033 Reviewed-by: Shawn N <shawnn@chromium.org>
* OPT3001: Support MOTIONSENSE_CMD_SENSOR_[OFFSET|RANGE] for calibration.Marco Chen2017-11-263-17/+49
| | | | | | | | | | | | | | | | | | | | | | | | | 1. The original driver of OPT3001 a. didn't support to process the command of offset. b. implemented command of range to setter/getter of Range Number Field of chip. But reffering to cros_ec_light_prox.c from linux kernel side, these two commands are actually leveraged for in_illuminance_calib[bias|scale] and these calibration factors should be applied into raw lux value read from the chip. 2. Move ALS in Poppy / Soraka boards from ALS_TASK to MOTIONSENSE_TASK. 3. Mofify parameters of ALS in Reef board in order to adapt changes here. BUG=b:69236269 BRANCH=none TEST=Manually test on the DUT. Change-Id: Ic3b593feb3e4bc6da0bada6b5d614975f0cf2280 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/774341 Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: reconfigure GPIO60 to be INPUT | PULL_UP for power savingsRuben Rodriguez Buchillon2017-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | GPIO60 (PMIC_INT) is currently only configured for INPUT. Tests showed that INPUT | PULL_UP has lower power consumption so reconfiguring it here. BUG=b:64503543 BRANCH=none TEST=manual (on chroot) $ make BOARD=soraka -j $ ./util/flash_ec --board soraka (on DUT) $ powerd_dbus_suspend (on chroot) $ dut-control -p $PORT pp3300_dsw_ec_ma -t 10 | grep @@ > NAME COUNT AVERAGE STDDEV MAX MIN > pp3300_dsw_ec_ma 5637 1.68 0.17 7.92 1.56 for comparison, without the change, the MIN is 2.00mA Change-Id: I86407a1440765d040c39272480b185342597d52b Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/786720 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy/soraka/nautilus: Do not enable V5A in deep sleep stateFurquan Shaikh2017-11-221-19/+0
| | | | | | | | | | | | | | | | | | | V5A was enabled in deep sleep state to allow wake from base in deep S3 state. Now that poppy and variants don't plan to use deep S3, this change is no longer required. BUG=b:69053636 BRANCH=None TEST=Verified following: > ectool i2cxfer 3 0x30 1 0x41 Read bytes: 00 > ectool i2cxfer 3 0x30 1 0x2a Read bytes: 00 Change-Id: Ice8cabf5ecac3851400af5fef43821f596bc5224 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/786789 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy/soraka: Add GPIO_SEL_1P8V flag for 1.8V pinsFurquan Shaikh2017-11-221-3/+3
| | | | | | | | | | | | | | | | | | | Jerry pointed out that certain GPIOs which are 1.8V are set as 3.3V in gpio.inc. Fix these gpios by add GPIO_SEL_1P8V flag to the gpio description: GPIOD1/I2C3_SCL0 GPIOD0/I2C3_SDA0 GPIO36 ACCEL_GYRO_INT_L BUG=b:69481600 BRANCH=None TEST=make -j BOARD=soraka. Verified that screen rotation works in tablet mode. Change-Id: Ifbc474846aff0760f0b183a9cfeef2790738ca79 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/780142 Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy/soraka: Fix battery_is_present detectionFurquan Shaikh2017-11-201-18/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was recently identified that when we do a software based battery cutoff and leave the system in cutoff state for > 25-30 seconds, then both FG and battery enter shutdown/ship mode. In order to get the battery out of this state, charger needs to provide VBAT > Vstartup. However, with the current implementation of battery_is_present, if EC is unable to talk to the battery i.e. i2c commands to read battery status fails, then battery_is_present returns BP_NO indicating that the battery is not present. This results in charger state machine setting 0V and 0A to the battery, thus causing the BGATE to be switched off. In order to wake the battery from such condition, it is necessary to provide pre-charge current and minimum voltage to ensure that BGATE is switched on and VBAT > Vstartup is provided. This change updates the battery_is_present algorithm to: 1. Check if battery is physically present. If not, return BP_NO. 2. If battery is present now and was present before when we checked, then return BP_YES. 3. If battery just changed status to BP_YES, then check its disconnect status. If EC is unable to read disconnect status, then return BP_NOT_SURE. This allows the charger state machine to provide precharge current and minimum voltage. 4. If EC is able to read disconnect status, try reviving it if necessary. 5. Return BP_NO if battery is still disconnected or is cutoff or not initialized. 6. Else return BP_YES. BUG=b:69329874 BRANCH=None TEST=Factory verified following: 1. Recovery from software based cutoff : Pass 10/10 2. Recovery from hardware based cutoff : Pass 10/10 3. Recovery from hibernate : Pass 10/10 4. Recovery from critical battery condition : Pass 10/10 5. Boot-up in case of no battery : Pass 10/10 Change-Id: I248705f87469a8d6604da1b1919492766499dd73 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/776024 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-172-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: Lower sensor max ODRGwendal Grignou2017-11-151-0/+2
| | | | | | | | | | | | | | | | EC seems to miss sample while providing sensor data at 200Hz. Limit sensors ODR to 100Hz. BUG=b:67112751 BRANCH=none TEST=compile, tbd Change-Id: Ic324c3d989854ae8b7f6b27bf6338266ce01ceda Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753434 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "poppy/nautilus: Move pmic vr decay enable/disable to suspend/resume ↵Furquan Shaikh2017-11-151-2/+8
| | | | | | | | | | | | | | | | | | | | hooks" This reverts commit 1f767e3e91be388dee689ac85408dfb5e3414581. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall. Verified by adding prints that VR decay enable happens before SLP_S0# is asserted. Change-Id: I0353f70c65ebe673b0e1b5ddbae2bb04368308cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771055 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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