| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
GMR sensors can be used to
(1) detect clamshell/tablet mode
(2) detect lid open/closed
But hall sensors can only do (2).
Therefore the naming related to "hall sensor" for tablet mode
application is incorrect.
This patch performs the following renaming to better reflect the reality:
config:
CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE
CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM
CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR ->
CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
GPIO:
HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L
functions:
hall_sensor_disable() -> gmr_tablet_switch_disable()
hall_sensor_isr() -> gmr_tablet_switch_isr()
hall_sensor_int() -> gmr_tablet_switch_init()
variable:
hall_sensor_at_360 -> gmr_sensor_at_360
BUG=b:139378190
BRANCH=none
TEST=make buildall
Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also
defined. Remove references to CONFIG_CHARGER_V2 from board header files.
Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when
appropriate.
BUG=b:139699769
BRANCH=none
TEST=make buildall -j
Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change allows us to use the IS_ENABLED condition to replace
the various ifdef guards around the CONFIG_ACCEL_FIFO
BUG=b:137758297,chromium:981990
BRANCH=None
TEST=buildall and CTS tests on Arcada
Change-Id: I65d36bac19855e51c830a33e6f3812575e8d15d9
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704164
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL annotates __overridable to the following functions:
board_system_is_idle
power_chipset_handle_host_sleep_event
power_board_handle_host_sleep_event
TEST=make buildall
BUG=none
BRANCH=none
Change-Id: I0168b69c49fab5672238711d4f3a6a5517cdd8b3
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1761759
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The extentions were added to make the compiler perform most
of the verification that the conversion was being done correctly
to remove 8bit addressing as the standard I2C/SPI address type.
Now that the compiler has verified the code, the extra
extentions are being removed
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
TEST=verify sensor functionality on arcada_ish
Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an
embedded TCPC.
This patch adds bus_type field to struct tcpc_config_t so that a TCPC
location on other type of bus can be specified.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b
Reviewed-on: https://chromium-review.googlesource.com/1640305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This changes requires all boards to define the maximum number
of sensors they support. This will allow us to later create
static arrays with the appropriate length.
BUG=chromium:966506
BRANCH=None
TEST=make buildall
Change-Id: I5a2fa8f0fdcaef69065dfd4c2bfea4e3f371e986
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1637414
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In usb_port_power_smart.c, we restore charging mode to
CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE instead of USB_CHARGE_MODE_CDP
directly. The benefit is that when we change the default mode, we don't
need to amend usb_port_power_smart.c. This should be applied to this
board.c as well.
BUG=b:130767435
BRANCH=rammus
TEST=`make BOARD=rammus -j4`
Change-Id: I0aef5bf3856eca82cb210c2a48ba31065e58e710
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1621450
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
tcpc_config contained a field for both the alert polarity and open
drain/push pull configuration. There is also a possible difference in TCPC
reset polarity. Instead of adding yet another field to describe this
configuration, it would be better to convert alert polairty, open
drain and reset polarity into a single flags field.
This CL modifies the tcpc_config struct to use a single flags field
and adds defines for what existing flag options can be.
BUG=b:130194031
BRANCH=none
TEST=make -j buildall
Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e
Signed-off-by: Scott Collyer <scollyer@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1551581
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
It's simply a bad idea to describe a macro in multiple locations.
It'll make it hard to change. It'll be difficult to keep all
locations in sync.
This patch replaces the comment duplicated in all ec.tasklist with
a pointer to the CONFIG_TASK_LIST definition. The macro will be
described in a single place (just like all/most other macros).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313
Reviewed-on: https://chromium-review.googlesource.com/1551579
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Rammus boards do not have a dedicated GPIO for MKBP events
between EC and AP. On boards without this hardware support, the
tight timestamps feature cannot be reliably supported due to
issues with the performance of the ACPI SCI chain, compared to
a dedicated interrupt.
Disabling tight_timestamps restores legacy behavior that is known
to fare better with sensors events over SCI.
BUG=b:123700100
BRANCH=rammus
TEST=tight_timestamps is 0, ran CtsSensorTestCases
Change-Id: I459f2673abad7ff75ba9e8a844b7702dee1ef8c0
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1524667
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Define macros to define custom events used by sensor interrupt handlers.
Remove CONFIG_ for activity events.
BUG=none
BRANCH=none
TEST=compile, sensors work on eve.
Change-Id: I08ef6ed2a004466ebc5f7650d6952a150b9de713
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1272189
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch turns the USB type-a charging off by default in suspend mode.
If the DUT power on with connecting a USB device, the OS must send an
event to clear inhibit_charging_in_suspend. Otherwise, the USB device
will lost the power in suspend mode, and the wakeup event won't be
generated if the device is a wakeup source (eg. USB keyboard or mouse).
BUG=b:121438672
BRANCH=firmware-rammus-11275
CQ-DEPEND=CL:1423758
TEST=Power on DUT without connecting USB, then suspend the DUT.
Verfied the USB type-a charging off.
Change-Id: I39a0f85d7033b798a80e80cc302a2c72cebae8d6
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1424042
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On Rammus, the power mode of the USB Type-A is CDP. However, the default
configuration is SDP2. We don't meet any problem on previous setting
because of missing CONFIG_USB_PORT_POWER_SMART_INVERTED.
This patch fixes the incorrect CONFIG in board.h.
BUG=none
BRANCH=firmware-rammus-11275
TEST=make -j buildall
connect phone to type-a port, CDP works
Change-Id: I19a6f2c01faa452131fa036a28be2fc37ce06e58
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1424039
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On Shyvana, we found that if we put the Parade PS8751 and Analogix
ANX3447 on the same i2c bus, the ANX3447 would be broken because
of PS8751 i2c bus error. To avoid this kind of problem, we decided
to separate the TCPC i2c bus starting from board version >= 2.
The new assignment are ANX3447:i2c_0_0, PS8751:i2c_0_1.
This patch also adds a new config CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
for enabling runtime switching the TCPC setting.
BUG=b:118063849
BRANCH=firmware-rammus-11275
TEST=verified on DUT with board_version <= 1
verified on reworked DUT with board_version >= 2
Change-Id: I0bdc930c1a5e691239f5f5c256d380d0111eed91
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1381600
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch removes the CONFIG_SYSTEM_UNLOCKED to lock the EC and
adds the CONFIG_USB_PD_COMM_LOCKED to enable USB PD only when EC
is in RW.
BUG=b:111816190,b:119929973
BRANCH=master
TEST=make buildall -j pass
Change-Id: Id812a4036b9a72e60d72a67d4cf4541aa84d5940
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1350509
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change updates motion_lid driver to use CONFIG_TABLET_MODE to
decide if device requires reporting of tablet mode. This basically
makes the config options CONFIG_LID_ANGLE_INVALID_CHECK and
CONFIG_LID_ANGLE_TABLET_MODE obsolete. Now that EC will always report
tablet mode aligned with Chrome (at 180 degree), any device that
supports tablet mode and uses motion lid driver will require this by
default and should not require boards to individually select any
special config options. Thus, it also gets rid of unused
CONFIG_LID_ANGLE_TABLET_MODE and CONFIG_LID_ANGLE_INVALID_CHECK.
BUG=b:120050761
BRANCH=octopus
TEST=make -j buildall
Change-Id: Ib73af66ca1c17d4033cf54f0b4b86bf41793f3a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1350470
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change performs the following renaming:
1. CONFIG_TABLET_SWITCH -> CONFIG_HALL_SENSOR
Indicates if a device has hall sensor
2. TABLET_MODE_GPIO_L -> HALL_SENSOR_GPIO_L
Provides the interrupt line from hall sensor to EC.
3. tablet_mode_isr -> hall_sensor_isr
Interrupt routine that gets control on hall sensor interrupt.
4. tablet_mode_init -> hall_sensor_init
Init routine for initializing hall sensor interrupt.
5. tablet_switch_disable -> hall_sensor_disable
Disable hall sensor interrupt and tablet mode sub-system.
This is done to separate hall sensor interrupt from tablet mode
handling. It is another step towards aligning tablet mode detection on
EC with Chrome. Hall sensor interrupt occurs when the lid is in
360-degree flipped mode. If tablet mode is not already triggered by
lid motion driver, then hall_sensor_isr will set tablet mode and take
necessary actions to disable input peripherals.
CQ-DEPEND=CL:1351518
BUG=b:120050761
BRANCH=octopus
TEST=make -j buildall
Change-Id: I5841f6875d538a624cb888bc048f252397ab457c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1350469
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This should be the last step to make all boards on ToT follow
go/usb-pd-slow-response-time. Theses boards all have the higher priority
tasks, but they aren't being used since the tcpc interrupt wasn't
scheduling calls on it.
BRANCH=none
BUG=b:112088135
TEST=builds
Change-Id: I2c39e661e804f88edd5b34636b93e6e63a5af57f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1283452
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Base on BMI160 location, the x axis is positive correlation
and the y, z axis negative correlation.
Correct the MB base reference direction.
BUG=b:118362153
BRANCH=ToT
TEST=Manual
1. Using EC console command "accelinfo on" the check the
Base Accel x, y, z value.
2. Run factory tool to verify.
Change-Id: I5c7968e9294b2fca511808d30aad3a99d524643f
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1307273
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to
the host to allow it to read the tablet mode flag from shared EC
memory and select the right DPTF table to load (if supported).
However, this config seems unnecessary because of the following
reasons:
1. Host sets SCI mask to indicate to the EC which events it wants to
process. Thus, even if the EC sets mode change flag, it will not be
notified to the host unless it supports mode change event.
2. Additionally, if host supports mode change event, but does not
support multiple DPTF tables, then EC ACPI code takes care of ensuring
that there is a thermal event handler present to reload tables.
3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86
boards.
BUG=b:117844490
BRANCH=None
TEST=make -j buildall
Change-Id: Ic4097ae047e2d559673a321da4df86514f902993
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1292359
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Per b:116180071 discussion, the V1.0A power rail should
keep at 1V during S0ix. This patch fixes the pmic setting
to avoid the potential stability issue.
BUG=b:116180071
BRANCH=master
TEST=Measure the V1.0A power rail during S0ix
Change-Id: Ic1d883d7d2427cdb2b8b871df17fbe701904e73e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1282550
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix ectool led command fail issue.
BUG=b:117631122
BRANCH=ToT
TEST=Manual
using ectool command to verify.
ectool led battery off => Check battery LED is off.
ectool led battery amber => Check battery LED is amber.
ectool led battery green => Check battery LED is green.
ectool led battery auto => Check battery LED is controlled by EC.
ectool led power off => Check power LED is off.
ectool led power white => Check power LED is white.
ectool led power auto => Check power LED is controlled by EC.
Change-Id: I9320f7a1880ff3949a90f66416520dfd56cde639
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1288177
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When battery full charge flag setting and battery discharge to 96%.
The battery LED will bright amber and system can't charge.
Modify CONFIG_BATTERY_LEVEL_NEAR_FULL from 97% to 94% to fix it.
BUG=b:117438684
BRANCH=ToT
TEST=Manual
1.Battery charge to full flag setting and remove AC.
2.Discharge the battery RSOC to 96% and plug-in AC.
3.Check battery LED is green.
4.Remove AC and discharge the battery RSOC to 93% and plug-in AC.
5.Check battery LED is amber and system is charge.
Change-Id: Ibd80304c109eb452bc5eba98fee3837a1611efb7
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1250583
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Modify PMIC and GPIO setting to fix power leakage.
Dependent on EE request:
1. Init PMIC Discharge control register.
1.1. Discharge control register 1 (0x3C) = 0x00.
1.2. Discharge control register 2 (0x3D) = 0x55.
1.3. Discharge control register 3 (0x3E) = 0x44.
1.4. Discharge control register 4 (0x3F) = 0x04.
2. Remove gpio "TP_INT_CONN" GPIO_PULL_UP configuration.
BUG=b:117194355
BRANCH=ToT
TEST=Manual
EE measure power and check it is improve.
Change-Id: I8b0e5ff479fee0ebcc26e9e57073ec6b5fc8868f
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1253369
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement the EC battery code.
BUG=b:111815315
BRANCH=ToT
TEST=Manual.
Check DC power on system.
Check battery can charging under AC mode.
Check battery discharging under DC mode.
Check battery cut off function.
Check battery XDSG/XCHG status
Change-Id: Ia9add6518948b30fbdb136f0b3c4104abd80a735
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1198903
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement keybaord backlight enable control
Enable keyboard backlight when system from S3 to S0.
Disable keyboard backlight when system from S0 to S3.
BUG=None
BRANCH=ToT
TEST=Manual.
When system power on, using console command kblight to check
keyboard backlight.
When system power off/suspend, check keyboard backlight.
Change-Id: I9a69664eb0cbd41c16cc90d3698c6375ddc02d9c
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1198944
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement power and charge LED function.
BUG=b:111815820
BRANCH=ToT
TEST=Manual.
Build and flash EC on rammus board.
Verify power LED behavior under power on/off/suspend.
Verify charge LED behavior under Battery full/charging/Error and DC only
Change-Id: I8bed644554c4dab853085613ddcc9e3d3417b9c2
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1198902
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Because the GPIO USB_PD_RST_C0_L is high active.
When USB_PD_RST_C0_L is high, the PD port 0 i2c communication will fail.
BUG=None
BRANCH=ToT
TEST=Manual.
Using consol command "i2cxfer r16 0 0x52 0x00" to read
TCPC port 0 VID is ok.
Change-Id: I998669f85770672478a4c9131f7b5a767ffd6773
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1198905
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We do not need to set the port_addr variable most places because the
SS-MUX is also the TCPC and the tcpc_config_t information is used
instead.
Remove unused variable setting to avoid confusion.
BRANCH=none
BUG=none
TEST=buildall. phaser USB-C communication (and muxs) still work which is
a nominal case for all of these changes.
Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200064
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To all boards that have space, add the PD tasks that handle interrupts
in parallel. This is the last change for go/usb-pd-slow-response-time.
BRANCH=none
BUG=b:112088135
TEST=buildall. This works on grunt and octopus. This CL is more of a
clean up for ToT to ensure that newly copied boards use the correct
paradigm.
Below is the space taken up by this change:
build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584)
build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160)
build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516)
build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800)
build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768)
build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164)
build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860)
build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064)
build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440)
build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444)
build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532)
build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416)
build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392)
build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912)
build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184)
build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680)
build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204)
build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740)
build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992)
build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088)
build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656)
build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248)
build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540)
build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960)
build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288)
build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988)
build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084)
build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512)
build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836)
build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300)
build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340)
build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800)
build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464)
build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772)
build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308)
build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580)
build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540)
build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264)
Compared 208 of 208 files.
38 files changed.
Total size change: -27484 bytes.
Average size change: -723 bytes.
Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1220667
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement touch pad enable control.
Enable touch pad when system from S5 to S3.
Disable touch pad when system form S3 to S5.
BUG=None
BRANCH=ToT
TEST=Manual.
Check touch pad can work under S0.
Check touch pad can wake up system under suspend.
Change-Id: Iccb06c3afeb458ea4504d4de971a49b1ab7bbe8d
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1198906
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Naming of many vector types and matrix types are not clear enough.
For example, we have:
vector_3_t, which is a vector of three int.
vec3_t, which is a vector of three float.
size4_t, which is a vector of four size_t.
mat33_t, which is a 3x3 matrix of float.
matrix_3x3_t, which is a 3x3 matrix of fixed point.
Besides, we have types like int8_t, uint16_t types.
To clearly distinguished types, the CL propose to,
For vector types, naming should be `$type + 'v' + $num + '_t'`:
vector_3_t becomes intv3_t
vec3_t becomes floatv3_t
vector 4 of uint16_t becomes uint16v4_t (which doesn't exist yet)
For matrix types, naming should be `mat$N$N_` + $type + '_t', where $N is the
matrix size:
matrix_3x3_t becomes mat33_fp_t # fp: fixed point
mat33_t becomes mat33_float_t
TEST=make buildall -j
BUG=b:114662791
Change-Id: I51d88d44252184e4b7b3564236833b0b892edc39
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1215449
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The board version is queried from the EEPROM. This patch adds
CONFIG_BOARD_VERSION_CBI to enable the board version query via host
command.
BUG=none
BRANCH=master
TEST='mosys platform version' returns the correct value
Change-Id: I87a591a00a4335031ee38eb3c0553f1be8c3b676
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1201222
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The dut keeps reboot due to the EC Assert. The problem is caused by
the changing of I2C_PORT_TCPC1 to NPCX_I2C_PORT0_0 (cl:1189663) and
the NPCX_I2C_PORT0_1 is removed from the i2c_ports[]. As a result,
when someone uses NPCX_I2C_PORT0_1, the assert popped out.
This patch changes the 'name' and 'port' of i2c_ports[] to avoid this
problem.
BUG=b:113715116
BRANCH=master
TEST=dut boot successfully
Change-Id: I90f7a1dcdec3ff2719f34786e9e57411b703562b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200662
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We are running out of RAM space for rammus and the UART buffer does
not need to be 4KB. 1KB is almost enough, so 2KB should be plenty. In
the long term chromium:826592 will allow us to use even smaller buffers.
BRANCH=none
BUG=chromium:826592,b:112088135
TEST=builds and links with child CL stack
Change-Id: I31bee3a8c5093e05dc5f27bcc99b8b19a8f022d5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200262
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Modify TCPC port 1 I2C bus to I2CC0_0 depend on hardware design.
BUG=b:113238132
BRANCH=ToT
TEST=verify
Insert TypeC to PD port 1 and check TCPC Init ready.
Using I2C command to check VID is ok.
Change-Id: I91c9d616e1809e272215f07e87431d3e0f5fa319
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1189663
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Rammus uses EEPROM to store the device info like sku id, board version.
This patch adds the cbi config for rammus.
BUG=b:111815817
BRANCH=master
TEST=ectool cbi set/get
Change-Id: I776de02b66b8545a2998635a974933fadd1e4d7a
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194547
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This adds support to configure dualrole setting
per port, so that servo v4 can adjust charge and
dut port separately.
servo will detect charge capability on CHG port
and choose source or sink as appropriate.
Fix null dereference bug in genvif duel to dynamic src_pdo.
"cc" command allows src, snk, srcdts, snkdts configurations.
BRANCH=None
BUG=b:72557427
TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub.
TEST=make buildall -j
Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096654
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
According to the proto schematics, revise the config
1. gpio.inc:
- Correct some pins assignment
- Remove unused pins
- Add TABLET_MODE_L, PP3300_USB_PD, EC_BRD_ID_EN,
LID_ACCEL_INT_L, TP_INT, TP_INT_EN
2. board.h:
- Remove unused options/code
- Add PWM related options/code to support kb light
- Add TABLET_SWITCH because of GMR support
- Add ANX3447 support
3. board.c:
- Remove unused code
- Add ANX3447 support
- Add temp sensor, ambient and eMMC
- Add PWM kb light
BUG=b:111579280
BRANCH=master
TEST=emerge-rammus chromeos-ec
Change-Id: Idbb1755f53c45018305a2724a14232a7cdab9acc
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1149772
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to
CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this
config option indicates that chipset sleep signals (SLP_S3 and SLP_S4)
are tranmitted over virtual wires instead of physical lines with eSPI.
BUG=b:111859300
BRANCH=None
TEST=make -j buildall
Change-Id: Iab4423abc9102164d4f43296a279c24355445341
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1151048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
The initial files are copied from nautilus and will be revised later.
BUG=b:111579280
BRANCH=master
TEST=emerge-rammus chromeos-ec
Change-Id: Ic1312716ca0b2200ec2d396f9e1e8c1bbe226904
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1149771
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|