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* Apollolake: Enter/exit from S0ix based on host commands from kernelArchana Patni2016-11-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the entry/exit model for S0ix from a PCH SLP_S0 signal based model to a hybrid host event/direct interrupt model. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. The assertion of SLP_S0 comes later than HC(suspend) and deasserion of SLP_S0 comes earlier than HC(resume). ________ ________ SLP_S0 |______________________| _____ ________ HC |___________________________| BRANCH=none BUG=chrome-os-partner:58740 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify idle state transitions during display off and periodic wakes from S0ix do not lead to state transitions in EC. Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/401072 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* reef/pyro/eve/snappy: source 3A on one portVincent Palatin2016-11-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add a new source policy to provide 3A if there is only one port used as a source. Also ensure that the load switch on VBUS when sourcing power is properly configured to limit the current to 1.5A or 3.0A depending on the case. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:56110 TEST=manual: connect the laptop to a type-C sink with Twinkie in between, without anything else connected on the laptop, see 3A flowing when measuring with Twinkie ('tw vbus'), plug a dangling C-to-A receptacle dongle on the other port and see 1.5A flowing through Twinkie. Force the input current limit on the sink to 3.0A and see the laptop cutting VBUS. Change-Id: Ic94ba186fc0648e770c8d13be0f96b23e968f855 Reviewed-on: https://chromium-review.googlesource.com/403851 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable high current on type-A ports by defaultstabilize-8992.BVijay Hiremath2016-11-151-1/+1
| | | | | | | | | | | | | BUG=chrome-os-partner:59309 BRANCH=none TEST=Able to draw 1.5A from Type-A ports Change-Id: I9c598f77a542650edf15f407ec4a10d0e7e7465e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/411345 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: enable tcpc low power modeKevin K Wong2016-11-111-7/+2
| | | | | | | | | | | BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890 BRANCH=none TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/399882 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: remove obsolete code for protoKevin K Wong2016-10-081-16/+1
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=booted reef evt Change-Id: I46aa5988a33b349007c3a21048f514b1720aacaf Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/394215 Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: Fix FAFT failure for firmware_ECUsbPortsDivya Sasidharan2016-09-231-1/+1
| | | | | | | | | | | | | | | | | Modify USB enable GPIO name to comply with FAFT test. It uses this name format USB%d_ENABLE to power on/off all the USB ports. BRANCH=none BUG=none TEST=on Reef FAFT test firmware_ECUsbPorts passes Change-Id: I9b3b5d1668acfca5505dcff6708800f409555040 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/386854 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* BD9995X: Rename common code of BD99955 and BD99956 as BD9995XVijay Hiremath2016-09-211-2/+2
| | | | | | | | | | | | | | | | | | Except the CHIP_ID and charger name code is common between BD99955 and BD99956. Hence renamed the code to BD9995X so that valid output is printed from console commands. BUG=chrome-os-partner:57519 BRANCH=none TEST=Manually tested on Reef. 'charger' console command prints charger name as 'bd99956' Change-Id: I3c995757941bcc5a6a8026dd807d76a7a47c9911 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/387119 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Prepare LID_OPEN GPIO for hibernationVijay Hiremath2016-09-111-1/+4
| | | | | | | | | | | | | | | | | | | LID_OPEN gpio is interrupt trigger on both the edge. If the system is hibernated when LID is open and then LID is closed, system wakes from hibernation. Hence setting the LID_OPEN GPIO as interrupt raising before hibernation so that system won't wake up upon LID close in hibernation. BUG=chrome-os-partner:57221 BRANCH=none TEST=Issued hibernate when LID is open, closed the LID after hibernation observed system won't boot back till LID is open again. Change-Id: Idc89c3d85b7d246c3e18d0ced48e7d47bebeafec Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/383753 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Update GPIOs for new schematicDavid Hendricks2016-09-091-8/+5
| | | | | | | | | | | | | | | | | | This makes minor changes to GPIOs for the next build: - USB_C0_PD_RST_L is actually push-pull in next build, so remove the comments about USB_C0_PD_RST_ODL. - Added TABLET_MODE - Make the net name for volume up/down buttons match the name in the schematic. BUG=none BRANCH=none TEST=built and booted on Reef EVT Change-Id: I0799de059d71809174e246b6bbd7f3a2fe25686a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/381791 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Minor corrections to GPIO listDavid Hendricks2016-09-021-3/+5
| | | | | | | | | | | | | | | | | This patch makes a few small changes to gpio.inc: - Correct NC1 assignment (GPIO00) - Add ENG_STRAP (GPIOB6) which is currently not connected to anything. - Cosmetic fix for LEDs (replace spaces with tabs for alignment) BUG=none BRANCH=none TEST=built and booted on Reef Change-Id: Ieca83be6c7423694d88f21ebfc3f57849bf42cde Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380449 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: Trigger interrupt on both the edges for volume button GPIOsVijay Hiremath2016-09-021-2/+2
| | | | | | | | | | | | | | | | | | Both press and release of the volume button has to be detected in order to process volume changes. Hence, trigger the interrupt on both the edges for volume button GPIOs. BUG=chrome-os-partner:56856 BRANCH=none TEST=Volume slider can slide when volume buttons are pressed. Change-Id: I0655f1c494d754904987cc2c76dcb3a39d5670ab Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/379621 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Add internal pull-up for TCPC1 INT# by default.Shamile Khan2016-08-171-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously this was only done when the board version is EVT or less and when daughter card is inserted. However board version can not be determined at this stage of power up since the function board_get_version() relies on reading Board ID ADC and ADCs have not yet been initialized. This pull up can be removed in future board versions in which the daughter card will always be in place and an internal pull-up will no longer be needed. BUG=chrome-os-partner:55488 chrome-os-partner:56039 BRANCH=none TEST=verify board has no watchdog reset when daughter baord is not connected. Also verify from EC log timestamps that there is no delay of approximately 1 second between "Inits done"and "KB init state" Change-Id: I68eff923dd795b7b2f23f88028ee14d1e845b401 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/370958 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* reef: make corrections to I2C GPIOs in gpio.incDavid Hendricks2016-08-171-9/+9
| | | | | | | | | | | | | | | | | There were a few things wrong with the way I2C pins were originally set up: - EC_I2C_SENSOR_SCL was moved from GPIOA0 to GPIO92. - EC_I2C_GYRO_SCL/SDA and EC_I2C_POWER_SCL/SDA were swapped. BUG=chrome-os-partner:53791 BRANCH=none TEST=Motion sensors work now. Change-Id: Id867c56b625da27e8ad82b503ae11173d7f855cc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/347754 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Martin Roth <martinroth@chromium.org>
* reef led: add battery led supportli feng2016-07-291-3/+3
| | | | | | | | | | | | | | | BUG=chrome-os-partner:55492 BRANCH=none TEST=on Reef proto, verified led behavior on battery charing, discharging cases Change-Id: Ibc134b741e5c433697b752f73bd3e29ba5910124 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/364025 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Update pins for EVTDavid Hendricks2016-07-291-3/+24
| | | | | | | | | | | | | | | | | | Updates for EVT: - TCPC0 interrupt polarity is now low, define GPIO_INT and set ANX74xx internal polarity control based on IS_PROTO. - Swapped pin assignments for USB_C1_PD_INT_ODL and EN_USB_C1_5V_OUT. - Rename USB_PD_RST_ODL to USB_C0_PD_RST_L and make it push-pull. - Add USB_C1_PD_RST_ODL BUG=chrome-os-partner:54958,chrome-os-partner:54952,chrome-os-partner:55165 BRANCH=none TEST=needs testing Change-Id: I075934cced532d656f942841c30e3640a6f42568 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358944 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* reef: Rejigger PROCHOT pinsDavid Hendricks2016-07-071-2/+6
| | | | | | | | | | | | | | Proto had two pins for PROCHOT# - One to monitor and one to override. Newer boards have only one pin that serves both purposes. BUG=chrome-os-partner:54953 BRANCH=none TEST=built and booted on reef Change-Id: Ida4bc2766caf15562c26e7a4b792a07604361da2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358940 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: correct GPIO name for PMIC_EN signal pinKevin K Wong2016-07-061-1/+1
| | | | | | | | | | | | | | | | | | | Rename from V5A_EN to PMIC_EN. The name V5A_EN came from Amenia where it controls both 5V_A-Rail and PMIC_EN. Reef has a separate 5V_A-Rail control (EN_PP5000) and an another GPIO pin for PMIC_EN. BUG=chrome-os-partner:53666 BRANCH=none TEST=buildall pass Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354767 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: Support DP alt mode of Type-C controllerli feng2016-06-271-5/+5
| | | | | | | | | | | | | | BUG=chrome-os-partner:54413,chrome-os-partner:54649 BRANCH=none TEST=none Change-Id: I32c969a97f84bf4e9953031c69008f8e598b7920 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/355604 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable external power interrupt GPIOVijay Hiremath2016-06-231-2/+1
| | | | | | | | | | | | | | | | | BUG=chrome-os-partner:54503 BRANCH=none TEST=Manually tested using console commands on both the ports. a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is 1 when AC connected & 0 when AC disconnected. b. Issued 'hibernate' & on plugging in the AC, device boots to S0. Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354721 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Add internal pull-up on LID_OPEN gpioFurquan Shaikh2016-06-101-1/+2
| | | | | | | | | | | | | | | | | | | | LID_OPEN gpio is present on the daughter card and provided by the EC. Add an internal pull-up on it for the cases when the daughter card isn't plugged in. This fix won't be required starting EVT. BUG=chrome-os-partner:54143, chrome-os-partner:53566 BRANCH=None TEST=Compiles successfully. "gpioget LID_OPEN" returns 1 without daughter card. Change-Id: Ieff281b489e4f3f8be184a55b7975fb2efcc1099 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/350460 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: Enable BC1.2 supportVijay Hiremath2016-06-081-1/+1
| | | | | | | | | | | | | | | BUG=chrome-os-partner:53688, chrome-os-partner:53721 BRANCH=none TEST=Type-C, DCP & SDP chargers can negotiate to desired current & voltage. Battery can charge. USB3.0 & USB2.0 sync devices are detected by the Kernel. Change-Id: I37890518c151ef94da2b2ade67a023f72d48fce6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/346784 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: Initialize EC_PCH_PWROK lowDavid Hendricks2016-06-071-1/+1
| | | | | | | | | | | | | | The PCH_PWROK signal has a pull-up on the PCH side, so we really want to drive this low. BUG=none BRANCH=none TEST=none Change-Id: Icb0702916671cfd632e67d036bfb865e968c102c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/350201 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Rename SMI/SCI GPIOs and enable CONFIG_SCI_GPIODavid Hendricks2016-06-061-2/+2
| | | | | | | | | | | | | | | This updates SMI/SCI-related config options on Reef so that SMIs and SCIs are generated correctly. BUG=chrome-os-partner:53726 BRANCH=none TEST=built and booted on Reef EC, firmware seemed more stable (stayed up longer), but still see watchdog timesouts in task 13. Change-Id: I6717f48a7655e49207fe34e6a166957eb34a05fd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/349711 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Don't set LPC pins in gpio.incDavid Hendricks2016-06-061-10/+12
| | | | | | | | | | | | | | | | The default mode for the LPC pins is actually LPC. Setting the altnerate function mode makes them GPIOs. BUG=none BRANCH=none TEST=build and booted on Reef EC. Didn't seem to make much of a difference on its own but with the follow-up things seemed more stable. Change-Id: Ibbc62d23d8d909be48a9bec90da8acebb9905b50 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/347443 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: keep analogix pd chip in resetAaron Durbin2016-05-241-1/+1
| | | | | | | | | | | | | | | | | The gpio settings for the USB_PD_RST_ODL signal had the default state high while the power enable, EN_USB_TCPC_PWR, was low. This is combination of settings is invalid for the part. Therefore, keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called to bring the pd chip online. BUG=chrome-os-partner:53035 BRANCH=None TEST=Rachel confirmed things still working. Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/347000 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: change USB_C0_PD_INT voltage toleranceAaron Durbin2016-05-241-1/+1
| | | | | | | | | | | | | | The USB_C0_PD_INT signal is actually at 3.3V levels. Don't mark the voltage sensitivity to 1.8V. BUG=chrome-os-partner:53035 BRANCH=None TEST=Rachel ran with resulting image. Nothing bad observed. Change-Id: I36bc3f911b715dc967cc8f23dfc70c3d0e5023d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/346734 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Initial commitDavid Hendricks2016-05-201-0/+152
This adds the basic framework for Reef including full GPIO listing, board config file, and rudimentary functionality. It has not been fully tested and still has several TODOs/FIXMEs. For now we just need something that will build and can be incrementally improved. BUG=chrome-os-partner:53035 BRANCH=none TEST=EC and AP both boot, seems reasonably stable for now Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339292 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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