| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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marked as MODULE_ADC
In the ADC initialization function, we should use the function
of gpio_config_module to set alternate function and declare
corresponding alternate function pins in gpio.inc. So we are
able to enable extra flag if needed.
BUG=none
BRANCH=none
TEST=testing the alternate function pins are normal
on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb
and reef_it8320.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because
that is the configuration option used to enable to use of the the GPIO
signal name thus defined. Remove the now unused
CONFIG_HOSTCMD_PLTRST_IS_VWIRE option.
BUG=b:139553375,b:143288478
TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite
BRANCH=none
Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to
CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this
config option indicates that chipset sleep signals (SLP_S3 and SLP_S4)
are tranmitted over virtual wires instead of physical lines with eSPI.
BUG=b:111859300
BRANCH=None
TEST=make -j buildall
Change-Id: Iab4423abc9102164d4f43296a279c24355445341
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1151048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Because H1 monitor tx/rx signals to detect servo board,
so we can't pull-up tx/rx or the DETECT_SERVO of H1 will
be always high even the servo board isn't connected.
BUG=none
BRANCH=none
TEST=H1 detect servo board correctly.
Change-Id: I2f2dfa220ed77478e6e622a0ed1189f559044aa3
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/897315
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add espi control module for it83xx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell.
2. console command "kbpress 1 4" to test keyboard data.
(board code for espi module test on CL:392587)
Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d
Reviewed-on: https://chromium-review.googlesource.com/394471
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This patch makes a few changes to gpio.inc.
- When pre-initialize GPIOs, set default level to low:
ENTERING_RW and USB2_OTG_VBUSSENSE.
- Disable internal pull-up (not necessary if
output type is push-pull):
USB_Cx_5V_EN.
- Set output type to open-drain:
EN_USB_Cx_3A and USB_C0_CCx_VCONN_EN.
The USB_C0_CCx_VCONN_EN is externally pulled up to PP3300_PD_A.
The EN_USB_Cx_3A is pulled to EN_USB_Cx_5V_OUT and connected
to base of BJT directly. The output current will be huge
if it is set as push-pull.
BRANCH=none
BUG=none
TEST=1. built and booted on reef_it8320.
2. plug-in a device on one port and add load current
on vbus to check if current limit sit at 3A.
Change-Id: I71fec59cd1696fff417d9cddc287e993988aea33
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/528034
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This change is based on reef's board code and modified for it8320.
BUG=none
BRANCH=none
TEST=Run the entire faft_ec suite and passed.
Change-Id: I8977d7431eb0a97ceb4ee1dfd11a2c4433687db0
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487792
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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copy board/reef and modified for 'pre-upload.py'.
BRANCH=none
BUG=none
TEST=build all.
Change-Id: I76618610f443c7d4bb1b7b507c71f3d74d639667
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/501607
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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