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* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board: it83xx based boards start to use CHIP_FAMILY and CHIP_VARIANTDino Li2018-07-021-0/+2
| | | | | | | | | | | | | With this patch, we can use them in code. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1116632 Reviewed-by: Jett Rink <jettrink@chromium.org>
* thermistor: move thermistor tables into common codeJett Rink2018-06-152-84/+17
| | | | | | | | | | | | | | | | | The exact same 2 lookup tables are in multiple board files. We seem to reuse the 2 thermistor circuit enough that we should single source them in a common location. BRANCH=none BUG=none TEST=yorp sensors still function properly Change-Id: Ic393c609c78c8a51c55a67b639c1fb9e6c387d8a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1100943 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Makefile.rules: Add buildalltests targetNicolas Boichat2018-05-261-0/+2
| | | | | | | | | | | | | | | | | In rare cases, it is useful to be able to build tests for all boards: buildall only builds the main image, but -paladin builders also builds test cases for each board. Also remove/fix tests for boards that currently fail. BRANCH=none BUG=b:35647963 TEST=make buildalltests -j, wait a long time, tests pass. Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072218 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc: convert LPC only boards to use CONFIG_HOSTCMD_LPCJett Rink2018-05-221-1/+1
| | | | | | | | | | | BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I4a70e10c34d79361ceada1ff40b8912b8a6fdaa7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067500 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* APL/GLK boards: Use chipset_pre_init_callbackFurquan Shaikh2018-04-191-2/+1
| | | | | | | | | | | | | | | | This change updates all APL/GLK boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I71ab0f1111e89a254db83fc58abfdfe8eacd3575 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018734 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: it83xx: pull pnpcfg_settings[] to the chip-levelDino Li2018-04-121-90/+0
| | | | | | | | | | | | | | | | | With this change, we don't need to declare pnpcfg_settings[] for each it83xx based board. BUG=b:76022972 BRANCH=none TEST=make buildall -j, boot to kernel on reef_it8320. Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1009544 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: it83xx: don't enable non-essential modules at defaultDino Li2018-03-291-6/+0
| | | | | | | | | | | | | We let board-level code to enable them if needed. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I9369e33ee1821125cf8719a0c3526afaf294da80 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/985346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-1/+1
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* reef_it8320: don't pull-up tx/rx of uartDino Li2018-02-021-1/+1
| | | | | | | | | | | | | | | Because H1 monitor tx/rx signals to detect servo board, so we can't pull-up tx/rx or the DETECT_SERVO of H1 will be always high even the servo board isn't connected. BUG=none BRANCH=none TEST=H1 detect servo board correctly. Change-Id: I2f2dfa220ed77478e6e622a0ed1189f559044aa3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/897315 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Removing unnecessary CONFIG_USB_PD_DISCHARGE defineJett Rink2018-02-011-1/+0
| | | | | | | | | | | | | | CONFIG_USB_PD_DISCHARGE is now defined automatically if you specify one of the specified options such as CONFIG_USB_PD_DISCHARGE_TCPC BRANCH=none BUG=none TEST=grunt still discharges using PPC Change-Id: I94086cfc58bebce9c62ad6aa52b7740b25276d89 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/894676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charger/isl923x: Implement charger_get_system_power from PSYSNicolas Boichat2018-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ISL923x, PSYS output is always enabled when the AP is on (provided CONFIG_CHARGER_PSYS is enabled). We add support for charger_get_system_power function, reading PSYS value, when CONFIG_CHARGER_PSYS_READ is defined. This will be used by the charging algorithm on lux. We also rename CONFIG_CMD_CHARGER_PSYS to CONFIG_CHARGER_PSYS_READ as CONFIG_CHARGER_PSYS_READ provides both "psys" console command and the new function. We also cleanup unneeded undefs in board files. Note that this does not implement the function on bd9995x, but this could be done without too much effort. BRANCH=none BUG=b:71520677 TEST=On lux, without AC connected, check that "psys" output roughly matches the output current from the battery. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: Ie1ce8e0ac103daacc5a08b8ccae604d1d83551b8 Reviewed-on: https://chromium-review.googlesource.com/848487 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: adc: add support ADC13-16Dino Li2017-12-121-3/+3
| | | | | | | | | | | | | IT8320 can support extra four ADC channels (ADC13-16). BRANCH=none BUG=none TEST=Run console command 'adc' and check the results. Change-Id: Ia9a259f54fa28d43dc0050c6e20885c0b3914f9c Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/808125 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* nds32: enable GCC LTODino Li2017-11-301-8/+1
| | | | | | | | | | | | | | | | | | | - We have more flash space to use with nds32 toolchain GCC6.3.0, so we enable a few console commands that were disabled previously. And we also enable LTO to reduce the size of FW image. - Put "__wait_evt" function into ram_code section to fill the gap of flash and improving performance of code-fetch. BUG=none BRANCH=none TEST=boot to kernel on reef_it8320. Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/788712 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chipset: Introduce CHIPSET_STATE_ANY_SUSPENDFurquan Shaikh2017-11-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | There are two different types of suspend states that are supported on x86 platforms -- S3 and S0ix. When AP enters S3, the chipset state is identified as CHIPSET_STATE_SUSPEND. On the other hand, when AP enters S0ix, the chipset state is identified as CHIPSET_STATE_STANDBY. There are several components within the EC e.g. charger state machine, usb pd task, motion sense task that take actions based on the chipset suspend state (and checked only for CHIPSET_STATE_SUSPEND until now). In order to ensure that different EC components do not have to worry about checking for all the different types of suspend states that are supported, introduce a new combination CHIPSET_STATE_ANY_SUSPEND which is a combination of CHIPSET_STATE_SUSPEND(S3) and CHIPSET_STATE_STANDBY(S0ix). BUG=b:69690699 BRANCH=None TEST=make -j buildall. Ruben verified that with this change, EC power consumption in S0ix drops from 7.85mW to 6.59mW on Soraka. Change-Id: I599a0ea2fe2f39132764a6068fa77c3aea02affa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/786919 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-172-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: add espi moduleDino Li2017-11-141-0/+2
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* bd9995x: Use fixed PD-port-to-VBUS/VCC mappingShawn Nematbakhsh2017-11-072-13/+4
| | | | | | | | | | | | | | | | | The bd9995x driver was written to allow any PD port # to be VBUS or VCC, but the mapping is broken in a few places. Since all boards use VBUS = port 0, remove the conversion entirely. BUG=chromium:781849 BRANCH=kevin TEST=Verify PD and BC1.2 charging still works on kevin. Change-Id: I3687866835d1684342d9f746d91b3a6079ab5cc4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/755000 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_manager: Enter safe mode at bootShawn Nematbakhsh2017-11-021-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | Charge port / current selection often needs to be significantly altered when a battery cannot provide sufficient charge, so have charge_manager initially enter safe mode. After a battery with sufficient capacity has been identified, charge manager will leave safe mode, and port / current selection will return to standard rules. BUG=chromium:777596 BRANCH=None TEST=Pass charge_manager unit tests. On kevin, remove battery, attach Apple PD charger, verify safe mode is not exited and device does not brown out. Hot-plug battery and verify safe mode is exited. Next, remove battery, attach to Samus, verify safe mode is not exited and device doesn't brown out. Hot-plug battery, verify that safe mode is exited and no active charge port, due to dual-role exclusion. Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733954 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chg_ramp: Add charge_is_consuming_full_input_current().Aseda Aboagye2017-11-011-10/+0
| | | | | | | | | | | | | | | | | | | Most boards had an identical implementation for this function, previously known as board_is_consuming_full_charge(). To reduce copy paste, let's just move it to common code. Boards that charge ramp without a battery will have to define their own implementation, but there probably won't be any boards like that in the near future. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ic99a378ac26dfd35d7d718bf9376eacfa8609166 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/748919 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* board: reef_it8320: disable CONFIG_CONSOLE_CMDHELP to save flash spaceDino Li2017-10-261-0/+1
| | | | | | | | | | | | | There isn't enough flash space, so we disable one more console command. BRANCH=none BUG=none TEST=build reef_it8320 and all. Change-Id: I4b6395322a6ab44476359316f16ac55d725bd2a8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/732816 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Remove ACCESSORY statesShawn Nematbakhsh2017-10-191-1/+0
| | | | | | | | | | | | | | | | | | | According to the USB-C spec, when a debug accessory is identified, we may optionally establish USB PD communication over CC. Some DTS partners (eg. servo_v4) expect us to speak PD, so let's make it so. There is no need for special ACCESSORY states, these do not exist in the PD spec. BRANCH=servo BUG=chromium:737755,b:65837068 TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify EC and cr50 consoles are available through servo_v4. Change-Id: I59d1ca50b4766509eccf38562cdf926578138585 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693294 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_ramp: Move ramp allowed / ilim callbacks to common codeShawn Nematbakhsh2017-10-062-24/+1
| | | | | | | | | | | | | | | | | | | | | The decision on whether to ramp (and how high) depends on the quirks of charger identification, so move the decision out of board, into the drivers that implement usb_charger. Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better contrast with the existing CONFIG_CHARGE_RAMP_HW. BUG=None TEST=Manual on kevin, verify ramp occurs when port plugged into Z840 workstation. BRANCH=None Change-Id: I5b395274133837a18a4f4ac34b59b623287be175 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/702681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Move *_set_input_current() to common codeShawn Nematbakhsh2017-10-051-24/+0
| | | | | | | | | | | | | | | | | | | Boards that use charge_manager have identical implementations of typec_set_input_current_limit() and pd_set_input_current_limit(), so move these functions to charge_manager. BUG=b:67413505 TEST=`make buildall -j`, also verify that fizz continues to power-on and boot AP, in both protected and unprotected mode, with barrel jack power and with zinger. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707 Reviewed-on: https://chromium-review.googlesource.com/701412 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exitFurquan Shaikh2017-10-031-1/+3
| | | | | | | | | | | | | | | | | | | Runtime S0ix results in SLP_S0 signal being toggled continuously resulting in an interrupt storm on the EC. In order to avoid this, enable SLP_S0 power signal only when host indicates intent to enter S0ix and disable when host exits from S0ix. BUG=b:65421825 BRANCH=None TEST=Verified that runtime S0ix no longer results in interrupt storm on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0 using powerindebug. Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add flags parameter to power_signal_infoFurquan Shaikh2017-10-031-9/+10
| | | | | | | | | | | | | | | | | | | | | | Replace structure member "level" in power_signal_info with "flags". "level" has been used on all boards to indicate active-high or active-low levels. Addition of "flags" allows easy extension of power_signal_info structure to define various flags that might be applicable to power signals (e.g. "level"). Going forward, additional flag will be added in follow-up CLs. Also, provide a helper function power_signal_is_asserted that checks the actual level of a signal and compares it to the flags level to identify if a power signal is asserted. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679979 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* board: reef_it8320: Report device orientation isn't tablet modeDino Li2017-09-282-0/+12
| | | | | | | | | | | | | | | We need to response EC ACPI device orientation command or keyboard/trackpad didn't work on OS image version R58 and after. BRANCH=none BUG=none TEST=keyboard and trackpad work on R58 and after. Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689715 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Remove support for debug accessories that provide VBUS + RdShawn Nematbakhsh2017-09-111-1/+0
| | | | | | | | | | | | | | | | | | | Reworked suzy-q and suzy-qable all provide Rp, so there is no need for special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS is no longer relevant, since we no longer take special action when VBUS is seen without Rp. BUG=chromium:737755 BRANCH=None TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5. Also, verify zinger works in S5 on reef. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec Reviewed-on: https://chromium-review.googlesource.com/656067 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Treat SYSTEM_IMAGE_RW_B also as RW copyDaisuke Nojiri2017-09-091-2/+1
| | | | | | | | | | | | | | SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy. This change makes EC treat it also as a RW copy. BUG=none BRANCH=none TEST=make buildall Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656337 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove duplicate BD9995X CONFIGsShawn Nematbakhsh2017-09-021-1/+1
| | | | | | | | | | | | | BUG=chromium:700933 BRANCH=None TEST=`make buildall -j` Change-Id: Id76fe93612fcd1ef924d7fa94479c45a52db046b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648566 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_port_power_smart: Add CDP/SDP only option.Aseda Aboagye2017-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | For some boards, the control lines to the charging port controller are all tied to a power rail. In essence, this leaves the ILIM_SEL as the only signal able to be controlled, which means that we only support CDP/SDP. This commit adds a new CONFIG_* option which describes this. CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY Additionally, some cleanup is made to not always assume the number of smart power ports. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/634274 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* battery: Check physical battery presence before inhibiting powerScott Collyer2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to satisfy factory testing requirements we need to boot a bare board with just an AC adapter without requiring a power button. However we also don't want to always allow booting of the battery is present but cut-off (which will indicate BP_NO so we can't use the existing battery_is_present function) or has critically low level as it may not immediately boot. To accomplish this add a function that allows the board to specify a custom "hardware presence" for the battery that is separate from the battery presence check. This CL is taking a change done for Eve and pulling into TOT so it can be used for other projects that have the same requirements. https://chromium-review.googlesource.com/c/582544 BUG=b:63957122 BRANCH=none TEST=manual Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627113 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* board: reef_it8320: disable CONFIG_CMD_I2C_XFER to save flash spaceDino Li2017-08-111-0/+1
| | | | | | | | | | | | | | There isn't enough flash space after 'repo sync', so disable one more console command. BRANCH=none BUG=none TEST=build reef_it8320 and all. Change-Id: I370e06d5de211b7de669f35071c680d28efb7c17 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/612001 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_mux: Merge PS8743 & PS8740 as PS874XVijay Hiremath2017-08-111-1/+1
| | | | | | | | | | | | | | | | | Merge PS8743 & PS8740 as PS874X as both the drivers are almost same. BUG=b:64598680 BRANCH=glkrvp TEST=make buildall -j On GLKRVP, verify mux setting is correct with Apple dongle (VGA + USB) and Pluggable adapter. Change-Id: Ic6d31979936ee213b07c4c71859809102ee91452 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/612209 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd_log: Make PD logging more generic for general purpose loggingShawn Nematbakhsh2017-08-021-1/+0
| | | | | | | | | | | | | | | | | | We can re-use our pd_log FIFO for other purposes, such as TPM logging. Carve out event_log, a generic logging module which pd_log is compatible with. BUG=b:63760920 TEST=On kevin, verify PD logging is still functional and entries are seen in dmesg. BRANCH=None Change-Id: I8e6ad6f93e9eebc676aca64652c60f81da471a94 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/597314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* S0ix: use both SLP_S0 interrupt and host command for s0ixJenny TC2017-07-243-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | EC currently uses a host command from kernel to enter s0ix. This patch waits for the SLP_S0 interrupt to come after receiving the host command before entering S0ix. On the exit path, the SLP_S0 interrupt directly triggers the exit rather than waiting for the host command. BRANCH=none BUG=b:37443151 TEST=check in EC logs for SLP_S0 entry and powerindebug output, check suspend_stress_test on reef and soraka works fine, make -j8 buildall runs fine Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2 Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/513705 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* driver: tcpm: ps8xxx: Add support for PS8805.Aseda Aboagye2017-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | This commit adds support for the PS8805, another Parade Tech TCPC with integrated superspeed muxes. This also creates a generic Parade Tech TCPC driver which supports the PS8xxx series. The current supported TCPCs are: - PS8751 - PS8805 BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I78383af414996e0e8d6220985d286f95267136f8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564799 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef_it8320: make modifications to GPIO listDino Li2017-06-101-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes a few changes to gpio.inc. - When pre-initialize GPIOs, set default level to low: ENTERING_RW and USB2_OTG_VBUSSENSE. - Disable internal pull-up (not necessary if output type is push-pull): USB_Cx_5V_EN. - Set output type to open-drain: EN_USB_Cx_3A and USB_C0_CCx_VCONN_EN. The USB_C0_CCx_VCONN_EN is externally pulled up to PP3300_PD_A. The EN_USB_Cx_3A is pulled to EN_USB_Cx_5V_OUT and connected to base of BJT directly. The output current will be huge if it is set as push-pull. BRANCH=none BUG=none TEST=1. built and booted on reef_it8320. 2. plug-in a device on one port and add load current on vbus to check if current limit sit at 3A. Change-Id: I71fec59cd1696fff417d9cddc287e993988aea33 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/528034 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: ec2i: move 'ec2i_setting' to header file of chipDino Li2017-05-181-44/+0
| | | | | | | | | | | | | | | This enum can be included in common. BUG=none BRANCH=none TEST=build boards: it83xx_evb and reef_it8320 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id7014b7de170cb3324c45d43fbf04ebe48a69f5e Reviewed-on: https://chromium-review.googlesource.com/505864 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* reef_it8320: initial reef_it8320 boardDino Li2017-05-188-904/+363
| | | | | | | | | | | | | | This change is based on reef's board code and modified for it8320. BUG=none BRANCH=none TEST=Run the entire faft_ec suite and passed. Change-Id: I8977d7431eb0a97ceb4ee1dfd11a2c4433687db0 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487792 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* board: reef_it8320: copy board/reefDino Li2017-05-178-0/+2997
copy board/reef and modified for 'pre-upload.py'. BRANCH=none BUG=none TEST=build all. Change-Id: I76618610f443c7d4bb1b7b507c71f3d74d639667 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/501607 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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