summaryrefslogtreecommitdiff
path: root/board/reef_it8320
Commit message (Collapse)AuthorAgeFilesLines
* usb_pd_policy: Make a lot of objects commonAseda Aboagye2019-12-101-314/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a board specific usb_pd_policy.c file that contains a lot of code for handling DisplayPort Alternate mode, Google Firmware Update Alternate mode, as well as some PD policy functions such as deciding to Accept or Reject a data role swap or a power role swap. Several boards simply copy/paste this code from project to project as a lot of this functionality is not actually board specific. This commit tries to refactor this by pulling the functions that are not mainly board specific into common code. The functions are made overridable such that boards that truly do require a different implementation may do so. Additionally, this consolidation changes the policy behaviour for some boards, but they should be for the better. Some examples include that data swaps are always allowed if we are a UFP (no system image requirement), power swaps are allowed to become a sink if we are no longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is not entered if the AP is off. In order to facilitate this refactor, a couple CONFIG_* options were introduced: - CONFIG_USB_PD_DP_HPD_GPIO /* HPD is sent to the GPU from the EC via a GPIO */ - CONFIG_USB_PD_CUSTOM_VDO /* * Define this if a board needs custom SNK and/or SRC PDOs. * * The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating * Dual-Role power, USB Communication Capable, and Dual-Role data. * * The default SNK PDOs are: * - Fixed 5V/500mA with the same PDO_FIXED_FLAGS * - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV, * operational current PD_MAX_CURRENT_MA, * - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power * PD_OPERATING_POWER_MW */ BUG=chromium:1021724,b:141458448 BRANCH=<as many as we can that are still supported> TEST=`make -j buildall` TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety of DP peripherals TEST=Repeat above with a nocturne TEST=Repeat above with an atlas Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-013-8/+9
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-311-1/+1
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* PCH_PLTRST_L: Use appropriate config optionAbe Levkoy2019-10-301-1/+1
| | | | | | | | | | | | | | | | | Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because that is the configuration option used to enable to use of the the GPIO signal name thus defined. Remove the now unused CONFIG_HOSTCMD_PLTRST_IS_VWIRE option. BUG=b:139553375,b:143288478 TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite BRANCH=none Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: Merge CONFIG_CHARGER_V2 into CONFIG_CHARGERKeith Short2019-09-181-1/+0
| | | | | | | | | | | | | | | | For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also defined. Remove references to CONFIG_CHARGER_V2 from board header files. Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when appropriate. BUG=b:139699769 BRANCH=none TEST=make buildall -j Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tglrvpu_ite: Adding VCONN supportAyushee2019-08-231-2/+2
| | | | | | | | | | | | | | | Added GPIOs pin config to support VCONN on tglrvp. Also added power switch function to enable/disable VCONN according to the cc lines. BRANCH=None BUG=b:139763031 TEST=Able to get characteristics of an E-marked cable Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591 Reviewed-by: Keith Short <keithshort@chromium.org>
* driver/tcpm/it83xx: Enable TCPC receive SOP'Ruibin Chang2019-08-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable TCPC receive SOP' for communication with cable, when we are Vconn source role. BUG=None BRANCH=None TEST=test on board: ampton and reef_it8320 1.SRC connects to SNK via E-mark cable, sources Vconn successfully, and receives cable's ack of discover id request. 2.SRC connects to SNK via E-mark cable, but not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 3.console cmd pdcable 0 2019-07-30 11:43:40 > pdcable 0 2019-07-30 11:43:45 Cable Type: Passive 2019-07-30 11:43:45 Connector Type: Type C 2019-07-30 11:43:45 Cable Current: 5A 2019-07-30 11:43:45 USB Superspeed Signaling support: Gen 1 Change-Id: Icd2e6f8481bb7a4e0b922460d46b831f36112738 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1728669 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-133-38/+1
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-14/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* dptf: Get rid of CONFIG_DPTF_DEVICE_ORIENTATIONFurquan Shaikh2018-10-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to the host to allow it to read the tablet mode flag from shared EC memory and select the right DPTF table to load (if supported). However, this config seems unnecessary because of the following reasons: 1. Host sets SCI mask to indicate to the EC which events it wants to process. Thus, even if the EC sets mode change flag, it will not be notified to the host unless it supports mode change event. 2. Additionally, if host supports mode change event, but does not support multiple DPTF tables, then EC ACPI code takes care of ensuring that there is a thermal event handler present to reload tables. 3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86 boards. BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ic4097ae047e2d559673a321da4df86514f902993 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1292359 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* tcpm: add TCPC RX circular buffer in ECJett Rink2018-09-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The alert line for TCPC will stay asserted as long as there are RX messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear all of the RX messages we know about during a single alert handling session. This CL can stand on its own, but it is a part of a CL stack that will tighten the critical section of time between received messages from the TCPC and sending follow up message out through the TCPC. See go/usb-pd-slow-response-time for more details. BRANCH=none BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761 BUG=b:113057273,b:112825261 TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to adversely affect state machine negotiation. Full CL stack consistently sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the 24 ms threshold we need to be under for USB PD spec compliance. Also testing pd_suspend scenario manually and EC was responsive after port 1 suspend because of "bad behavior" Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185727
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board: it83xx based boards start to use CHIP_FAMILY and CHIP_VARIANTDino Li2018-07-021-0/+2
| | | | | | | | | | | | | With this patch, we can use them in code. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1116632 Reviewed-by: Jett Rink <jettrink@chromium.org>
* thermistor: move thermistor tables into common codeJett Rink2018-06-152-84/+17
| | | | | | | | | | | | | | | | | The exact same 2 lookup tables are in multiple board files. We seem to reuse the 2 thermistor circuit enough that we should single source them in a common location. BRANCH=none BUG=none TEST=yorp sensors still function properly Change-Id: Ic393c609c78c8a51c55a67b639c1fb9e6c387d8a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1100943 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Makefile.rules: Add buildalltests targetNicolas Boichat2018-05-261-0/+2
| | | | | | | | | | | | | | | | | In rare cases, it is useful to be able to build tests for all boards: buildall only builds the main image, but -paladin builders also builds test cases for each board. Also remove/fix tests for boards that currently fail. BRANCH=none BUG=b:35647963 TEST=make buildalltests -j, wait a long time, tests pass. Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072218 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc: convert LPC only boards to use CONFIG_HOSTCMD_LPCJett Rink2018-05-221-1/+1
| | | | | | | | | | | BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I4a70e10c34d79361ceada1ff40b8912b8a6fdaa7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067500 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* APL/GLK boards: Use chipset_pre_init_callbackFurquan Shaikh2018-04-191-2/+1
| | | | | | | | | | | | | | | | This change updates all APL/GLK boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I71ab0f1111e89a254db83fc58abfdfe8eacd3575 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018734 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: it83xx: pull pnpcfg_settings[] to the chip-levelDino Li2018-04-121-90/+0
| | | | | | | | | | | | | | | | | With this change, we don't need to declare pnpcfg_settings[] for each it83xx based board. BUG=b:76022972 BRANCH=none TEST=make buildall -j, boot to kernel on reef_it8320. Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1009544 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-091-1/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: it83xx: don't enable non-essential modules at defaultDino Li2018-03-291-6/+0
| | | | | | | | | | | | | We let board-level code to enable them if needed. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I9369e33ee1821125cf8719a0c3526afaf294da80 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/985346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-1/+1
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* reef_it8320: don't pull-up tx/rx of uartDino Li2018-02-021-1/+1
| | | | | | | | | | | | | | | Because H1 monitor tx/rx signals to detect servo board, so we can't pull-up tx/rx or the DETECT_SERVO of H1 will be always high even the servo board isn't connected. BUG=none BRANCH=none TEST=H1 detect servo board correctly. Change-Id: I2f2dfa220ed77478e6e622a0ed1189f559044aa3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/897315 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Removing unnecessary CONFIG_USB_PD_DISCHARGE defineJett Rink2018-02-011-1/+0
| | | | | | | | | | | | | | CONFIG_USB_PD_DISCHARGE is now defined automatically if you specify one of the specified options such as CONFIG_USB_PD_DISCHARGE_TCPC BRANCH=none BUG=none TEST=grunt still discharges using PPC Change-Id: I94086cfc58bebce9c62ad6aa52b7740b25276d89 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/894676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charger/isl923x: Implement charger_get_system_power from PSYSNicolas Boichat2018-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ISL923x, PSYS output is always enabled when the AP is on (provided CONFIG_CHARGER_PSYS is enabled). We add support for charger_get_system_power function, reading PSYS value, when CONFIG_CHARGER_PSYS_READ is defined. This will be used by the charging algorithm on lux. We also rename CONFIG_CMD_CHARGER_PSYS to CONFIG_CHARGER_PSYS_READ as CONFIG_CHARGER_PSYS_READ provides both "psys" console command and the new function. We also cleanup unneeded undefs in board files. Note that this does not implement the function on bd9995x, but this could be done without too much effort. BRANCH=none BUG=b:71520677 TEST=On lux, without AC connected, check that "psys" output roughly matches the output current from the battery. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: Ie1ce8e0ac103daacc5a08b8ccae604d1d83551b8 Reviewed-on: https://chromium-review.googlesource.com/848487 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: adc: add support ADC13-16Dino Li2017-12-121-3/+3
| | | | | | | | | | | | | IT8320 can support extra four ADC channels (ADC13-16). BRANCH=none BUG=none TEST=Run console command 'adc' and check the results. Change-Id: Ia9a259f54fa28d43dc0050c6e20885c0b3914f9c Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/808125 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* nds32: enable GCC LTODino Li2017-11-301-8/+1
| | | | | | | | | | | | | | | | | | | - We have more flash space to use with nds32 toolchain GCC6.3.0, so we enable a few console commands that were disabled previously. And we also enable LTO to reduce the size of FW image. - Put "__wait_evt" function into ram_code section to fill the gap of flash and improving performance of code-fetch. BUG=none BRANCH=none TEST=boot to kernel on reef_it8320. Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/788712 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chipset: Introduce CHIPSET_STATE_ANY_SUSPENDFurquan Shaikh2017-11-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | There are two different types of suspend states that are supported on x86 platforms -- S3 and S0ix. When AP enters S3, the chipset state is identified as CHIPSET_STATE_SUSPEND. On the other hand, when AP enters S0ix, the chipset state is identified as CHIPSET_STATE_STANDBY. There are several components within the EC e.g. charger state machine, usb pd task, motion sense task that take actions based on the chipset suspend state (and checked only for CHIPSET_STATE_SUSPEND until now). In order to ensure that different EC components do not have to worry about checking for all the different types of suspend states that are supported, introduce a new combination CHIPSET_STATE_ANY_SUSPEND which is a combination of CHIPSET_STATE_SUSPEND(S3) and CHIPSET_STATE_STANDBY(S0ix). BUG=b:69690699 BRANCH=None TEST=make -j buildall. Ruben verified that with this change, EC power consumption in S0ix drops from 7.85mW to 6.59mW on Soraka. Change-Id: I599a0ea2fe2f39132764a6068fa77c3aea02affa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/786919 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-172-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: add espi moduleDino Li2017-11-141-0/+2
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* bd9995x: Use fixed PD-port-to-VBUS/VCC mappingShawn Nematbakhsh2017-11-072-13/+4
| | | | | | | | | | | | | | | | | The bd9995x driver was written to allow any PD port # to be VBUS or VCC, but the mapping is broken in a few places. Since all boards use VBUS = port 0, remove the conversion entirely. BUG=chromium:781849 BRANCH=kevin TEST=Verify PD and BC1.2 charging still works on kevin. Change-Id: I3687866835d1684342d9f746d91b3a6079ab5cc4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/755000 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_manager: Enter safe mode at bootShawn Nematbakhsh2017-11-021-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | Charge port / current selection often needs to be significantly altered when a battery cannot provide sufficient charge, so have charge_manager initially enter safe mode. After a battery with sufficient capacity has been identified, charge manager will leave safe mode, and port / current selection will return to standard rules. BUG=chromium:777596 BRANCH=None TEST=Pass charge_manager unit tests. On kevin, remove battery, attach Apple PD charger, verify safe mode is not exited and device does not brown out. Hot-plug battery and verify safe mode is exited. Next, remove battery, attach to Samus, verify safe mode is not exited and device doesn't brown out. Hot-plug battery, verify that safe mode is exited and no active charge port, due to dual-role exclusion. Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733954 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chg_ramp: Add charge_is_consuming_full_input_current().Aseda Aboagye2017-11-011-10/+0
| | | | | | | | | | | | | | | | | | | Most boards had an identical implementation for this function, previously known as board_is_consuming_full_charge(). To reduce copy paste, let's just move it to common code. Boards that charge ramp without a battery will have to define their own implementation, but there probably won't be any boards like that in the near future. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ic99a378ac26dfd35d7d718bf9376eacfa8609166 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/748919 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* board: reef_it8320: disable CONFIG_CONSOLE_CMDHELP to save flash spaceDino Li2017-10-261-0/+1
| | | | | | | | | | | | | There isn't enough flash space, so we disable one more console command. BRANCH=none BUG=none TEST=build reef_it8320 and all. Change-Id: I4b6395322a6ab44476359316f16ac55d725bd2a8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/732816 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Remove ACCESSORY statesShawn Nematbakhsh2017-10-191-1/+0
| | | | | | | | | | | | | | | | | | | According to the USB-C spec, when a debug accessory is identified, we may optionally establish USB PD communication over CC. Some DTS partners (eg. servo_v4) expect us to speak PD, so let's make it so. There is no need for special ACCESSORY states, these do not exist in the PD spec. BRANCH=servo BUG=chromium:737755,b:65837068 TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify EC and cr50 consoles are available through servo_v4. Change-Id: I59d1ca50b4766509eccf38562cdf926578138585 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693294 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_ramp: Move ramp allowed / ilim callbacks to common codeShawn Nematbakhsh2017-10-062-24/+1
| | | | | | | | | | | | | | | | | | | | | The decision on whether to ramp (and how high) depends on the quirks of charger identification, so move the decision out of board, into the drivers that implement usb_charger. Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better contrast with the existing CONFIG_CHARGE_RAMP_HW. BUG=None TEST=Manual on kevin, verify ramp occurs when port plugged into Z840 workstation. BRANCH=None Change-Id: I5b395274133837a18a4f4ac34b59b623287be175 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/702681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Move *_set_input_current() to common codeShawn Nematbakhsh2017-10-051-24/+0
| | | | | | | | | | | | | | | | | | | Boards that use charge_manager have identical implementations of typec_set_input_current_limit() and pd_set_input_current_limit(), so move these functions to charge_manager. BUG=b:67413505 TEST=`make buildall -j`, also verify that fizz continues to power-on and boot AP, in both protected and unprotected mode, with barrel jack power and with zinger. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707 Reviewed-on: https://chromium-review.googlesource.com/701412 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exitFurquan Shaikh2017-10-031-1/+3
| | | | | | | | | | | | | | | | | | | Runtime S0ix results in SLP_S0 signal being toggled continuously resulting in an interrupt storm on the EC. In order to avoid this, enable SLP_S0 power signal only when host indicates intent to enter S0ix and disable when host exits from S0ix. BUG=b:65421825 BRANCH=None TEST=Verified that runtime S0ix no longer results in interrupt storm on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0 using powerindebug. Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add flags parameter to power_signal_infoFurquan Shaikh2017-10-031-9/+10
| | | | | | | | | | | | | | | | | | | | | | Replace structure member "level" in power_signal_info with "flags". "level" has been used on all boards to indicate active-high or active-low levels. Addition of "flags" allows easy extension of power_signal_info structure to define various flags that might be applicable to power signals (e.g. "level"). Going forward, additional flag will be added in follow-up CLs. Also, provide a helper function power_signal_is_asserted that checks the actual level of a signal and compares it to the flags level to identify if a power signal is asserted. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679979 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* board: reef_it8320: Report device orientation isn't tablet modeDino Li2017-09-282-0/+12
| | | | | | | | | | | | | | | We need to response EC ACPI device orientation command or keyboard/trackpad didn't work on OS image version R58 and after. BRANCH=none BUG=none TEST=keyboard and trackpad work on R58 and after. Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689715 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Remove support for debug accessories that provide VBUS + RdShawn Nematbakhsh2017-09-111-1/+0
| | | | | | | | | | | | | | | | | | | Reworked suzy-q and suzy-qable all provide Rp, so there is no need for special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS is no longer relevant, since we no longer take special action when VBUS is seen without Rp. BUG=chromium:737755 BRANCH=None TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5. Also, verify zinger works in S5 on reef. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec Reviewed-on: https://chromium-review.googlesource.com/656067 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Treat SYSTEM_IMAGE_RW_B also as RW copyDaisuke Nojiri2017-09-091-2/+1
| | | | | | | | | | | | | | SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy. This change makes EC treat it also as a RW copy. BUG=none BRANCH=none TEST=make buildall Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656337 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove duplicate BD9995X CONFIGsShawn Nematbakhsh2017-09-021-1/+1
| | | | | | | | | | | | | BUG=chromium:700933 BRANCH=None TEST=`make buildall -j` Change-Id: Id76fe93612fcd1ef924d7fa94479c45a52db046b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648566 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_port_power_smart: Add CDP/SDP only option.Aseda Aboagye2017-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | For some boards, the control lines to the charging port controller are all tied to a power rail. In essence, this leaves the ILIM_SEL as the only signal able to be controlled, which means that we only support CDP/SDP. This commit adds a new CONFIG_* option which describes this. CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY Additionally, some cleanup is made to not always assume the number of smart power ports. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/634274 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* battery: Check physical battery presence before inhibiting powerScott Collyer2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to satisfy factory testing requirements we need to boot a bare board with just an AC adapter without requiring a power button. However we also don't want to always allow booting of the battery is present but cut-off (which will indicate BP_NO so we can't use the existing battery_is_present function) or has critically low level as it may not immediately boot. To accomplish this add a function that allows the board to specify a custom "hardware presence" for the battery that is separate from the battery presence check. This CL is taking a change done for Eve and pulling into TOT so it can be used for other projects that have the same requirements. https://chromium-review.googlesource.com/c/582544 BUG=b:63957122 BRANCH=none TEST=manual Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627113 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
View Lorry Controller Status