| Commit message (Collapse) | Author | Age | Files | Lines |
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There are 2 tablet mode triggers:
* Lid: when the lid angle close to 360 degree, either detected by
a GMR sensor or by the angle computed by 2 motion sensors.
* Base: when the detachable base is detached.
These 2 triggers set the tablet mode status, which as a boolean,
resulting a race condition.
This CL fixes the race condition. Each trigger updates its own bit. The
final tablet mode status is the OR of all bits.
BRANCH=Trogdor
BUG=b:193873098
TEST=Attached the base, checked tablet_mode enabled;
detached the base, checked tablet_mode disabled;
flip base to 360 degree, checked tablet_mode disabled;
move the base out of the lid, checked tablet_mode disabled.
Change-Id: Ia9d9d2d66c194796c1039cc8b746c8d1f28a4496
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044414
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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Currently keyboard_scan_config is defined by each board using
CONFIG_KEYBOARD_BOARD_CONFIG. This patch makes it defined as
__override hence removes CONFIG_KEYBOARD_BOARD_CONFIG.
BUG=None
BRANCH=None
TEST=buildall
Change-Id: I53a356741ba4d00e829ca59b74ee6dc704188728
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044403
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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Refactor system_get_board_version() a bit so that we can remove
CONFIG_BOARD_VERSION_CUSTOM and CONFIG_BOARD_VERSION from config.h.
BRANCH=None
BUG=b:186264627
TEST=make buildall -j
TEST=zmake testall
Cq-Depend: chromium:3015243
Change-Id: Id5ab809493c297b7d330ea13dcd6934ec00042a6
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004112
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Currently, power-on battery SoC and shutdown battery SoC are
independently configured by each board. This patch will unify the
setting as follows:
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%)
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%)
BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%)
CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed)
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1
This allows us to show the low battery alert whenever we can because
EC doesn't inhibit power-on even if it knows the host would
immediately shut down.
With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery
threshold (and the SoC will be agreed between the EC and Powerd).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the
same threshold. This is for avoiding degrading the UX by increasing
the power-on threshold (even though a question that 1% may not be
enough for soft sync to finish consistently remains to be answered).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a
lower threshold but we think 2% is enough to finish the software sync.
A lower threshold also improves the UX by showing the low battery
alert in the situation where otherwise the system would leave the user
uninformed by not responding to a power button press.
BUG=b:191837893
BRANCH=None
TEST=buildall
Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Move the "thermistor.h" header to the include/driver/temp_sensor
directory. It is used by the Zephyr shim, so the change is useful to
include the header.
BUG=b:180403276
BRANCH=none
TEST=make buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I0e83df97e50a3b324440b65ddb900ddf135f2439
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2843323
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Use board-specific override files when generating VIFs for boards.
BUG=b:172276715
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I197365018ceb8197c22d631cebf4cbce1c0119f7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785506
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Almost every relevant board copy-pastes 5000 us. Make that the default
and get rid of the redundant definitions. This is the approximate result
of this command:
find . -type f -name *.h | xargs sed -i -E \
'/#define CONFIG_USBC_VCONN_SWAP_DELAY_US[[:space:]]+5000[[:space:]]/d'
BUG=b:144165680
TEST=make buildall
BRANCH=none
Change-Id: Ife86f9752971abcd7ab5ad5a5e607eb2ccbde2ba
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628132
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This
is the approximate result of the following command, run from
platform/ec:
find . -type f -\( -name '*.c' -o -name '*.h' -\) | \
xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g'
Fix some latent formatting errors in usb_pd_protocol.c, because they
were preventing pre-upload hooks from passing.
BUG=b:144165680
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Now that the DPM will be handling source-out decisions for TCPMv2,
remove references to its old configuration options from TCPMv2 boards in
order to avoid any confusion as to what code is running now. Also
remove the charge manager notifications of sink attach/detach since the
policy is being centralized into the DPM.
Note that the previous configuration options only ever allocated one 3.0
A port, and so the default number of 3.0 A ports has been set to 1.
BRANCH=None
BUG=b:168862110,b:141690755
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ie452e3da32b04226503539daa67b6b9f4a58aa58
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597431
Reviewed-by: Keith Short <keithshort@chromium.org>
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Rename CONFIG_I2C_CONTROLLER and related comments.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The VCC is the power source of EC's GPM0~6, will connect to 1.8v or
3.3v depended on platform design.
This change was made to ensure voltage level setting of GPM0~6 matches
the corresponded VCC level. So we can enable internal pull-up no matter
VCC is connected to 1.8v or 3.3v
BUG=b:168783892
BRANCH=none
TEST=- buildall.
- The level setting is correct on these boards:
asurada, drawcia, and reef_it8320
Change-Id: I4eae368e569987381a0437494262d588436bb011
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2397931
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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For chip it8xxx2 series and it8320dx, we set embedded flash clock
48MHz as default.
BUG=none
BRANCH=none
TEST=build all
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I100d70fbf80430ae98fa14c557886c4a37d8b93a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355164
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Enable TCPMv2 on board it8xxx2_pdevb and reef_it8320.
BUG=none
BRANCH=none
TEST=TCPMv2 can run on board it8xxx2_pdevb and reef_it8320.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8bdfc2f2b0642bb406f360c6d0a3b1f1c637b5ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334433
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Enable PD in RO for TCPMv2 on board it8xxx2_pdevb and reef_it8320
(both are development board).
BUG=none
BRANCH=none
TEST=can run PD functions in RO image.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Ia2b61213366c0e38076ad5c52942928ad4bbc3b7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334432
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This is development board with EC it8320bx, we had given to
INTEL and GOOGLE. Now most of the development board, we re-work
EC to it8320dx that is mass production version and flash size is
enough to define CONFIG_SYSTEM_UNLOCKED, so I update chip variant
to dx version, but this may not suit for those bx board.
BUG=none
BRANCH=none
TEST=can boot on board reef_it8320
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I1f36ee15ffc515243863f73afb30a958613985ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340729
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Enable flash clock 48Mhz, so the test environment same as
project ampton and waddledee.
BUG=none
BRANCH=none
TEST=can boot and PD functions work.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8ac3ebef79a4ced9d963e4841c3304f4bd2c96e6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334437
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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On board reef_it8320, it doesn't support chromeos vivaldi
keyboard function, so undefine the configuration.
BUG=none
BRANCH=none
TEST=Top function keys are working now.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: If3899b64a028272f997703a6fe5c2beb09813d42
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334436
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Larger stack size on board it8xxx2_pdevb and reef_it8320.
BUG=none
BRANCH=none
TEST=can boot on board it81202_pdevb and reef_it8320
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Iaee6ce48399dde5adddce5894474a1152b5f9453
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334434
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Different DB options may cause different numbers of charger chips to be
present on the system. Remove constant count for charger chips, and
instead always call into the overridable function to query the count.
BRANCH=None
BUG=b:155963446
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I0e65b8af351ecabe6f7b823e0e56f1932cc280a6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2277833
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This command is unrelated to the PDCMD task and can be safely pulled
into the common PD host command code. After this commit, most boards
using the PD_INT tasks may safely remove the PDCMD task from their
boards.
BRANCH=None
BUG=b:154959596
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I2915acd5398a5dc7da2e6daff1e213fc8dfbadc8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2208220
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I33a63d6ac45bbd46da74db34a21d1bb130476362
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2196946
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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marked as MODULE_ADC
In the ADC initialization function, we should use the function
of gpio_config_module to set alternate function and declare
corresponding alternate function pins in gpio.inc. So we are
able to enable extra flag if needed.
BUG=none
BRANCH=none
TEST=testing the alternate function pins are normal
on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb
and reef_it8320.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Split ps874x.[ch] into ps8740.[ch] and ps8743.[ch]
since we need to support both at runtime for Dalboz.
I left PS8742 in ps8740.[ch] since it is not very different.
BUG=b:153454399
BRANCH=none
TEST=make -j buildall
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: I92b02e08f377d1781c130a0bbe1482a936ad7a4d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2151647
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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To prevent cc pins leakage and cc pins can be used as gpio.
We will check if the chip supported tcpc physical port count is
more than board active ITE port count. If yes, we will disable
unused cc port module.
BUG=none
BRANCH=none
TEST=1) on board it8xxx2_pdevb with chip it81202, check the pd
port connection with adapter and dongle when hibernate
and resume.
adapter: connect
dongle: disconnect then re-connect
2) on board it83xx_evb with chip it8320, set cc pins as
gpio, check output level when hibernate and resume.
Change-Id: I13511741b2e066dd87277db9f71f2b4a9323ad6d
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994693
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This makes retimers appear as generic muxes. By allowing a
chain of muxes they can be stacked up to the new configurations
that zork requires and will continue to work as they did before
on configurations that only have a single mux.
The code used to have two different arrays, 1) muxes and 2)
retimers. On one of the zork configurations the processor
MUX stopped being the primary mux and the retimer took its
place. In a different configuration of that same platform
it left the primary and secondary alone but the mux_set
FLIP operation had to be ignored. Since the same
interfaces needed to be available for both it stopped making
sense to have two different structures and two different
methods of handling them. This consolodates the two into
one.
The platforms that do not have retimers, this change will
not make any difference. For platforms like zork, it will
remove the retimers and make them chained muxes. So
testing on trembyle makes sense to verify,
BUG=b:147593660
BRANCH=none
TEST=verify USB still works on trembyle
Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794
Commit-Queue: Jett Rink <jettrink@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The current use of the PD Config Flags are a bit confusing and
has been changed to the following:
The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable
the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY
is enabled, one of the following must be enabled:
CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine
CONFIG_USB_PD_TCPMV2 - current power delivery state machine
BUG=b:149993808
BRANCH=none
TEST=make -j buildall
Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238
Signed-off-by: Sam Hurst <shurst@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Add PD driver for chip it8xxx1/8xxx2 series.
BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
(set cc toggle by console cmd):
1.pin configuration
console cmd "gpioget" check gpio settings.
memory dump check cc pin alternate settings.
2.Tx data error handle
Message discard, No GoodCRC, Tx not enable, Timeout
errors happen, corresponding INT will be triggered
then do properly handle.
3.basic pd connection
SNK:connect with adaptor, request max power (15V,3A),
state SNK_READY.
SRC:enable DRP role,
connect with dongle, provide power (5V,1.5A),
source Vconn 5v, get ack of cable discover id,
state SRC_READY.
4.pd module disable
SNK:connect with adapter.
console cmd "hibernate sec", driver disable pd module,
check still connection with adapter via dead battery rd.
And when resume from hibernate, pd init can re-enable
pd module, re-connect with adapter.
SRC:connect with dongle.
console cmd "hibernate sec", driver disable pd module,
check cc pin (not Vconn source pin) volt power down
to ~0v. And when resume from hibernate, pd init can
re-enable pd module, re-connect with dongle.
5.Tx hard reset
console cmd "pd port hard", check hard reset message by
lecroy analyzer.
6.Tx cable reset
check cable reset message by lecroy analyzer.
7.SOP' enable
SRC:connects to SNK via E-mark cable.
Source Vconn successfully, and receives cable's ack
of discover id request.
Not source Vconn to cable, and receives nothing
of discover id request (this isn't effect on
request SNK flow).
8.power role swap
console cmd "pd port swap power", check pd protocol
by lecroy.
Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The action_delay_sec field hasn't actually been referenced by
any code since 2013. Removing the corresponding struct field.
BUG=None
BRANCH=None
TEST=builds
Change-Id: Ia7334c26b85d0161ff61bb51fbdda61bb921595a
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054945
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This commit removes the temporary common charger chip configuration and
instead puts the configuration in each board.
BRANCH=none
BUG=b:147672225
TEST=builds, runs on waddledoo and octopus
Change-Id: If81aef31e48c65999a87e202494f286716114bbb
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The other driver structure members return an ec_error_list value and
fill in parameters to return data. This commit changes the
get_vbus_voltage call to follow that model.
BRANCH=None
BUG=b:147672225
TEST=builds
Change-Id: I7308502a9734274dd308b830762493c4d70d147a
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015340
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The PI3USB3X532 driver in the EC assumes that all superspeed muxes are
on the same i2c bus, I2C_PORT_USB_MUX. However, that may not be true
for some boards. This commit utilizes the MUX_PORT(...) macro to
determine the i2c port to use from the usb_mux table. The boards that
use this driver have been updated to pack the i2c port in the port_addr
member. There should be no functional changes to those boards.
BUG=b:147689445
BRANCH=None
TEST=`make -j buildall`
Change-Id: If6460b84a5e39610d658f06a42ca1db0bd4da048
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013658
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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The Pericom PI3USB30532 usb mux driver will actually also work for the
PI3USB31532. This commit renames the driver to reflect this while also
adding the PI3USB31532 to the list of supported USB muxes.
BUG=b:146654043
BRANCH=None
TEST=`make -j buildall`
Change-Id: Ic8e2852a3e038b05eb18d1d9db210b7fdce957d7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1990362
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
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There is a board specific usb_pd_policy.c file that contains a lot of
code for handling DisplayPort Alternate mode, Google Firmware Update
Alternate mode, as well as some PD policy functions such as deciding to
Accept or Reject a data role swap or a power role swap. Several boards
simply copy/paste this code from project to project as a lot of this
functionality is not actually board specific.
This commit tries to refactor this by pulling the functions that are not
mainly board specific into common code. The functions are made
overridable such that boards that truly do require a different
implementation may do so.
Additionally, this consolidation changes the policy behaviour for some
boards, but they should be for the better. Some examples include that
data swaps are always allowed if we are a UFP (no system image
requirement), power swaps are allowed to become a sink if we are no
longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is
not entered if the AP is off.
In order to facilitate this refactor, a couple CONFIG_* options were
introduced:
- CONFIG_USB_PD_DP_HPD_GPIO
/* HPD is sent to the GPU from the EC via a GPIO */
- CONFIG_USB_PD_CUSTOM_VDO
/*
* Define this if a board needs custom SNK and/or SRC PDOs.
*
* The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating
* Dual-Role power, USB Communication Capable, and Dual-Role data.
*
* The default SNK PDOs are:
* - Fixed 5V/500mA with the same PDO_FIXED_FLAGS
* - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV,
* operational current PD_MAX_CURRENT_MA,
* - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power
* PD_OPERATING_POWER_MW
*/
BUG=chromium:1021724,b:141458448
BRANCH=<as many as we can that are still supported>
TEST=`make -j buildall`
TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety
of DP peripherals
TEST=Repeat above with a nocturne
TEST=Repeat above with an atlas
Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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this changes the declaration and definitions of
typec_set_source_current_limit() to take an enum tcpc_rp_value instead
of int.
BRANCH=none
BUG=none
TEST=buildall passes
Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because
that is the configuration option used to enable to use of the the GPIO
signal name thus defined. Remove the now unused
CONFIG_HOSTCMD_PLTRST_IS_VWIRE option.
BUG=b:139553375,b:143288478
TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite
BRANCH=none
Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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If the host command handler callback function returns an int, it's easy
to accidentally mix up the enum ec_error_list and enum ec_status types.
The host commands always expect an enum ec_status type, so we change the
return value to be of that explicit type. Compilation will then fail if
you accidentally try to return an enum ec_error_list value.
Ran the following commands and then manually fixed up a few remaining
instances that were not caught:
git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\
xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\
static enum ec_status \1(struct host_cmd_handler_args \*args)##'
git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\
xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\
enum ec_status \1(struct host_cmd_handler_args \*args)##'
BRANCH=none
BUG=chromium:1004831
TEST=make buildall -j
Cq-Depend: chrome-internal:1872675
Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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For all boards that defined CONFIG_CHARGER, CONFIG_CHARGER_V2 is also
defined. Remove references to CONFIG_CHARGER_V2 from board header files.
Replace CONFIG_CHARGER_V2 in common C modules with CONFIG_CHARGER when
appropriate.
BUG=b:139699769
BRANCH=none
TEST=make buildall -j
Change-Id: I6b54baf4ad2406bbed629b6b272dad9ea6a81280
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1789420
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Added GPIOs pin config to support VCONN on tglrvp. Also added
power switch function to enable/disable VCONN according to the
cc lines.
BRANCH=None
BUG=b:139763031
TEST=Able to get characteristics of an E-marked cable
Change-Id: Ib09307aafe68ea955f256d3f35670579072c3040
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1762591
Reviewed-by: Keith Short <keithshort@chromium.org>
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Enable TCPC receive SOP' for communication with cable, when
we are Vconn source role.
BUG=None
BRANCH=None
TEST=test on board: ampton and reef_it8320
1.SRC connects to SNK via E-mark cable, sources Vconn successfully,
and receives cable's ack of discover id request.
2.SRC connects to SNK via E-mark cable, but not source Vconn to
cable, and receives nothing of discover id request
(this isn't effect on request SNK flow).
3.console cmd pdcable 0
2019-07-30 11:43:40 > pdcable 0
2019-07-30 11:43:45 Cable Type: Passive
2019-07-30 11:43:45 Connector Type: Type C
2019-07-30 11:43:45 Cable Current: 5A
2019-07-30 11:43:45 USB Superspeed Signaling support: Gen 1
Change-Id: Icd2e6f8481bb7a4e0b922460d46b831f36112738
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1728669
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an
embedded TCPC.
This patch adds bus_type field to struct tcpc_config_t so that a TCPC
location on other type of bus can be specified.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b
Reviewed-on: https://chromium-review.googlesource.com/1640305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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It's simply a bad idea to describe a macro in multiple locations.
It'll make it hard to change. It'll be difficult to keep all
locations in sync.
This patch replaces the comment duplicated in all ec.tasklist with
a pointer to the CONFIG_TASK_LIST definition. The macro will be
described in a single place (just like all/most other macros).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313
Reviewed-on: https://chromium-review.googlesource.com/1551579
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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CONFIG_DPTF_DEVICE_ORIENTATION was added to indicate mode change to
the host to allow it to read the tablet mode flag from shared EC
memory and select the right DPTF table to load (if supported).
However, this config seems unnecessary because of the following
reasons:
1. Host sets SCI mask to indicate to the EC which events it wants to
process. Thus, even if the EC sets mode change flag, it will not be
notified to the host unless it supports mode change event.
2. Additionally, if host supports mode change event, but does not
support multiple DPTF tables, then EC ACPI code takes care of ensuring
that there is a thermal event handler present to reload tables.
3. CONFIG_DPTF_DEVICE_ORIENTATION was defined for almost all new x86
boards.
BUG=b:117844490
BRANCH=None
TEST=make -j buildall
Change-Id: Ic4097ae047e2d559673a321da4df86514f902993
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1292359
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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The alert line for TCPC will stay asserted as long as there are RX
messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear
all of the RX messages we know about during a single alert handling
session.
This CL can stand on its own, but it is a part of a CL stack that will
tighten the critical section of time between received messages from the
TCPC and sending follow up message out through the TCPC.
See go/usb-pd-slow-response-time for more details.
BRANCH=none
BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761
BUG=b:113057273,b:112825261
TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to
adversely affect state machine negotiation. Full CL stack consistently
sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the
24 ms threshold we need to be under for USB PD spec compliance.
Also testing pd_suspend scenario manually and EC was responsive after
port 1 suspend because of "bad behavior"
Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185727
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This adds support to configure dualrole setting
per port, so that servo v4 can adjust charge and
dut port separately.
servo will detect charge capability on CHG port
and choose source or sink as appropriate.
Fix null dereference bug in genvif duel to dynamic src_pdo.
"cc" command allows src, snk, srcdts, snkdts configurations.
BRANCH=None
BUG=b:72557427
TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub.
TEST=make buildall -j
Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096654
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS
This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to
CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this
config option indicates that chipset sleep signals (SLP_S3 and SLP_S4)
are tranmitted over virtual wires instead of physical lines with eSPI.
BUG=b:111859300
BRANCH=None
TEST=make -j buildall
Change-Id: Iab4423abc9102164d4f43296a279c24355445341
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1151048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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With this patch, we can use them in code.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Id9646ef82f26bcb6bf55f2ce33a4647b5934c365
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1116632
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The exact same 2 lookup tables are in multiple board files. We seem to
reuse the 2 thermistor circuit enough that we should single source them
in a common location.
BRANCH=none
BUG=none
TEST=yorp sensors still function properly
Change-Id: Ic393c609c78c8a51c55a67b639c1fb9e6c387d8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1100943
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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