summaryrefslogtreecommitdiff
path: root/board/snoball
Commit message (Collapse)AuthorAgeFilesLines
* snoball: GPIO changes for proto 1Shawn Nematbakhsh2016-04-253-152/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:52690 BRANCH=None TEST=`make buildall -j` Change-Id: I787e8bc2fb5ca04a0879eeec7a8d7169e36b7661 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340445 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* snoball: Add support for proto 0.9 boardShawn Nematbakhsh2016-04-195-161/+78
| | | | | | | | | | | | | | | | This board uses a different stm32f0 MCU and has significant architectural changes. BUG=chrome-os-partner:50549 BRANCH=None TEST=`make buildall -j`, verify snoball boots to console Change-Id: I842a3efc5e179b33bbf0441e8d4ea07fa006e3fe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329439 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpm: update code to support multiple tcpm driverKevin K Wong2016-04-171-3/+3
| | | | | | | | | | | BUG=chromium:593822 BRANCH=none TEST=make buildall Change-Id: Ic30c1b890da7639aa80a53040ecc5bebfb4be2e8 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336030 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Add config to disable PD communication in locked ROShawn Nematbakhsh2016-04-111-1/+0
| | | | | | | | | | | | | | | | | | | | The scheme to disable PD communication in locked RO needs to be implemented on other platforms, so move it to common code, behind CONFIG_USB_PD_COMM_LOCKED. BUG=chrome-os-partner:52157 BRANCH=glados TEST=Manual on chell. Lock system and boot to recovery, then verify PD communication is functional. Enable CONFIG_USB_PD_COMM_LOCKED and verify PD communication isn't functional under the same test conditions. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I8d1f24c0b60cf1c54e329af003b7083ee55ffc40 Reviewed-on: https://chromium-review.googlesource.com/338064 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cleanup: Add warning comment to gpio.inc filesBill Richardson2016-02-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | With commit e9883124ff16, a GPIO_INT macro was added. That change also required that all instances of GPIO_INT in a board's gpio.inc file come before any GPIO macros, or the interrupt handler wouldn't work properly. This CL just adds a warning comment about requirement to all gpio.inc files. BUG=chromium:471331 BRANCH=none TEST=make buildall, test image on Cr50 This is a change to comments only. There is no new behavior to verify, although I did run try out one new image just to be sure nothing stupid happened. Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329334 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: Don't use HSI48 clock for chips which don't support itShawn Nematbakhsh2015-12-111-1/+1
| | | | | | | | | | | | | | | | | | stm32f03x and stm32f070 officially do not support an HSI48 clock, so configure our 48MHz clock using HSI8 and PLL. BUG=chromium:568717 BRANCH=None TEST=Verify snoball 1us timer is accurate and we can execute approximately 48 million NOPs in a second. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347 Reviewed-on: https://chromium-review.googlesource.com/317459 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* snoball: Enable PWMs for post-regulator voltage controlShawn Nematbakhsh2015-12-043-8/+32
| | | | | | | | | | | | | | | BUG=chrome-os-partner:48044 TEST=Manual with snoball w/ subsequent commit. Run `pwm <ch> 50` for each channel, verify with `adc` that each PD output voltage is approximately VBUCK / 2. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0c791fa4de47f92423c4cfd6ef5013495f5a5019 Reviewed-on: https://chromium-review.googlesource.com/315142 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: Add support for multiple distinct TCPC alert signalsShawn Nematbakhsh2015-11-252-2/+14
| | | | | | | | | | | | | | | | | | | | | If multiple TCPCs are present on a system then we may have multiple alert signals, each of which alerts us to the status of a different TCPC. Make boards with external non cros-ec TCPCs define tcpc_get_alert_status, which returns alert status based upon any alert GPIOs present, and then service only ports which are alerting. BUG=chromium:551683,chrome-os-partner:47851 TEST=Verify snoball PDCMD task sleeps appropriately when no devices are inserted, and verify ports go to PD_DISCOVERY state when we attach samus. Also verify that glados / glados_pd can still negotiate PD. BRANCH=None Change-Id: Iae6c4e1ef4d6685cb5bf7feef713505925a07c8c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313209 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* snoball: Enable secondary bias regulatorShawn Nematbakhsh2015-11-231-1/+1
| | | | | | | | | | | | | | | | | This regulator must be enabled in order to power snoball through the VBUS path. BUG=chrome-os-partner:47851 BRANCH=None TEST=Boot snoball with 12V supply on VBUS, verify that EC is stable and not resetting constantly. Change-Id: Id1b79b69f641e0c80160b161fe177aeb9c3de733 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313811 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* snoball: Correct DMA UART channelsShawn Nematbakhsh2015-11-191-0/+3
| | | | | | | | | | | | | | | | Snoball uses DMA2 + DMA3 for UART1 debug console. No changes are needed to STM32_SYSCFG_CFGR1 since this is the register default config. BUG=chrome-os-partner:47851 BRANCH=None TEST=Boot snoball, verify EC console works in both directions. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id984b63f8c0c2d5c042265fd86b3d0c71fd68e6f Reviewed-on: https://chromium-review.googlesource.com/313168 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* snoball: Use TIM1 for LSB system clockShawn Nematbakhsh2015-11-191-2/+2
| | | | | | | | | | | | | | | | | TIM14 can't be used in our existing master / slave system clock config due to lacking master mode control / TRGO. BUG=chrome-os-partner:47851 TEST=Manual on snobal. Verify that timer interrupts function, HOOK_SECOND hooks are called and watchdog doesn't fire. BRANCH=None Change-Id: I659b3cc46cf350fc58d88853fcc3d436b5f37d52 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313189 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* fusb302: Move i2c slave address defines to common headerShawn Nematbakhsh2015-11-171-2/+1
| | | | | | | | | | | | | BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: I51000b3ad32ebef8d19a685b8adbbbe2a42301f5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312797 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* snoball: Initial board commitShawn Nematbakhsh2015-11-177-0/+414
BUG=chrome-os-partner:47522 BRANCH=None TEST=Compile only Change-Id: I588733c0f34239a2b3eb36a8810ccfddd8ee98ca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312250 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
View Lorry Controller Status