| Commit message (Collapse) | Author | Age | Files | Lines |
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For most tests, we don't need to power the AP. Let's exclude chipset
task to save memory space.
BUG=chrome-os-partner:18598
TEST=Run pingpong test on Spring
BRANCH=none
Change-Id: I545c5b3e1c27b0067d4ffe09a7971d32b75d6039
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47833
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This changes current TASK() syntax to TASK_BASE() and TASK_NORMAL(),
where TASK_BASE is necessary for the EC to boot on a board and
TASK_NORMAL represents the task that can be removed in a test binary.
Tasks introduced by a test should be listed as TASK_TEST().
Note that this CL breaks current tests (many of them are broken anyway),
which will be fixed in up coming CLs.
BUG=chrome-os-partner:18598
TEST=Build link/bds/spring/snow/daisy/mccroskey. (mccroskey failed for
unrelated issue)
BRANCH=none
Change-Id: Ic645cdae0906ed21dc473553f1f43c2537ec4bb9
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47531
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This makes the charging task name consistent across platform.
No functional changes, just renaming.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all EC boards
Change-Id: I348b31313f6604df2a05b474bdf6e0be7450c8c9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/46891
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Rename tasks
TICK -> HOOKS
The hooks task handles more than just the TICK hook now.
X86POWER -> CHIPSET
GAIAPOWER -> CHIPSET
Kinda kludgy that the name of the task controls which chipset source gets
included. Change this to a CONFIG_CHIPSET_{X86,GAIA} #define to make it
easier to support future chipsets. Also, rename the task function to
chipset_task() so ec.tasklist is chipset-agnostic.
No code changes, just renaming constants and functions.
BUG=none
BRANCH=none
TEST=build bds,link,daisy,snow,spring
Change-Id: I163ce1cd27b2d8d030d42bb1f7eb46b880c244fb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/45805
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Support the keyscan test functionality on stm32.
Note: This is enabled by default so that it continues to build. But it
is unlikely that we will want this in a shipping image. I suggest we add
the facility for a dev build.
Secondly, the stack has to be larger due to a printf (which admittedly I
could just remove). Should we make the stack size conditional on the
CONFIG? Seems a bit ugly, on the other hand we don't want to waste IRAM.
BUG=chrome-os-partner:12179
BRANCH=none
TEST=manual for now:
On snow:
./ectool keyscan 20000 key_sequence.txt
See that the test passes.
Change-Id: Ic441ca0bde1be9589a924374605e2f146d16f423
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/35118
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This reduces memory footprint.
BUG=chrome-os-partner:15714
BRANCH=none
TEST=system still boots; 'waitms 1500' prints watchdog error dump
Change-Id: Ieb0248a34655514b03d919cc36c2b369691da716
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36937
Reviewed-by: Simon Glass <sjg@chromium.org>
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Adds a new HOOK_TICK event which is called every 250ms (LM4) or 500ms
(STM32). This will be used to consolidate a number of tasks which do
small amounts of work infrequently, and previously needed their own
task functions.
This CL adds the tick task; subsequent CLs will consolidate watchdog
and other tasks into tick hooks.
BUG=chrome-os-partner:15714
BRANCH=none
TEST=taskinfo shows TICK task as lowest priority
Change-Id: I9068ee99d56a5bf5c12afd86ad51998c013f4954
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36908
Reviewed-by: Simon Glass <sjg@chromium.org>
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Increase stack size slightly for vboot hash task since the vboot
SHA256 function allocates ~300 bytes of stack data. Reduce stack size
for watchdog, power LED, and a few other tasks with simple call trees
where we can be sure an error path isn't going to blow past the
reduced stack.
This frees up ~1KB of RAM on STM32.
BUG=chrome-os-partner:13814
BRANCH=all
TEST=boot system; shmem should show more unused RAM; taskinfo should show
tasks still have unused stack
Change-Id: I47d6b77564a0180d15d86667cc0566a8919b776e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32608
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Activate the VBOOT code to compute the SHA256 hash of the RW partition
of the EC firmware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On Snow, reset the EC and see the hash is computed at startup.
Change-Id: Id1930f823ef516e459b4905c7d0f301568fddf0f
Reviewed-on: https://gerrit.chromium.org/gerrit/29279
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
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This change contains a basic charging loop that follows Chromium
battery charging flow. The temperature range constants, loop delay
time will be move to battery pack later.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9724,9757,9759
TEST=manual, uart console
Plug AC adapter:
> pmu event: 0000000000001110
[batt] state discharging -> idle
[batt] state idle -> charging
> battery
I: 0x04fd = 1277 mA(CHG)a
Unplug AC adapter:
> pmu event: 0000000000000110
[batt] state charging -> idle
[batt] state idle -> discharging
> battery
I: 0xffcb = -53 mA(DISCHG)
Change-Id: Ifed594d78c0ed08c5e4821a9c8581c1a87526729
Reviewed-on: https://gerrit.chromium.org/gerrit/25618
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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Put the power LED in the right state (off, on, breathing) depending on
the AP state (off, running, suspending).
The power LED is connected to GPIO B3.
The AP suspend detection is done through GPIO A7.
(so we no longer configure it as SPI alternate function)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10647
TEST=on Lucas DVT, boot/stop the board and see the LED on and off.
Change-Id: I42121aacab35e9da7a751dc9f56bcc5af7850783
Reviewed-on: https://gerrit.chromium.org/gerrit/25880
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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This also updates the communication protocol between the EC and the AP in a
non backward compatible way.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=on Daisy with updated kernel driver, use the keyboard in ChromeOS
Change-Id: I5a50e9a74b9891153a37ea79318c8a66a1b0c5ca
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Mostly stolen from Daisy.
Notable differences:
- No SYSCFGEN required for external interrupts ?
- No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available
--> CODEC_INT and ENTERING_RW signals are missing
BUG=None
TEST=Tested on ADV2/Snow, able to see EC serialconsole
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
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