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* stm32: Implement keyscan test infrastructureSimon Glass2012-10-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Support the keyscan test functionality on stm32. Note: This is enabled by default so that it continues to build. But it is unlikely that we will want this in a shipping image. I suggest we add the facility for a dev build. Secondly, the stack has to be larger due to a printf (which admittedly I could just remove). Should we make the stack size conditional on the CONFIG? Seems a bit ugly, on the other hand we don't want to waste IRAM. BUG=chrome-os-partner:12179 BRANCH=none TEST=manual for now: On snow: ./ectool keyscan 20000 key_sequence.txt See that the test passes. Change-Id: Ic441ca0bde1be9589a924374605e2f146d16f423 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35118
* Watchdog is reloaded by HOOK_TICK, not its own taskRandall Spangler2012-10-301-1/+0
| | | | | | | | | | | | | This reduces memory footprint. BUG=chrome-os-partner:15714 BRANCH=none TEST=system still boots; 'waitms 1500' prints watchdog error dump Change-Id: Ieb0248a34655514b03d919cc36c2b369691da716 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36937 Reviewed-by: Simon Glass <sjg@chromium.org>
* Add tick taskRandall Spangler2012-10-301-0/+1
| | | | | | | | | | | | | | | | | | | Adds a new HOOK_TICK event which is called every 250ms (LM4) or 500ms (STM32). This will be used to consolidate a number of tasks which do small amounts of work infrequently, and previously needed their own task functions. This CL adds the tick task; subsequent CLs will consolidate watchdog and other tasks into tick hooks. BUG=chrome-os-partner:15714 BRANCH=none TEST=taskinfo shows TICK task as lowest priority Change-Id: I9068ee99d56a5bf5c12afd86ad51998c013f4954 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36908 Reviewed-by: Simon Glass <sjg@chromium.org>
* Use CONFIG_TASK_VBOOTHASH instead of CONFIG_VBOOTRandall Spangler2012-10-231-3/+0
| | | | | | | | | | | | | | | This fixes build breaks in 'make tests'. BUG=none BRANCH=none TEST=make tests (note that this still fails due to other problems; will fix those in a followup CL) Change-Id: I5b5ce52ed6e44ade6051e0a091a6699c0454d61a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36353 Reviewed-by: Simon Glass <sjg@chromium.org>
* Hook functions no longer return valuesRandall Spangler2012-10-231-8/+3
| | | | | | | | | | | | | | | Previously, all hook functions returned EC_SUCCESS, which was meaningless because nothing ever looked at the return value. Changing the return value to void saves ~100 bytes of code size and an equal amount of source code size. BUG=none BRANCH=none TEST=code still builds; link still boots Change-Id: I2a636339894e5a804831244967a9c9d134df7d13 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36372
* tpschrome: AC detection is board specific.Vincent Palatin2012-09-201-0/+33
| | | | | | | | | | | | | | | | | | | | | | the PMU VACG signal used to detect AC state is connected to a GPIO, so it's a board specific configuration. On top of that, Daisy variants have custom logic on that line which is not present on the next boards, so we need to update it before doing BSP for next-gen boards. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:14313 TEST=make BOARD=snow && make BOARD=daisy on snow EC console, type "pmu" command with AC plugge and unplugged, see that the "ac gpio" line reflects the right value. BRANCH=none Change-Id: If1e19b89b2f2de45d8dddc8340931e56c5f7f0a5 Reviewed-on: https://gerrit.chromium.org/gerrit/33630 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* spi: Rewrite driver for new protocol, better performanceSimon Glass2012-09-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old spi driver has atrophied in various ways. It doesn't support the new protocol and does not build either. Rewrite the driver to: - Use dma for reception (rather than just reception) - This makes message reception more robust and allows us to process the new multi-byte commands - Add timeouts for rx and tx so that we don't wait forever - Increase buffer sizes to deal with new larger messages - Always send a preamble byte regardless of SPI clock speed (previously above 10MHz we sometimes miss this) - Use the NSS line to delineate transactions. When it drops, a transaction is starting. When it rises the transaction is immediately terminates regardless of state. This keeps the AP and EC in sync even in the event of timeouts, bus errors and other oddities. - Implement the new protocol which has a checksum, version byte, etc - Set up tx dma in advance and kick it when ready, thus ensuring that a message body is always attached immediately after the preamble - Use the new host_cmd_handle_args structure, which makes things much easier for us, since we don't need globals, and can use the send_response handler to know when a slow command is complete. - Handle the new type of 'slow' commands properly BUG=chrome-os-partner:10533 TEST=manual build and boot to kernel on snow Change-Id: I11767d1a6f045a86f6c9a0b4b1e943b660e4da33 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32076 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Move pending command logic into host_commandSimon Glass2012-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This logic doesn't really belong in drivers, since to enable another driver (like SPI) we must repeat it all. This is tricky if we enable both I2C and SPI. Move the logic into host_command. BUG=chrome-os-partner:10533 BRANCH=none TEST=manual Use U-Boot to test comms status functionality on snow: SMDK5250 # mkbp write rw 40000000 SMDK5250 # mkbp erase rw SMDK5250 # mkbp erase rw Change-Id: I3f90aada80208cd0540be14525f73f980ad33292 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32075 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Switch to variable-size stacksRandall Spangler2012-09-091-9/+10
| | | | | | | | | | | | | | | | | | | | Increase stack size slightly for vboot hash task since the vboot SHA256 function allocates ~300 bytes of stack data. Reduce stack size for watchdog, power LED, and a few other tasks with simple call trees where we can be sure an error path isn't going to blow past the reduced stack. This frees up ~1KB of RAM on STM32. BUG=chrome-os-partner:13814 BRANCH=all TEST=boot system; shmem should show more unused RAM; taskinfo should show tasks still have unused stack Change-Id: I47d6b77564a0180d15d86667cc0566a8919b776e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32608 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* snow: re-configure I2C arbitration pins at AP off/on to fix leakageDavid Hendricks2012-09-071-15/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This (re-)configures the I2C arbitration lines as floating inputs when the AP powers off, and restores them strictly before the AP powers on. This is intended to prevent leakage when the AP is off and arbitration is not needed. This CL does not impact the AP on/suspend case. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:12573,chrome-os-partner:12381 TEST=manual (see notes below) - PA4: SPI1_NSS / AP_CLAIM, input w/ pull-up when AP on - PA6: SPI1_MISO / EC_CLAIM, output when AP is on - Both floating when AP off 8 = input with pull up/down, 4 = floating input, 1 = output AP off (before this CL): > rw 0x40010800 read 0x40010800 = 0x41484144 > gpioget SPI1_NSS 0* SPI1_NSS > gpioget SPI1_MISO 1 SPI1_MISO AP off (after this CL): > rw 0x40010800 read 0x40010800 = 0x44444144 > gpioget SPI1_NSS 0* SPI1_NSS > gpioget SPI1_MISO 0* SPI1_MISO AP on or suspended (before and after this CL): > rw 0x40010800 read 0x40010800 = 0x81484144 > gpioget SPI1_NSS 1* SPI1_NSS > gpioget SPI1_MISO 1* SPI1_MISO Additional testing: - "pmu 10000" and "cros_test i2c" in u-boot only showed the FET2 control changing (as expected). - "pmu 10000" and "while [ 1 ] ; do i2cdump -f -y -r 0-24 4 0x48 b ; done" and ran "suspend_stress_test" for a couple dozen iterations. The registers only changed as expected (FET1 and FET6 turned off when suspending). Change-Id: I72f5cb1883d01b1faad6c2db65dfa09d477e1885 Reviewed-on: https://gerrit.chromium.org/gerrit/32078 Commit-Ready: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* Snow: Dont hang when trying to pmic-reset boardCharlie Mooney2012-08-311-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Old Snow board (non-MP) don't have the capability to hard-reset their pmics unless they've been manually fixed to do so. This means that if you have an old board, with a new copy of the EC on it and it tries to hard-reset the system, it will hang forever and trigger the watchdog. Since there's no way for the EC to check if the hardware fix exists on its board, this adds a timeout after trying to reset. If the board has the fix, it will reset before the timeout expires. Otherwise, it will print a warning message before returning, to prevent it hanging. Additionally, it also fixes the places board_hard_reset() is called to deal with the new possibility of it returning. BUG=chrome-os-partner:13508 TEST=On a machine with the hardware rework and one without it, go to the EC console and run "pmu reset" to try and force a reset. The one with the fix should reset immediately, and the one without should warn you that it tried (and failed) to reset. BRANCH=snow Change-Id: I493122ee4da539f363a31f624ab9dd7db8068ec8 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Use new panic stack on all platformsRandall Spangler2012-08-311-1/+0
| | | | | | | | | | | | | | | | Now that the panic stack goes at the end of RAM, there's no overhead to using it on all platforms. When it was a dedicated block of memory, we needed to turn it off on some low-RAM platforms (e.g. Snow). BUG=chrome-os-partner:7466 TEST='crash divzero' or 'crash unaligned'; should print dump and reboot BRANCH=all Change-Id: Iddfeb134e237538215df51abe4e16ee831b3ae2d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32037 Reviewed-by: Simon Glass <sjg@chromium.org>
* Snow must assert ENTERING_RW GPIO when jumping between imagesRandall Spangler2012-08-301-1/+1
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:13439 BRANCH=snow TEST=manual 1. Ctrl+Refresh+Esc; should go to INSERT screen 2. Ctrl+D; should show TODEV (this confirms it's still possible to get into dev mode the right way) 3. From EC console, 'sysjump rw' 4. Ctrl+D; should NOT show TODEV (this confirms the bug is fixed) Change-Id: Ic4879cb0a7fc47527eac1a5a727f3225744ff880 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31932
* snow: Don't turn on SPI clockDoug Anderson2012-08-301-3/+0
| | | | | | | | | | | | | | We're not using SPI on snow so no reason to clock it on. BUG=None TEST=Things still boot BRANCH=snow Change-Id: I14fe227ba75501dea28f6a91645c14ae433aac2d Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31957 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* snow: re-factor i2c initDavid Hendricks2012-08-302-15/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-factors i2c initialization to simplify it and make it follow the correct order. This is intended to fix a bug where the I2C lines could be driven low for no good reason on EC startup, potentially causing issues with other devices. The ordering should be: 1. Setup pins as inputs on EC startup. 2. Initialize I2C module(s) 3. Re-configure pins as alternate function. (Thanks to dianders for pointing out this bug) Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:13443 TEST=Tested by examining scope traces during EC reboot Change-Id: Ibb845f3fd538da387132b1c822929f8613de077d Reviewed-on: https://gerrit.chromium.org/gerrit/31647 Commit-Ready: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
* Snow: Adding in EC ability to hard reset pmicCharlie Mooney2012-08-282-16/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By pulling line gio_A15 high, you can for a hard reset of the pmic after the stuff resistor is changed. This change adds a function that you can call from the EC and trigger this event (board_hard_reset). The user has access to this command over the EC console by running "pmu reset" and it will force the emergency reset. The board_hard_reset function is used in the pmu's reset code. Whenever it is trying to initialize or shut down the pmu, it resets many or all of its registers over i2c. If the i2c commands fail to get a response from the pmu, the EC will now force a hard reset of the system, which restores everything, allowing for a restart to fix any situation where the pmu has gotten its configuration trashed. BUG=chrome-os-partner:12913 TEST=boot the machine. From EC console check the pmic's register values, then alter them. Run "pmu reset" to force a reset, and check the values again. They should be safe values, which you can confirm by powering on the AP. Repeat this from various starting states: only the EC on, AP on as well, and setting various registers to 0x00's and 0xff's. To stress test the hard-reset ability from the EC's POV, run while true; do echo "pmu reset"; sleep 5; done | cu -l DEVICE -s 15200 BRANCH=snow Change-Id: I911fb9623a7c106d1f993ee4681258c05d4dedae Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31524 Reviewed-by: Simon Glass <sjg@chromium.org>
* snow: toggle pull-up on PA7 (SUSPEND_L) on power on/offDavid Hendricks2012-08-281-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds hooks to re-configure SUSPEND_L (GPIO PA7) when the system turns on/off. When the system is turned on, PA7 will have its internal pull-up enabled. This is required since SUSPEND_L is driven by an open- drain buffer. When the AP is off, we can disable the pull-up (configure PA7 as floating input) to reduce leakage. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:12700,chrome-os-partner:13200 TEST=see notes below 1. Dump GPIO_A CRL when system is off: read 0x40010800 = 0x41484144 2. Dump GPIO_A CRL when system is on: read 0x40010800 = 0x81484144 3. Dump GPIO_A when system is put into suspend: read 0x40010800 = 0x81484144 4. Resume, see power LED react quickly. 5. Soft poweroff, dump GPIO_A CRL: read 0x40010800 = 0x41484144 Change-Id: I62f02324a2a1fbfb6eff539fc6fdc35a035fa020 Reviewed-on: https://gerrit.chromium.org/gerrit/31315 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* Support battery cut-off mechanism for factory.Louis Yung-Chieh Lo2012-08-281-0/+3
| | | | | | | | | | | | | | | | | | | The cut-off command is manufacturer-specific. Thus the logic is implemented in gas gauge IC code. For those boards using this gas gauge, define the CONFIG_BATTERY_BQ20Z453 in board.h. BUG=chrome-os-partner:12962, BRANCH=snow Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> TEST=Tested on snow ectool batterycutoff ; expect system is off immediately ; if AC power is not connected. Change-Id: Idd290c76439f3263c1c812b236b79623878f73b2 Reviewed-on: https://gerrit.chromium.org/gerrit/31466 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Ready: Yung-Chieh Lo <yjlou@chromium.org> Tested-by: Yung-Chieh Lo <yjlou@chromium.org>
* snow: Change TPSCHROME fastcharge timeout to 6 hoursRong Chang2012-08-281-5/+6
| | | | | | | | | | | | | | | | | | When battery temperature t in range 0C to 10C, default charging current is 50%. And it will take longer than 3 hours to charge battery from 0% to full. Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:13172 TEST=manual Check pmu register 0x4. FASTCHARGE bits[4:2] should be 0b100. Change-Id: I133acee21c0886b0739b4b41766ca077bb4babbc Reviewed-on: https://gerrit.chromium.org/gerrit/31458 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Ignore TPSCHROME NTC reading in T40 rangeRong Chang2012-08-281-0/+10
| | | | | | | | | | | | | | | | | | | | | | | TPSCHROME NTC readings didn't match battery gas gauge temperature. The charging was turned off by TPSCHROME too early, and was resumed too late. This change disables TPSCHROME thermal protection in T40 by set charging voltage and current to 100%. Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:12221 BUG=chrome-os-partner:13171 TEST=manual Check pmu register settings. VSET/ISET are equal in T23,T34,T40 ranges. Change-Id: Ic60cc2bf606ed02496aad80b02360a19efafd3c0 Reviewed-on: https://gerrit.chromium.org/gerrit/31457 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* i2c: Enable arbitration GPIOs only when activeSimon Glass2012-08-272-4/+9
| | | | | | | | | | | | | | | | | | | | | | | Only setup the arbitration GPIOs when CONFIG_ARBITRATE_I2C is set. BUG=chrome-os-partner:13064 BRANCH=snow TEST=manual build and boot on snow On the EC: > pmu 1000 In U-Boot: cros_test i2c See that there are no failures. Change-Id: I8a7724700ff79406527c3db8708833728eb9a978 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31305
* Make AC status feature optional at compile timeSimon Glass2012-08-272-1/+12
| | | | | | | | | | | | | | | | This feature is not actually used on current platforms. Avoid setting up the GPIO unless it is specifically enabled. BUG=chrome-os-partner:13064 BRANCH=snow TEST=manual build and boot on snow. See the AC power GPIO does not change when un/plugging power. Change-Id: I6731625a19f30f6dd35471b126f3083b39747203 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31304 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Fix poweron state machine in the ECPuneet Kumar2012-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing state machine does the following: - when power button is pressed it 1. powers on the AP 2. sets a timer of 1 sec and then 3. waits for power button to be released When the timer fires it checks xpshold is set by the AP and if so it clears the pwron signal (which is used by the AP to detect power button is pressed). The problem occurs when the user holds the power button for more than a second. The AP turns on xpshold, then notices that pwron is still on and subsequently powers down because it thinks the power button is pressed. When the button is finally released, since it was held down for more than a second, the timer routine notices that xpshold is not on and therefore shuts down the system. Another problem found while analysing this state machine is that loop checking for poweroff only triggers on the rising edge of xpshold. This means that if the AP powers down the EC might miss a possible power event. Here is the proposed fix: When the power button is pressed the EC will: 1. power on the AP 2. Check for xpshold to be asserted with a 1 sec timeout 3. If uboot is healthy xpshold should come on pretty quickly; the EC then waits for the power button to be released in less than 8 seconds 4. If the power button is released then the EC waits for power off events. 5. If the power button is not released it waits for upto 8 seconds before turning off the AP. The added wrinkle is how to address a borked uboot case. In the case where xpshold doesn't come on in < 1 second, the EC will allow the AP to stay on for upto 16 seconds so that USB boot can finish. The user must hold the power button down until uboot boots and sets xpshold. The assumption here is that USB boot takes < 16 seconds. BUG=chrome-os-partner:12748 TEST="follow instructions in bug report" Change-Id: I5b582a6c3ae3449238e2813e4a581bd8f92dd846 Signed-off-by: Puneet Kumar <puneetster@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31291 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Snow: i2c arbitration cleanup (suspend)Charlie Mooney2012-08-231-9/+5
| | | | | | | | | | | | | | | | | | | | | | | The ec used to have to check the state of the AP since it would leave the arbitration lines when it suspended. That meant you couldn't trust the arbitration lines without checking the power state. Now the AP pulls the arbitration lines high when it suspends, so it no longer needs to test this when trying to acquire master. BUG=chrome-os-partner:12460 TEST=First, on the EC console run "battery" and "pmu" to make sure they work. Then repeat those steps after putting the AP in suspend by running powerd_suspend, they should still work. Then shutdown the machine entirely and try them again. Note: pmu needs the AP to be on to work, so if it fails here that's okay, just make sure it's not an arbitration error. BRANCH=snow Change-Id: I335156bbce4888949111f74e8a83fe9d184a7a63 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/30906 Reviewed-by: Jon Kliegman <kliegs@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* snow: configure USART Rx as an input with pull resistorDavid Hendricks2012-08-211-2/+10
| | | | | | | | | | | | | | | | | | | | | | USART1 has always had its Tx and Rx pins configured as "alternate function output". However, this turns out to be incorrect since there is no concept of an AF input on the STM32F. Instead, the Rx pin should be configured as an input (and the Tx remains an AF output). This also simplifies the console resume code since we only need to enable/disable the interrupt rather than reconfiguring the GPIO. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:12223 TEST=flashed on snow, EC console works Change-Id: Ia92dbbac16fc55d0db62381dfb487aeb4f4121b4 Reviewed-on: https://gerrit.chromium.org/gerrit/30941 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* snow/stm32: re-configure power LED on the fly (input vs. pwm)David Hendricks2012-08-172-5/+32
| | | | | | | | | | | | | | | | | | | | | | | Usually the power LED is driven by the PWM mode so that its nominal brightness can be set to a "soft" on value. However, when the LED is to remain off the LED should be switched to floating input mode. This reduces voltage leakage. This CL updates the power_led_task to configure the LED however is appropriate and adds board functions to re-configure the GPIO. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:12381 TEST=LED responds as expected in suspend and on/off states, also tested that leakage is reduced with multimeter Change-Id: If90ac78aaffe7358cce80dd02ec1423c2cb4f664 Reviewed-on: https://gerrit.chromium.org/gerrit/29705 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* daisy: Modify charging flow to comply charging specificationRong Chang2012-08-161-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This change corrects charger interrupt event handling, charger enable gpio, battery full condition, EC deep sleep mode support when AC unplugged, and lid controlled power off. Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:12573,12574,12575 TEST=manual - ec console command 'gpioget': - SPI1_MISO should be 0 when AP off - CHARGER_EN should be 0 after AC unplugged - charging led should be off after AC unplugged - when battery remaining charge < 3%, system should be powered off without AC. - ec console command 'sleepmask 0', turn off AP: - deep sleep only when AC unplugged Change-Id: I0f63835dae67d90de7a8c8c6c3537ca9a16faed4 Reviewed-on: https://gerrit.chromium.org/gerrit/30316 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Handle IRQ from TPS65090, pass AC status to APSimon Que2012-08-142-1/+3
| | | | | | | | | | | | | | | | | | | Changes made by this patch: 1. Create IRQ handler for the TPS65090 IRQ. IRQ wakes up charger task. 2. Charger task sets the AC_STATUS GPIO based on the AC status. 3. Initialize PMU at power-on. BRANCH=snow BUG=chrome-os-partner:11739 TEST=Power on the system, with servo v2 connected to EC console. Plug and unplug AC. The IRQ handler should be triggered. Change-Id: Ice23411c275111fdb56d2c47ba28c3c44dee4d71 Signed-off-by: Simon Que <sque@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29914 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* stm32f100: implement low power modeVincent Palatin2012-08-091-0/+3
| | | | | | | | | | | | | | | | | | | | | When the AP is not running and we have enough time go to STOP mode instead of simple idle. The EC consumption should drop from 12mW to a few mW. This is currently not activated by default, you need to type "sleepmask 0" in the EC console to activate it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8866 TEST=on Snow, check the software is still working properly when STOP mode is activated and measure power consumption on 3v_alw rail. Change-Id: I231d76fe6494c07b198c41694755b82d87c00e75 Reviewed-on: https://gerrit.chromium.org/gerrit/29315 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Remove signature-based vboot supportRandall Spangler2012-08-071-1/+0
| | | | | | | | | | | | | | | | | | | | Superseded by EC software sync (hash-based). Sig-based vboot was correctly implemented, but ended up being too slow to be useful given the limited processing power of the EC chips, and we also couldn't come up with a manageable way to handle A/B autoupdate of signed EC firmware. This change and an associated vboot_reference change shrinks the EC binary by ~2KB. BUG=chrome-os-partner:11232 TEST=build link,snow; boot link and check that 'hash' command still works. Change-Id: I3f03ae2d0a4030977826980d6ec5613181e154c2 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29496 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* snow daisy: compute RW firmware hashVincent Palatin2012-08-062-0/+5
| | | | | | | | | | | | | | | | | Activate the VBOOT code to compute the SHA256 hash of the RW partition of the EC firmware. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=On Snow, reset the EC and see the hash is computed at startup. Change-Id: Id1930f823ef516e459b4905c7d0f301568fddf0f Reviewed-on: https://gerrit.chromium.org/gerrit/29279 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* snow: remove debug features to save RAMVincent Palatin2012-08-061-2/+2
| | | | | | | | | | | | | | | | | | We need a bit more internal RAM for verified boot hash feature, let's de-activate RAM hungry debug features. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:12271 chrome-os-partner:10895 TEST=make BOARD=snow check RAM size with CONFIG_VBOOT and CONFIG_VBOOT_HASH activated. Change-Id: I4d1d6c0f99a8b03011af6eb2d73455beba93c535 Reviewed-on: https://gerrit.chromium.org/gerrit/29278 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* snow: add keypress noise suppressionDavid Hendricks2012-08-011-0/+7
| | | | | | | | | | | | | | | | | | | This was implemented for Daisy a long time ago, but left out on Snow due to some confusion. GPIO remapping is already handled because PD1 and PD0 (which is used for ENTERING_RW) are remapped together. So all we need here is the board_keyboard_suppress_noise() function definition which gets called from the keyboard scanning code whenever a change is detected. BUG=none TEST=Verified using a scope that CODEC_INT line is driven when a key is pressed (15us pulse) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ifd358eb89a9547c4f4b9536b8922c93d2c3b77a0 Reviewed-on: https://gerrit.chromium.org/gerrit/28989 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Snow has write protect pin (PB4) wired to EC.Louis Yung-Chieh Lo2012-08-012-8/+2
| | | | | | | | | | | | | | Intend to keep fake_wp functions for test. BUG=chrome-os-partner:9986 TEST=build only (success on link/snow/daisy/bds). Have no hardware to test. Change-Id: I1e2ae923790d65b6c95819f5274dbe8c7f254429 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28793 Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "Enable snow I2C host auto detection"Rong Chang2012-07-302-40/+0
| | | | | | | | | | | | | | | | This reverts commit 024c44cd96bf97e81d4d3af45a0f0cb0ef1425a0. board/snow/board.c board/snow/board.h Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:10622 TEST=build snow ec image without warning Change-Id: I65660383873907722933b41249e17dd1f83d8fde Reviewed-on: https://gerrit.chromium.org/gerrit/28698 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Set TPSCHROME temp range configurationRong Chang2012-07-291-22/+30
| | | | | | | | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:11627 TEST=manual Check pmu registers under uart console: "pmu" TPSCHROME version < 3: reg(7) == 0xbd reg(8) == 0xfd TPSCHROME version >= 3: reg(7) == 0xbf reg(8) == 0xff Change-Id: Ifeda54aa142b362aa224575c55220913b0ee7436 Reviewed-on: https://gerrit.chromium.org/gerrit/28587 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Fix I2C arbitration timeout when chipset is suspendedRong Chang2012-07-171-2/+3
| | | | | | | | | | | | | | | When system is off or suspended, board_i2c_claim() should not wait for AP's signal. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:11285 TEST=manual Put AP into suspend Type 'i2c r 0x90 0' and see that no arbitration error is obtained. Change-Id: I22243457fc29bc6c88f413ce0660c700e54f6761 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27498
* Get AC state from GPIO instead of PMURong Chang2012-07-112-0/+2
| | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=none TEST=manual plug and unplug the ac adapter, check charging state Change-Id: I933976d79bbd2da59449f0b9208656897713ebf2 Reviewed-on: https://gerrit.chromium.org/gerrit/27146 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* snow/daisy: enable lid openDavid Hendricks2012-07-071-1/+3
| | | | | | | | | | | | | | | | | This enables lid open on Snow (and presumably Daisy). For now we only care about interrupting on lid open (rising edge of LID_OPEN) to turn on the AP. BUG=chrome-os-partner:9708 TEST=Tested on Snow Signed-off-by: David Hendricks <dhedndrix@chromium.org> Change-Id: I8f6cb4dd9d3ebc0380c8a5e7a3f2ce967e3eff48 Reviewed-on: https://gerrit.chromium.org/gerrit/26648 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org>
* snow: Add pmu command to print out pmu registersSimon Glass2012-07-051-0/+2
| | | | | | | | | | | | | | | | This command is primarily useful for testing, since it repeatedly hammers the i2c bus. Enable the command on snow for now. BUG=chrome-os-partner:10888 TEST=manual: run 'pmu 100' on snow and see that it displays the correct output. Change-Id: I36c15af195d17f67dff4c05559d1756693a65c19 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26829 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* i2c: Add delay after bus release, print an error on failureSimon Glass2012-07-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the delay for bus claim to 100ms, since in testing with the AP requesting the bus constantly, I was able to make a 50ms timeout happen after about 3000 transactions. With 100ms, the timeout happens only once in 130,000 i2c transactions with both AP and EC fully loading the i2c bus simulataneously. The bus claim failure should never happen, but in case it does, print an error. Also make sure we delay for a bit, to allow the AP to see the change in state. BUG=chrome-os-partner:10888 TEST=manual: build for all boards boot on snow, test: on AP: $ while true; do i2cdump -f -y 4 0x48; done >/dev/null on EC: $ pmu 10000 See that the machine operates normally with no lock-ups, etc. Change-Id: I9a48144f560c596429c525a42c77ac41ec095ec0 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26828 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* snow: Enable I2C bus arbitration on host portSimon Glass2012-07-051-0/+1
| | | | | | | | | | | | | | | | | | | | Enable this feature so that we can be a bus master on the I2C host port when the AP is not using it. BUG=chrome-os-partner:10888 TEST=manual: build for all boards boot on snow, test that: - keyboard still works in U-Boot - battery charging is enabled - U-Boot can see TPSCHROME - keyboard works in kernel - kernel reports battery levels correctly Change-Id: Ie17e38feea721355a738d85f0295ed5f145c8a0c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26826 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Enable help debug features on all boardsSimon Glass2012-07-041-0/+2
| | | | | | | | | | | | | This ensures that we have all available help enabled. For the moment this is useful for development. We may revisit later. BUG=chrome-os-partner:10895 TEST=manual: build for all boards Change-Id: I721e09995959638660ff417dd9420200e2e1a703 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26173
* Initialize PMU default settings using board configurationRong Chang2012-07-032-1/+43
| | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:11749 TEST=on snow with fully discharged dead battery plug ac power and check if it can charge to full Change-Id: Ie90255614bff879780edbd2bf1fc77bf8e2c04c8 Reviewed-on: https://gerrit.chromium.org/gerrit/26674 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* snow: Implement I2C arbitrationSimon Glass2012-07-021-0/+71
| | | | | | | | | | | | | | | | | | | | | | | Use two suitable GPIOs to implement a simple arbitration scheme. Each side owns one of the GPIOs, which are normally pulled high. When one side wants to use I2C as a master, it pulls its GPIO low, waits for a short period to make sure that the other side is not also pulling its GPIO low, and then goes ahead with the transaction. When the transaction is over, the GPIO is released, thus freeing the I2C bus up for use by the other end. For simplicity the terminolgy used here is EC for us, and AP for the other end. BUG=chrome-os-partner:10888 TEST=manual: build for all boards boot on snow (cannot test i2c as it is broken) Change-Id: I97d9fbd5aba8248c8c1240baaec17db22860665c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26142
* Daisy/Snow: Drive power LED with PWMDavid Hendricks2012-07-022-2/+9
| | | | | | | | | | | | | | | | | | | | This drives the power LED for Snow (PB3) using TIM2 in PWM mode. Since timer setup and manipulation is STM32-specific, the power LED logic moved to to chip/stm32/power_led.c. This also adds a "powerled" console command for testing. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=chrome-os-partner:10647 TEST=Tested on Snow with powerled command, compiled for Daisy Change-Id: I5a7dc20d201ea058767e3e76d54e7c8567a3b83c Reviewed-on: https://gerrit.chromium.org/gerrit/26267 Commit-Ready: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* Fix multiple charging issues on snowRong Chang2012-07-011-2/+3
| | | | | | | | | | | | | | | | | | | This change fixes mutiple snow charging issues. Including: - disable i2c host auto selection - i2c_read8 got wrong output value - pmu CHARGE_EN control workaround Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:11010 TEST=Only test on snow dvt with AP turned off plug/unplug ac adapter and check charging led check console command 'battery' Change-Id: I29d554b3daa4cfc538bd5bf5ba5233976d381861 Reviewed-on: https://gerrit.chromium.org/gerrit/26529 Tested-by: Rong Chang <rongchang@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32: Use SPI ports for i2c arbitrationSimon Glass2012-06-282-1/+3
| | | | | | | | | | | | | | | We plan to use two of the SPI ports (NSS and MISO) for arbitration on the i2c host interface. In preparation for this, add the extra GPIO to the table, and change NSS to a pull-up. BUG=chrome-os-partner:10888 TEST=manual: build for all boards boot on snow Change-Id: I70962b25f371a4ca54f0ce67dcf0bc33b1cc8c47 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26139
* TPSChrome charging loopRong Chang2012-06-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change contains a basic charging loop that follows Chromium battery charging flow. The temperature range constants, loop delay time will be move to battery pack later. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9724,9757,9759 TEST=manual, uart console Plug AC adapter: > pmu event: 0000000000001110 [batt] state discharging -> idle [batt] state idle -> charging > battery I: 0x04fd = 1277 mA(CHG)a Unplug AC adapter: > pmu event: 0000000000000110 [batt] state charging -> idle [batt] state idle -> discharging > battery I: 0xffcb = -53 mA(DISCHG) Change-Id: Ifed594d78c0ed08c5e4821a9c8581c1a87526729 Reviewed-on: https://gerrit.chromium.org/gerrit/25618 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Only one RW image is now the defaultRandall Spangler2012-06-261-0/+4
| | | | | | | | | | | | And if RW B isn't enabled, it's not even linked. BUG=chrome-os-partner:10881 TEST=on link, should be no B image, and 'sysjump B' should fail On BDS, still should be A and B images Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Icb2af07881cc7e28b9b877f45824486a22fde8d7 Reviewed-on: https://gerrit.chromium.org/gerrit/26116
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