| Commit message (Collapse) | Author | Age | Files | Lines |
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Setting up numbers for Battery info like input current limit,
Battery voltage, temperature limits as per the actual battery spec.
BUG=None
TEST=Tested on Braswell Ref Design
BRANCH=None
Change-Id: I66c3dfe6166d03d2cb79d80a887168f08753d22d
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/260631
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Add physical flash interface for read / write / protection of external
SPI on mec1322.
BUG=chrome-os-partner:36167
TEST=Manual on glower:
flashread 0xf000 0x200 --> dumps 0xff
flashwrite 0xf000 0x200
flashread 0xf000 0x200 --> dumps write pattern
flasherase 0xf000 0x1000
flashread 0xf000 0x200 --> dumps 0xff
spi_flash_prot 0 0x10000
flashinfo --> shows first 64KB protected
spi_flashwrite 0xf000 0x200 --> access denied
spi_flashwrite 0x1f000 0x200 --> OK
flashread 0x1f000 0x200 --> dumps write pattern
BRANCH=None
Change-Id: I2cb20a49934999fc0dd9b3425eb99708711637c5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/257132
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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W25X40 uses a different protection register encoding than our existing
W25Q64 code. Move the SPI ROM option to a config, and add support for
the new part.
BUG=chrome-os-partner:37688
TEST=`make buildall -j`. W25X40 protection code tested in a subsequent
commit.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaaeabf42c6c62c20debc91afd2cf8671c14244c8
Reviewed-on: https://chromium-review.googlesource.com/258440
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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For boards without a shared SPI, it's reasonable to use a SPI flash
smaller than 1MB. Change the script to allow this.
BRANCH=None
BUG=chrome-os-partner:35308
TEST=Build strago and check the size of ec.spi.bin.
Change-Id: Iabf7065d158be5f82c55e182e430858a12b18b6e
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/241111
Tested-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
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circuitry.
BUG=None
TEST=make -j buildall
BRANCH=None
Change-Id: I88fa219cd9e573c1544400d24d00c4fdec93840f
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/237272
Reviewed-by: Vic Yang <victoryang@chromium.org>
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BUG=None
TEST=Tested on Braswell Reference Design
BRANCH=None
Change-Id: Idc064e1af837e5e6a1bf4174885bd10624f463d2
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226297
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Divya Jyothi <zdivyajyothi@gmail.com>
Tested-by: Divya Jyothi <zdivyajyothi@gmail.com>
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Add another variable PROJECT_EXTRA which chips and boards can use to
add additional prerequisites to the default all target
Add rules for creating ec.spi.bin to package the ec firmware for
strago
BUG=None
BRANCH=None
TEST=Tested on Braswell Ref Design Board
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: icarus sparry <icarus.w.sparry@intel.com>
Change-Id: I4fb9f1275dc5bc2987b6abf5d45b0baf363c0d7a
Reviewed-on: https://chromium-review.googlesource.com/226305
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com>
Tested-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
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Modules that are enabled are listed below:
- Power Sequencing
- Keyboard Scan and Protocol
- LPC to support Keyboard
- Power Button Task
ec.spi.bin has to be generated manualy using
pack_ec.py
BUG=None
BRANCH=None
TEST=Tested on Stargo-Proto board
Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226303
Reviewed-by: Vic Yang <victoryang@chromium.org>
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