delta/coreboot/chrome-ec.git - review.coreboot.org: chrome-ec.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	hatch: refactor PD_MAX_VOLTAGE/PD_MAX_CURRENT/PD_MAX_POWER/PD_OPERATING_POWER/	Josh Tsai	2019-12-06	1	-0/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	1) The four config is determined by board, move it into board.h. 2) Update the config variables above for stryke. BUG=b:145257655 BRANCH=hatch TEST=make buildall Change-Id: I1dd6a4f2a78b5196006821bc5d2686f68206c2e1 Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1950270 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
*	stryke: Assign SYS_RST_ODL to GPIOC5 and make sure EC_RST_ODL is LOCKED	Josh Tsai	2019-12-05	1	-2/+13
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	There is an error where SYS_RST_ODL is assigned to GPIO02 where it is actually assigned to GPIOC5 in the schematics. BUG=b:145369657 BRANCH=none TEST=make buildall Change-Id: I26a4b37baf160714bc07d8f9eb5df7234e76d96e Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948701 Reviewed-by: Ruby Lee <ruby_lee@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
*	stryke: Initial EC image	Dtrain Hsu	2019-12-03	7	-0/+1019
	The starting point for the stryke EC image (Auto-Generated by create_initial_ec_image.sh version 1.0.0). BUG=b/145101696 BRANCH=none TEST=make BOARD=stryke Change-Id: Id4546da9d79d6692cd66dc6b44f46973e8c50e58 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935472 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Commit-Queue: Shelley Chen <shchen@chromium.org>